JPH06326330A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To manufacture a high-output semiconductor device having excellent heat radiating characteristics at a high yield. CONSTITUTION:The semiconductor device has such a structure that a transistor cell 15-is mounted on a via hole 13 filled with a metal 13a or another low- thermal-resistance substance independently from a semiconductor substrate 1 used at the time of manufacturing the semiconductor device in an island-like state. Therefore, such a structure and process which do not allow the cracking of substrates can be realized even when the substrate thickness in the transistor cell section is reduced to <=30mum with the purpose of improving the heat radiating characteristics of the semiconductor device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to improvement of characteristics of a semiconductor device operating in a high frequency band of several hundred MHz to several hundred GHz.

[0002]

2. Description of the Related Art FIG. 7 shows a conventional MMIC (Monolithic Mic).
FIG. 7 (a) is a perspective view thereof, and FIG. 7 (b) is a cross-sectional view taken along line VIIb-VIIb of FIG. 7 (a). is there. FIG. 8 is a plan view of FIG. 7. In the figure, 1 is a semi-insulating GaAs semiconductor substrate, 2 is a signal input pad, 3 is a signal output pad, 4 is a metal pattern provided on a via hole, 5 is a transistor portion, 5a is a source electrode, and 5b is a drain. The electrodes 5c are gate electrodes. Incidentally, here, the drain electrode 5b and the gate electrode 5c
Are formed so as to interlock with each other as shown in FIG. Also, 5d is the source electrode 5 of each transistor.
air bridge wiring for wiring a and the metal pattern 4, 6
Is an input matching circuit for matching the input signal input from the signal input pad 2, and 7 is an output matching circuit for matching the output signal output from the signal output pad 3. Further, 8 is a via hole which is provided so as to penetrate through the semiconductor substrate 1 and whose inside is filled with metal, 9 is a back metal made of Au, and 10 is n.
This is an operating layer made of a type GaAs layer. This n-type GaAs
The operating layer is formed by epitaxial growth or ion implantation.

The signal input pad 2 is connected to the gate electrode 5c through the input matching circuit 6, the signal output pad 3 is connected to the drain electrode 5b through the output matching circuit 7, and the source electrode 5a is connected to the air bridge wiring 5d and the metal pattern 4. Also, wiring is provided to the back surface metal 9 through the metal inside the via hole 8.

Next, the operation will be described. Conventional MM
In the IC semiconductor device, the heat generated in the transistor portion 5 is radiated through the via hole 8 whose inside is filled with metal and also radiated from the back surface of the chip through the semiconductor substrate 1.

Further, for example, Japanese Patent Application Laid-Open No. 59-172720 discloses a microwave FET in which a hole is formed on the back surface of an element forming portion of a substrate and the hole is filled with metal. FIG. 9 is a view showing a method of filling a through hole of a substrate with a metal according to this conventional technique, and FIG. 10 is a plan view of a microwave FET formed by using this metal filling method.
In the figure, 1 is a substrate, 41 is a lower resist layer, 42 is a metal layer, 42a is the rest of the metal layer 42, 43 is a hole,
44 is an upper resist layer, 45 is a plated metal layer, and 46 is F
ET and 47 are through holes, 55a is a source electrode, 55b is a drain electrode, and 55c is a gate electrode.

In this conventional example, holes 43 are formed between the FETs formed on the surface of the semiconductor substrate 1, and a metal layer 42 is formed in the holes 43 as shown in FIG. As shown in FIG. 9B, the upper resist layer 44 is formed except for the hole 43 and the upper edge thereof, and as shown in FIG. 9C, the metal layer 42 is formed by electroplating using the metal layer 42 as an electrode. After the plated metal layer 45 is formed on the exposed portion of the substrate to a thickness such that the hole 43 is filled, the lower resist layer 41 is formed by the lift-off method.
The upper metal layer 42 and the upper resist layer 44 are removed, and the remaining portion 42a of the metal layer 42 is left in the hole 43 in an integrated manner with the plated metal layer 45, as shown in FIG. 9 (d). , Holes 4 are formed by etching from the back surface of the semiconductor substrate 1.
The through hole 47 is formed so as to be continuous with 3.

Next, the operation will be described. In the microwave FET formed by using the metal filling method of the conventional example, the heat generated in the FET 46 is radiated from the back surface of the chip via the metal filled in the through hole 47.

Although the FET is mounted as the active element in the above-mentioned conventional example, the HBT (Heterojunc.
tionBipolar Transistor, Heterojunction Bipolar Transistor, HEMT (High Electron Mobility Transi)
Stor, high electron mobility transistor), etc.

[0009]

The conventional MMIC semiconductor device is configured as described above, and it is necessary to reduce the thickness of the semiconductor substrate of the transistor portion to about 2 μm to improve the heat dissipation of the element. However, when stress such as thermal stress when soldering the MMIC device at the time of manufacturing is applied to the semiconductor substrate, there is a problem that the semiconductor substrate is cracked or cracked and the element is broken.

Further, in the microwave FET disclosed in Japanese Patent Laid-Open No. 172720/1984, the heat generated in the FET section is radiated through the via hole provided on the back surface of the element, so that the heat radiation performance is improved. It is not necessary to reduce the thickness of the semiconductor substrate in order to improve However, in this conventional example, as shown in FIG. 10, the substrate on which the element is formed and the substrate around it are partially connected. Therefore, when the microwave FET is soldered, thermal stress is FE.
There is a problem that the element is adversely affected by being added to the T portion.

The present invention has been made in order to solve the above-mentioned problems, and a semiconductor device having a good heat dissipation property in which the element is not adversely affected by the thermal stress generated when the device is soldered. It is an object of the present invention to provide a manufacturing method suitable for this device.

[0012]

A semiconductor device according to the present invention comprises a semiconductor substrate, a via hole penetrating the substrate, and a single or a plurality of transistor cells provided on the via hole. The single or plural transistor cells are formed independently of the surrounding semiconductor substrate on the low thermal resistance material filling the inside of the via hole on the substrate main surface side.

Further, in the method of manufacturing a semiconductor device according to the present invention, one or a plurality of transistor cells are formed on a semiconductor substrate, the main surface of the substrate other than the transistor cells is etched to a predetermined depth, A metal film for fixing the transistor cell to the semiconductor substrate is formed between the transistor cell and the semiconductor substrate, and then the metal for fixing the transistor cell only on a portion of the substrate under the region where the transistor cell exists. After forming a via hole by etching from the back side until the film is exposed and separating the transistor cell or cells and the underlying semiconductor substrate from the surrounding substrate, a low thermal resistance material is placed in the via hole. It is designed to be filled.

Also, in the method for manufacturing a semiconductor device according to the present invention, the transistor cell is formed on the semiconductor substrate, the main surface side surface of the semiconductor substrate other than the transistor cell is etched to a predetermined depth, and then the semiconductor substrate is formed. A mask for covering and temporarily fixing the transistor cells is formed on the entire main surface of the semiconductor substrate, and then a mask for temporarily fixing the transistor cells is exposed only on the lower portion of the semiconductor substrate where the transistor cells are present. Until then, a via hole is formed by etching from the back side to separate the transistor cell from the surrounding semiconductor substrate, and then the low heat resistance material is filled in the via hole.

[0015]

In the semiconductor device of the present invention, the transistor cell is provided so as to penetrate the substrate and is provided on the substrate main surface side of the via hole having the low thermal resistance substance filled therein, independently of the surrounding semiconductor substrate. Since it is formed, the substrate thickness of the unit transistor cell part is 3 for the purpose of improving heat dissipation.
Even when the thickness is 0 μm or less, the cracking of the substrate does not occur due to the thermal stress generated during the soldering work of the semiconductor device.

Further, in the manufacturing method of the present invention, a metal film is formed between the transistor cell and the matching circuit substrate, the transistor cell is fixed to the semiconductor substrate, and then only the lower portion of the transistor cell on this substrate is fixed. By etching from the back side until this metal film is exposed,
By forming a via hole to separate the transistor cell from the surrounding semiconductor substrate and then filling the via hole with a low thermal resistance material, the transistor cell is surrounded by a metal filled via hole. It is formed independently from the semiconductor substrate, which makes it excellent in heat dissipation,
Moreover, it is possible to easily manufacture a semiconductor device in which transistor cells are not adversely affected even if stress such as thermal stress at the time of soldering during manufacturing is applied to the semiconductor substrate, without causing the transistor cells to fall apart.

Further, in the manufacturing method of the present invention, a mask for covering and temporarily fixing the transistor cells is formed on the entire main surface side of the semiconductor substrate on which the transistor cells are formed, and the transistor cells on the substrate are present. By etching only the lower part from the back side until the mask for temporarily fixing the above is exposed, a via hole is formed to separate the transistor cell from the surrounding semiconductor substrate, and then a low thermal resistance material is placed in the via hole. After filling
Since the temporary fixing mask is removed, the transistor cell is formed on the metal-filled via hole independently of the surrounding semiconductor substrate, which has excellent heat dissipation and is suitable for soldering during manufacturing. It is possible to easily manufacture a semiconductor device in which the transistor is not adversely affected even when a stress such as the thermal stress is applied to the semiconductor substrate, without causing the transistor cells to fall apart.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. Example 1. 1A and 1B are views showing a semiconductor device according to a first embodiment of the present invention when an active element is an FET, FIG. 1A is a perspective view thereof, and FIG. 1B is FIG. 1A. Ib-Ib
Sectional drawing in section, FIG. 1 (c) is Ic-Ic of FIG. 1 (a)
FIG. 2 is a cross-sectional view showing a cross section, and FIG. In the figure, the same reference numerals as those in FIG.
A semi-insulating substrate made of GaAs having a thickness of 30 μm or less separated from the semiconductor substrate 1 when the
Reference numeral 13 is a via hole in which the inside of the hole is filled with a low heat resistance substance such as a metal mainly made of Au or grease, 13a is a low heat resistance substance filled in the via hole 13, and 14 is independent from the semiconductor substrate 1. A metal pattern made of Au or the like for fixing the transistor cell to the semiconductor substrate, which is formed on the wafer surface around the transistor cell formed in this way, 15 is a unit transistor cell, 2
Reference numerals 3 and 24 denote air bridge wirings that serve as a gate wiring and a drain wiring, respectively.

In the semiconductor device of the first embodiment, a semi-insulating substrate 12 and an operating layer 10 are sequentially laminated from the lower layer as an active element on a metal 13a of Au filled in the via hole 13 to form an FET. This FET is formed independently of the surrounding semiconductor substrate 1. In addition, a source electrode 5a, a drain electrode 5b, and a gate electrode 5c are formed on the operating layer 10 in a comb-like shape like the conventional example. A metal film 14 is formed as a source wiring around the FET.

Next, a method of manufacturing the semiconductor device according to the first embodiment will be described with reference to FIG. 2 especially when the active element is a GaAs FET. First, on a semi-insulating GaAs semiconductor substrate 1a, as shown in FIG.
lGaAs etching stopper layer 1b, semi-insulating GaA
The s layer 1c and the n-type GaAs operating layer 10 are sequentially formed by epitaxial growth. Then, on the operating layer 10, FIG.
As shown in (b), the source electrode 5a, the drain electrode 5b,
The gate electrode 5c is formed and the transistor portion 5 is formed.

Next, as shown in FIG. 2C, the surface of the main surface of the semiconductor substrate 1 other than the transistor cells 15 is changed to Ga.
Wet etching using an etchant that etches As but not AlGaAs is performed to the depth of the surface of the etching stopper layer 1b.

Next, as shown in FIG. 2D, a metal film 14 of Au or the like is formed between the transistor cells 15 and 15 and between the transistor cells 15 and the semiconductor substrate 1. The metal film 14 will later fix the transistor cell 15 to the surrounding semiconductor substrate 1. The metal film 14 is formed by forming a pattern on a required portion of the surface of the semiconductor substrate 1, forming a thin metal film by sputtering, vapor deposition, or electroless plating, and then forming a thick metal film 14 by electrolytic plating. It is what The metal film 14 serves as a source wiring for wiring the source electrode 5a and another source electrode 5a, and the source electrode 5a and the back surface metal 9.

Then, as shown in FIG. 2 (e), the semi-insulating semiconductor substrate 1 is polished from the back surface to a thickness of 10 to 150 μm to be thin.

Next, from the back side of the semiconductor substrate 1, only the lower portion where the transistor cells 15 are present is etched with GaAs, but not with AlGaAs, by wet etching using an etchant to form the etching stopper layer 1b. Etch to the back side. Furthermore A
Wet etching using an etchant that etches lGaAs but not GaAs,
The etching stopper layer 1b is etched until the metal film 14 that fixes the transistor cell 15 is exposed, and the transistor cell 15 is separated from the surrounding semiconductor substrate 1.
A via hole 13 is formed as shown in FIG.

Then, as shown in FIG. 2 (g), A is formed on the entire inner surface of the via hole 13 and the entire rear surface of the semiconductor substrate 1.
The metal film 9 made of u is formed by the sputtering method or the vapor deposition method.

Next, as shown in FIG. 2 (h), the via hole 1
3 is filled with a metal 13a made of Au. The metal 13a may be another low heat resistance material.

Then, the signal input pad 2, the signal output pad 3, the input matching circuit 6, and the output matching circuit 7 are formed by a metal pattern, the air bridge wirings 23, 24 are formed, and the base wiring and the collector wiring are formed. Done, Figure 1 (a)
The semiconductor device of the present Example 1 shown in is completed.

In the step shown in FIG. 2C, the etching stopper layer 1b is left in a region other than the region directly below the transistor cell 15. AlGaAs is etched at this stage, but GaAs is removed. The etching stopper layer 1b is removed by wet etching using an etchant that does not etch, and etching is stopped at the back surface of the etching stopper layer 1b at the stage of FIG. The layer 1b may be left.

In the first embodiment, as shown in FIG.
In the steps of (c) and FIG. 2 (f), the semiconductor substrate on which the etching stopper layer 1b is formed is used in order to control the etching to a desired shape and depth, but without using the etching stopper layer 1b. However, those etchings may be controlled by time.

Next, the operation will be described. The heat generated just below the gate 5c of each transistor is filled with A in the operating layer 10, the semi-insulating substrate 12, and the via hole 13.
Heat is radiated from the back surface of the substrate through the metal 13a of u.

As described above, in the semiconductor device of the first embodiment, the semi-insulating substrate 12 below the transistor 15, which is the heat generating portion of the semiconductor device, is formed to have a small thickness, so that heat is radiated for each unit transistor cell. By forming the transistor cell 15 on the via hole 13 filled with the metal 13a made of Au having good ductility while being excellent in ductility, stress applied to the semiconductor substrate 1 of the FET cell is suppressed, and heat dissipation is excellent. Moreover, there is an effect that a semiconductor device having a small ground inductance can be obtained.

In the method of manufacturing a semiconductor device according to the first embodiment, the metal film 14 is formed between the transistor cells 15 and between the transistor cells 15 and between the transistor cells 15 and the semiconductor substrate 1. Transistor cell 1
After fixing 5 to the semiconductor substrate 1, only the lower part of the transistor cell 15 of this substrate 1 is etched from the back side until the metal film 14 is exposed, thereby forming a via hole 13 and surrounding the transistor cell 15. After separating from the semiconductor substrate 1 and further forming the metal film 9 on the entire inner surface of the via hole 13 and the entire rear surface of the substrate 1, the metal 13a is filled in the via hole 13 so that the transistor cell 15 has a ductility. Since it is formed independently of the surrounding semiconductor substrate 1 on the via hole 13 filled with a good metal 13a, even if stress such as thermal stress during soldering is applied to the semiconductor substrate 1 at the time of manufacturing, the transistor cell It is possible to easily realize a semiconductor device excellent in heat dissipation, which does not adversely affect 15.

Example 2. 3A and 3B are views showing a semiconductor device according to a second embodiment of the present invention when the active element is an HBT, FIG. 3A is a perspective view thereof, and FIG. 3B is FIG. 3A.
IIIb-IIIb sectional view, and FIG. 4 is a sectional view showing the manufacturing method. In the figure, the same reference numerals as those in FIG. 1 and FIG.
Reference numeral 6 is an emitter electrode, 17 is an emitter wiring, 18 is an emitter layer, 19 is a base layer, 20 is a collector layer, 21 is a collector electrode, 22 is a base electrode, 31 is a transistor electrode when the transistor cell is separated from the surrounding semiconductor substrate 1. This is a mask for temporarily fixing the transistor cells.

In the MMIC semiconductor device according to the second embodiment, the semi-insulating substrate 1 is formed from the lower layer as an active element on the metal 13a made of Au filled in the via hole 13.
2, a collector layer 20, a base layer 19, and an emitter layer 18 are laminated in this order, and the collector layer 20 and the base layer 1
9. An HBT in which each collector electrode 21, base electrode 22, and emitter electrode 16 are formed on the emitter layer 18 is used, and this HBT element is used for the surrounding semiconductor substrate 1
It is formed independently from.

Next, a method of manufacturing a semiconductor device according to a second embodiment of the present invention will be described with reference to FIG. 4 particularly when the active element is an HBT. On the semiconductor substrate 1, a transistor cell 15 made of HBT, that is, a collector layer 20, a base layer 19, and an emitter layer 18 are stacked in this order from the lower layer,
Moreover, the transistor cell 15 having the emitter electrode 16, the collector electrode 21, and the base electrode 22 is formed on each collector layer 20, the base layer 19, and the emitter layer 18 (FIG. 4A).

Next, the surface of the semiconductor substrate 1 other than the transistor cells 15 on the main surface side is etched to a depth of 1 to 10 μm (FIG. 4 (b)).

Next, a mask 31 is formed on the entire main surface of the semiconductor substrate 1 to cover the transistor cells 15 and temporarily fix them (FIG. 4 (c)).

Then, the semiconductor substrate 1 is replaced with 10 to 150.
Polish from the back to a thickness of μm (Fig. 4 (d)).

Next, the transistor cell 1 of the semiconductor substrate 1
Only the lower part where 5 exists is the transistor cell 15
Etching from the back side is performed until the mask 31 for temporarily fixing the transistor is exposed, the transistor cell 15 is separated from the surrounding semiconductor substrate 1, and the via hole 13 is formed (FIG. 4).
(e)).

Next, a metal film 9 is formed on the entire inner surface of the via hole 13 and the entire rear surface of the semiconductor substrate 1 (FIG. 4 (f)).

Then, metal 1 is placed inside the via hole 13.
Fill 3a. Here, the metal 13a may be another low heat resistance material (FIG. 4 (g)).

Next, after removing the mask 31, the air bridge wiring 17 is formed to perform the emitter wiring (FIG. 4 (h)), the signal input pad 2, the signal output pad 3, the input matching circuit 6, and The semiconductor device according to the second embodiment is completed by forming the output matching circuit 7 with a metal pattern and performing the base wiring and the collector wiring (FIG. 3 (a)).

In the second embodiment as well, as in the first embodiment, the etching shape is controlled by using the etching stopper layer in the steps of FIGS. 4 (b) and 4 (e). May be.

Next, the operation will be described. The heat generated in each transistor is radiated from the rear surface of the substrate through the semi-insulating substrate 12 and the metal 13a filled with Au in the via hole 13.

As described above, in the semiconductor device of the second embodiment,
By forming the substrate thickness of the semi-insulating substrate 12 below the transistor, which is the heat generating portion of the semiconductor device, thinly, and forming the transistor cell on the via hole 13 filled with the metal 13a made of Au, the unit cell is formed. The semiconductor device is excellent in heat dissipation for each transistor cell, stress applied to the semiconductor substrate 1 of the HBT cell is suppressed, and a semiconductor device excellent in heat dissipation and having a small ground inductance can be obtained.

As described above, in the method of manufacturing the semiconductor device according to the second embodiment, the mask 31 that covers the transistor cell 15 and temporarily fixes the transistor cell 15 is formed on the entire main surface side of the semiconductor substrate 1 on which the transistor cell 15 is formed. By etching from the back side of the substrate 1 only on the lower side of the substrate 1 where the transistor cell 15 is present until the mask 31 for temporarily fixing is exposed, a via hole 13 is formed and the transistor cell 15 is surrounded by the surrounding semiconductor. Separated from board 1,
Further, after the metal film 9 is formed on the entire inner surface of the via hole 13 and the entire rear surface of the substrate 1, the via hole 13 is formed.
By filling the inside of the hole with the metal 13a and removing the mask 32, the transistor cell 15 is formed on the via hole 13 filled with the metal 13a having good ductility independently of the surrounding semiconductor substrate. It is possible to easily realize a semiconductor device having excellent heat dissipation, which does not adversely affect the transistor cells 15 even if stress such as thermal stress at the time of soldering is applied to the semiconductor substrate 1.

Example 3. 5A and 5B are views showing a semiconductor device according to a third embodiment of the present invention in the case where the active element is an HBT. FIG. 5A is a perspective view thereof, and FIG. 5B is FIG. 5A.
6 is a cross-sectional view taken along line Vb-Vb in FIG. 6, and FIG. 6 is a cross-sectional view illustrating the manufacturing method thereof. In the figure, the same reference numerals as those in FIGS. 1 and 3 denote the same or corresponding parts, and in the figure, 25,
Reference numeral 26 is a base wiring and air bridge wiring serving as a collector wiring, respectively, and 32 is the transistor cell 15 when the transistor cell 15 is separated from the surrounding semiconductor substrate 1.
Is a mask for temporarily fixing.

In the semiconductor device according to the third embodiment, the emitter layer 18, the base layer 19, and the collector layer 20 are sequentially stacked from the lower layer on the metal 13a of Au filled in the via hole 13 as an active element. And base layer 1
9. An HBT in which a base electrode 22 and a collector electrode 21 are formed on the collector layer 20 is used.
The BT is formed independently of the surrounding semiconductor substrate 1.

Next, a method of manufacturing a semiconductor device according to a third embodiment of the present invention will be described with reference to FIG.
The case will be described. First, a transistor cell 15 composed of an HBT semiconductor device is formed on a semiconductor substrate 1 from the lower layer to an emitter layer 18, a base layer 19, and a collector layer 20.
Are sequentially stacked, and the collector layer 20 and the base layer 19 are further stacked.
A collector electrode 21 and a base electrode 22 are formed on each (FIG. 6 (a)).

Next, the entire main surface of the semiconductor substrate 1 is covered with the transistor cell 15 so as to cover the transistor cell 15.
A mask 32 for temporarily fixing is formed (FIG. 6 (b)).

Next, the semiconductor substrate 1 is set to 10 to 150 μm.
The back side is polished to the thickness of (Fig. 6 (c)).

Then, only the lower portion of the semiconductor substrate 1 where the transistor cell 15 is present is set to the transistor cell 1
5 for temporarily fixing 5 and the transistor cell 15
Etching is performed from the back side until the emitter layer 18 is exposed to form the via hole 13 so as to separate the transistor cell 15 from the surrounding semiconductor substrate 1 (FIG. 6 (d)).
).

Next, a metal film 9 is formed on the entire inner surface of the via hole 13 and the entire rear surface of the semiconductor substrate 1 to form an emitter electrode to be an ohmic electrode, and
Perform emitter wiring (Fig. 6 (e)).

Next, the inside of the via hole 13 is filled with metal 13a (FIG. 6 (f)), and the mask 32 is removed (FIG. 6 (g)).

The signal input pad 2, the signal output pad 3, the input matching circuit 6, and the output matching circuit 7 are formed of a metal pattern, and the air bridge wiring 25,
Base wiring and collector wiring are respectively performed by 26 to complete the semiconductor device of the third embodiment (FIG. 5A).
).

In the third embodiment as well, similar to the first embodiment, the etching shape may be controlled by using the etching stopper layer in the step of FIG. 6 (d).

Next, the operation will be described. In the third embodiment, the semiconductor substrate 1 is etched from the back side to separate the transistor cell 15 from the surrounding semiconductor substrate 1, and thus the transistor cell 15 is directly mounted on the via hole 13 filled with the metal 13a. The heat generated in each transistor is radiated from the back surface of the substrate 1 through the metal 13a made of Au with which the via hole 13 is filled.

As described above, in the semiconductor device of the third embodiment,
The transistor cell 15 is formed independently of the surrounding semiconductor substrate 1, and has a metal 13 with good ductility inside.
Since the emitter layer 18 of the transistor cell 15 is directly formed on the via hole 13 filled with a,
It is possible to obtain a semiconductor device having excellent heat dissipation, suppressing stress applied to the semiconductor substrate 1 of the HBT cell, and having a small ground inductance.

As described above, in the method of manufacturing the semiconductor device according to the third embodiment, the mask 32 that covers the transistor cells 15 and temporarily fixes them is formed on the entire main surface side of the semiconductor substrate 1 on which the transistor cells 15 are formed. By etching from the back side of the substrate 1 only on the lower side of the substrate 1 where the transistor cell 15 is present until the mask 32 for temporary fixing is exposed, the via hole 13 is formed and the transistor cell 15 is surrounded by the surrounding semiconductor. Separated from board 1,
Further, after the metal film 9 is formed on the entire inner surface of the via hole 13 and the entire rear surface of the substrate 1, the via hole 13 is formed.
By filling the inside of the hole with the metal 13a and removing the mask 32, the transistor cell 15 is
Since it is formed on the via hole 13 filled with a independently from the surrounding semiconductor substrate, the transistor cell 15 is not adversely affected even if stress such as thermal stress at the time of soldering during manufacturing is applied to the semiconductor substrate 1. It is possible to easily realize a semiconductor device which is excellent in heat dissipation and does not fall short.

As described above, in the method of manufacturing the semiconductor device according to the third embodiment, the order of stacking the emitter layer 18, the base layer 19 and the collector layer 20 is reversed from that of the second embodiment, and the emitter layer 18 and the emitter layer 18 are stacked. The emitter electrode and the emitter wiring can be omitted by contacting the metal film 9 on the via hole 13 with each other, that is, forming an ohmic contact with the metal film 9, thereby omitting the emitter electrode and the emitter wiring. Can be easy.

Example 4. Although the semiconductor device in which the active element is the FET or the HBT has been described in the first, second, and third embodiments, the active element is the HEM.
It may be T, and in this case, it can be manufactured by the same manufacturing method as the method shown in the first embodiment, and the same effect as the semiconductor device of the first embodiment can be obtained.

[0062]

As described above, according to the semiconductor device of the present invention, the transistor cell is provided on the main surface side of the substrate of the via hole provided through the substrate and filled with the low thermal resistance substance. Since the structure is mounted independently of the surrounding substrate, it is possible to improve the heat dissipation and also to perform the soldering work when the substrate thickness of the transistor cell part is 30 μm or less for the purpose of improving the heat dissipation characteristics. There is an effect that it is possible to obtain a structure in which a substrate crack or the like does not occur due to thermal stress generated at the time.

According to the method of manufacturing a semiconductor device of the present invention, a metal film is formed between the transistor cell and the semiconductor substrate to fix the transistor cell to the semiconductor substrate, and then the transistor cell under the substrate is formed. Since the via hole is formed by etching only the side part from the back side until the metal film is exposed, the transistor cell is separated from the surrounding substrate, and then the via hole is filled with the low thermal resistance material. Even if a stress such as thermal stress at the time of soldering at the time of manufacturing is applied to the semiconductor substrate, the transistor is not adversely affected, and a semiconductor device excellent in heat dissipation can be easily manufactured.

Further, according to the method of manufacturing a semiconductor device of the present invention, a mask for covering the transistor cells and temporarily fixing the transistor cells is formed on the entire main surface side of the semiconductor substrate on which the transistor cells are formed, and then the semiconductor is formed. Only the lower part of the substrate where the transistor cells are present is etched from the back side until the mask for temporarily fixing the above is exposed to form a via hole, and the transistor cell is separated from the surrounding semiconductor substrate, and then the via hole is formed. After filling the low thermal resistance material in the inside, since the temporary fixing mask was removed, even if stress such as thermal stress at the time of soldering during manufacturing is applied to the semiconductor substrate, the transistor cell is not adversely affected. There is an effect that a semiconductor device having excellent heat dissipation can be easily manufactured.

[Brief description of drawings]

FIG. 1 is a diagram showing a semiconductor device according to a first embodiment of the invention.

FIG. 2 is a sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a semiconductor device according to a second embodiment of the invention.

FIG. 4 is a sectional view showing a method of manufacturing a semiconductor device according to a second embodiment of the invention.

FIG. 5 is a diagram showing a semiconductor device according to a third embodiment of the invention.

FIG. 6 is a sectional view showing a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

FIG. 7 is a perspective view showing a conventional MMIC semiconductor device.

FIG. 8 is a plan view showing a conventional MMIC semiconductor device.

FIG. 9 is a perspective view showing another conventional method for manufacturing a semiconductor device.

FIG. 10 is a plan view showing another conventional semiconductor device.

[Explanation of symbols]

 1, 1a, 1c GaAs semiconductor substrate 1b Etching stopper layer 2 Signal input pad 3 Signal output pad 4 Metal pattern 5 Transistor part 5a Source electrode 5b Drain electrode 5c Gate electrode 5d Air bridge wiring 6 Input matching circuit 7 Output matching circuit 8 Via hole 9 Backside Metal 10 Operating Layer 12 Semi-Insulating Substrate 13 Via Hole 13a Filling Metal 14 Metal Film 15 Transistor Cell 16 Emitter Electrode 17 Emitter Wiring 18 Emitter Layer 19 Base Layer 20 Collector Layer 21 Collector Electrode 22 Base Electrode 23, 24, 25, 26 Air Bridge Wiring 31, 32 Mask 41 Lower Resist Layer 42 Metal Layer 42a Remaining Part of Metal Layer 43 Hole 44 Upper Resist Layer 45 Plating Metal Layer 46 FET 47 Through Hole 55a Source Electrode 55b Drain Down electrode 55c gate electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location H01L 21/331 29/73 21/338 29/812 27/095 7376-4M H01L 29/80 L 7376 -4M E

Claims (9)

[Claims] 1. A semiconductor integrated circuit device having a transistor operating in a high frequency band, a semiconductor substrate, a via hole provided through the substrate, and a single or a plurality of transistors provided on the via hole. A cell, the one or more transistor cells are formed independently of the surrounding semiconductor substrate on the low thermal resistance material filling the via holes on the main surface side of the substrate. A semiconductor device characterized by the above. 2. The semiconductor device according to claim 1, wherein in the transistor cell, a semiconductor layer is stacked in this order from a lower layer to a semi-insulating substrate and an operating layer, and a source electrode, a drain electrode and a gate are provided on the operating layer. A semiconductor device, which is an electronic transistor semiconductor device having an electrode. 3. The semiconductor device according to claim 1, wherein in the transistor cell, a semi-insulating substrate, a collector layer, a base layer, and an emitter layer are stacked in this order from a lower layer, and the collector layer and the base layer. A semiconductor device characterized by being a heterojunction bipolar transistor semiconductor device having collector electrodes, base electrodes, and emitter electrodes on an emitter layer. 4. The semiconductor device according to claim 1, wherein in the transistor cell, semiconductor layers are stacked in this order from a lower layer to an emitter layer, a base layer, and a collector layer, and a base electrode is provided on each of the base layer and the collector layer. , A semiconductor device characterized by being a heterojunction bipolar transistor semiconductor device having a collector electrode. 5. A step of forming one or a plurality of transistor cells on a semiconductor substrate, a step of etching the main surface side surface of the semiconductor substrate other than the transistor cells to a predetermined depth, the transistor cell and the semiconductor. A step of forming a metal film for fixing the transistor cell to the semiconductor substrate between itself and the substrate; and the metal for fixing the transistor cell only in a portion of the semiconductor substrate below the region where the transistor cell exists. A step of separating the one or more transistor cells and the semiconductor substrate thereunder from the surrounding semiconductor substrate by forming a via hole by etching from the back side until the film is exposed; and a low thermal resistance in the via hole. And a step of filling with a substance. 6. The method of manufacturing a semiconductor device according to claim 5, further comprising a step of forming an etching stopper layer in the semiconductor substrate before the step of forming a transistor cell on the semiconductor substrate. The step of etching the main surface side surface of the semiconductor substrate other than to a predetermined depth is performed by etching the main surface side surface of the semiconductor substrate other than the transistor cells to the surface of the etching stopper layer. A method for manufacturing a semiconductor device, comprising: 7. A step of forming a transistor cell on a semiconductor substrate, a step of etching the main surface side surface of the semiconductor substrate other than the transistor cell to a predetermined depth, and an entire main surface side of the semiconductor substrate. And a step of forming a mask for temporarily fixing the transistor cell so as to cover the transistor cell, and a mask for temporarily fixing the transistor cell is exposed only on a lower portion of the semiconductor substrate where the transistor cell exists. Of a semiconductor device including a step of forming a via hole by etching from the back side to separate the transistor cell from the surrounding semiconductor substrate, and a step of filling the via hole with a low thermal resistance material. Production method. 8. The method of manufacturing a semiconductor device according to claim 7, wherein a semiconductor layer is laminated on a semiconductor substrate in the order from a lower layer to a collector layer, a base layer, and an emitter layer, and the collector layer,
A method for manufacturing a semiconductor device, comprising forming a collector electrode, a base electrode, and an emitter electrode on a base layer and an emitter layer, respectively, to form a heterojunction bipolar transistor semiconductor device. 9. The method for manufacturing a semiconductor device according to claim 7, wherein a semiconductor layer is laminated on a semiconductor substrate in the order of an emitter layer, a base layer and a collector layer from a lower layer, and on the base layer and the collector layer. A method of manufacturing a semiconductor device, comprising forming a collector electrode and a base electrode to form a heterojunction bipolar transistor semiconductor device.