GB2278017A

GB2278017A - Semiconductor integrated circuit device

Info

Publication number: GB2278017A
Application number: GB9409633A
Authority: GB
Inventors: Makio Komaru
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 1993-05-13
Filing date: 1994-05-13
Publication date: 1994-11-16
Anticipated expiration: 2014-05-13
Also published as: JPH06326330A; GB9409633D0; DE4416696A1; GB2278017B

Abstract

A semiconductor integrated circuit device including transistors operating at a high frequency band includes a semiconductor substrate 1, a Thrnugh-hole hole 13 penetrating the substrate, and one or more transistor cells 5 disposed on material 13a of a low thermal resistance filling the hole 13. Thus, the transistor cells formed on the material of a low thermal resistance filling the hole 13 are separated from the substrate surrounding the transistor cells. Accordingly, the semiconductor device generates no crack of the substrate even when the thickness of the substrate at the transistor cell part is made thinner than 30 mu m for the purpose of improving the heat radiation characteristic and a semiconductor device having an excellent heat radiation property is obtained. <IMAGE>

Description

i 2278017

SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR FIELD OF THE INVENTION

The present invention relates to a semiconductor device and a method for producing the same and.. more particularly, to an improvement in characteristics of a semiconductor device operating at a high frequency band from several hundreds MHz to several hundreds GHz. BACKGROUND OF R INVENTION

Figures 7(a) and 7(b) are views illustrating a prior art MMIC (Monolithic Microwave Integrated Circuit) device. Figure 7(a) is a perspective view of the device, and figure 7(b) is a cross-sectional view of the device in line 7b-7b of figure 7(a). Figure 8 is a plan view of the device shown in figure 7. In the figures, reference numeral 1 designates a semiinsulating GaAs semiconductor substrate, numeral 2 designates a signal input pad, numeral 3 designates a signal output pad, numeral 4 designates a metal pattern disposed on a via-hole. Numeral 5 designates a transistor part, numeral 5a designates a source electrode, numeral 5b designates a drain electrode, and numeral 5c designates a gate electrode. The drain electrodes 5b and the gate electrodes 5c are formed in a comb tooth shape so as to be engaged with each other as illustrated in figure B. An air bridge wiring 5d is provided for wiring the source electrodes 5a of the respective transistors with the metal patterns 4. An input

1 - 2 matching circuit 6 takes matching for an input signal that is input from the signal input pad 2. An output matching circuit 7 takes matching for an output signal that is output from the signal output pad 3. Via holes 8 are formed penetrating the semiconductor substrate 1 and are filled with metal. Here, there may be a case where the via holes 8 are not filled with metal. A rear surface metal 9 comprises Au. An active layer 10 comprises an n type GaAs layer. The n type GaAs operation layer 10 is formed by epitaxial growth, ion implantation, or the like.

The signal input pad 2 is wired to the gate electrodes 5c via the input matching circuit 6. The signal output pad 3 is wired to the drain electrodes 5b via the output matching circuit 7. The source electrodes 5a are wired to the rear surface metal 9 via the air bridge wiring 5d, the metal patterns 4 and the metal filled in the via holes 8.

A description is given of the operation.

In the prior art MMIC device, heat generated at the transistor part 5 is radiated through the via holes 8 filled with metal as well as radiated from the rear surface of the chip through the semiconductor substrate 1.

Japanese Published Patent Application no. 59-172720 discloses a microwave FET (field effect transistor) including holes filled with metal which are formed at a rear surface of an element formation part of a substrate.

1 Figures 9(a)-9(e) illustrate a prior art method for filling a through hole of the substrate with metal. Figure 10 is a plan view of the microwave FET formed with the through hole filled by this method. In the figures, reference numeral 1 designates a substrate, numeral 41 designates a rear photoresist layer, numeral 42 designates a metal layer, numeral 42a designates a remaining part of the metal layer 42, numeral 43 designates a hole, numeral 44 designates an upper photoresist layer, numeral 45 designates a plated metal layer, numeral 46 designates an FET, numeral 47 designates a through hole, numeral 55a designates a source electrode, numeral 55b designates a drain electrode, and numeral 55c designates a gate electrode.

In this prior art method, the holes 43 are formed between FETs formed on the upper surface of the semiconductor substrate 1, and the metal layer 42 is formed on the entire surface as illustrated in figure 9(a). The upper photoresist layer 44 is formed on the entire surface except the hole formation parts (43) and upper edge parts thereof as illustrated in figure 9(b). The plated metal layer 45 is formed on respective exposed parts of the metal layer 42 by electroplating using the metal layer 42 as an electrode so as to have a thickness burying the holes 43 and, thereafter, the lower photoresist layer 41, the metal layer 42 and the upper photoresist layer 44 are removed so

1 that a part 42a of the metal layer 42 remain integrated with the plating metal layer 45 in respective holes 43 as illustrated in figure 9(c). A through hole 47 connecting the holes 43 is formed by performing etching from the rear surface of the semiconductor substrate 1 as illustrated in figure 9(d). The through hole 47 is filled with metal 48 comprising such as Au as illustrated in figure 9(e). Here, there may be a case where the through hole 47 is not filled with metal.

A description is given of the operation.

In the microwave FETs formed by this prior art metal filling method, heat generated in the FETs 46 is radiated from the rear surface of the chip through the metal filled within the through hole 47.

While in the above-described prior arts, FETs are included as active elements, HBTs (Heterojunction Bipolar Transistor), HEMTs (High Electron Mobility Transistor), or the like other than FETs may be employed as transistors which are included in an MMIC.

In the prior art MMIC semiconductor device as described above, it is necessary to make the semiconductor substrate at the transistor part thin to be approximately 2 pm - 30 pm so as to improve heat radiation of the element. Therefore, when stress such as thermal stress is applied to the semiconductor substrate at soldering the MMIC device in the manufacture, crack or fracture occurs at the semiconductor substrate, resulting in breakage of the element.

Further, the microwave FET disclosed in Japanese Published Patent Application no. 59-172720 has a structure in which heat generated in the FET par' is radiated through a via-hole formed at the rear surface of the element and, therefore, there is no necessity of making the semiconductor substrate thin in order to improve heat radiation of the element. In this prior art FET, however, the substrate at the element formation part and the substrate at the periphery of the element formation part are connected at a portion and, therefore, when this FET is soldered, thermal stress is applied to the FET part, whereby the element characteristic is adversely affected.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a semiconductor device which is not unfavorably affected by the thermal stress generating during soldering the semiconductor device, and has an improved heat radiation property.

It is another object of the present invention to provide a method suitable for producing such a device.

Other objects and advantages of the present invention will become apparent from the detailed description given hereinafter; it should be understood, however, that the

6 detailed described and specific embodiment are given by way of illustration only, since various changes and modifications within the scope of the invention will become apparent to those skilled in the art from this detailed description.

According to the first aspect of the present invention, a semiconductor device includes a semiconductor substrate, a through hole or via-hole formed penetrating the substrate, and a single or a plurality of transistor cells disposed on the material filled in the through hole or via-hole. The transistor cells are formed on a material of a low thermal resistance filled in the through hole or via-hole at the main surface of the substrate, independent from the peripheral semiconductor substrate. As a result, even in a case where the thickness of the substrate at the unit transistor cell is set to below 30 pmg for the purpose of improving heat radiation, no crack is generated during the substrate by thermal stress generated at soldering the semiconductor device.

According to a second aspect of the present invention, a method for producing a semiconductor device includes: forming a single or plural transistor cells on a semiconductor substrate; etching a main surface of the substrate to a prescribed depth except a part on which the transistor cells are formed, forming a metal film for fixing the transistor cells to the semiconductor substrate, between the transistor cells and the semiconductor substrate; etching only a part of the substrate under a region where the transistor cells are disposed from the rear surface up to exposing the metal film for fixing the transistor cells thereby to f orm a through hole so as to separate the single or plural transistor cells and the part of the semiconductor substrate positioning under those from the peripheral substrate; and thereafter, filling the through hole with a material of low thermal resistance. Thus, the transistor cells are formed on the material f illing the through hole separated from the peripheral semiconductor substrate. Therefore, a semiconductor device having an improved heat radiation property and having transistors which are not adversely affected even when stress such as thermal stress is applied to the semiconductor substrate during soldering in the manufacture, is easily fabricated without the transistor cells being separated from each other.

According to a third aspect of the present invention, a method for producing a semiconductor device includes: forming transistor cells on a semiconductor substrate; etching a main surface of the semiconductor substrate to a prescribed depth except a portion on which the transistor cells are formed, forming a mask covering and provisionally fixing the transistor cells on the entire surface of the semiconductor substrate at the main surface; etching only a - 8 portion of the semiconductor substrate on which the transistor cells are disposed from the rear surface up to exposing the mask for provisionally fixing the transistor cells thereby to f orm a through hole, and thereby separating the transistor cells from the peripheral semiconductor substrate; f illing the through hole with a material of low thermal resistance; and removing the provisional fixation mask. Thus, the transistor cells are formed on the through hole filled with metal independent from the peripheral semiconductor substrate. Therefore, a semiconductor device having transistors which are not adversely affected even when stress such as thermal stress is applied to the semiconductor substrate during soldering in the manufacture and having an improved heat radiation property is easily fabricated without the transistor cells being separated from each other.

BRIEF DESCRTPTTON OF THE DRAWTNGS Figures l(a)-l(c) are a perspective view and crosssectional views illustrating a semiconductor device in accordance with a first embodiment of the present invention.

Figures 2(a)-2(h) are cross-sectional views illustrating a method for producing the semiconductor device in accordance with the first embodiment of the present invention.

Figures 3(a) and 3(b) are a perspective view and a cross-sectional view illustrating a semiconductor device in accordance with a second embodiment of the present invention.

Figures 4(a)-4(b) are cross-sectional views illustrating a method for producing the semiconductor device in accordance with the second embodiment of the present invention.

Figures 5(a) and 5(b) are a perspective view and a cross-sectional view illustrating a semiconductor device in accordance with a third embodiment of the present invention.

Figures 6(a)-6(g) are cross-sectional views illustrating a method for producing the semiconductor device in accordance with the third embodiment of the present invention.

Figures 7(a) and 7(b) are a perspective view and a cross-sectional view illustrating a prior art MMIC semiconductor device, respectively.

Figure 8 is a plan view illustrating the prior art MMIC semiconductor device.

Figures 9(a)-9(e) are cross-sectional views illustrating another prior art method for producing a semiconductor device.

Figure 10 is a plan view illustrating the other prior art semiconductor device.

nRTAIT,Rn nRseRTPTmN OF THE PREFERRpn RmRonTMRMT Embodiment 1 Figures l(a)-l(c) are views illustrating a semiconductor device in accordance with a first embodiment of the present invention where FETs are employed as active elements. Figure l(a) is a perspective view of the semiconductor device, figure 1(b) is a cross-sectional view of the device taken alone line lb-lb of figure l(a), and figure l(c) is a cross- sectional view of the device taken along line lc-lc of figure l(a). Figures 2(a) to 2(h) are cross-sectional views illustrating a method for producing the device. In the figures, the same reference numerals as those shown in figure 7 designate the same or corresponding parts. A semi- insulating substrate 12 comprising GaAs is formed separated from the semiconductor substrate 1 in a thickness of less than 30 pm when a via- hole 13 is formed by etching in the semiconductor substrate 1. The via- hole 13 is filled with a metal, for example, Au, or a material of a low thermal resistance, for example, grease. Reference numeral 13a designates a material of a low thermal resistance filled in the via-hole 13. A metal pattern 14, for example, Au pattern for fixing the transistor cells to the semiconductor substrate is formed on the wafer surface around the transistor cells as a source wiring. Reference numeral 15 designates a unit transistor cell, and numerals 23 and 24 designate air bridge wirings as a gate wiring and a drain wiring, respectively.

The semiconductor device of this first embodiment includes FETs as active elements which are formed on the Au layer 13a filled in the via-hole 13 laminating an operating layer 10 on a semi-insulating substrate 12. These FETs are separated from the peripheral semiconductor substrate 1. Source electrodes 5a, drain electrodes 5b, and gate electrodes 5c are formed in a comb tooth configuration on the operating layer 10 as in the prior art. The metal film 14 as a source wiring is formed around the FETs.

A description is given of a method for producing the semiconductor device of the first embodiment with reference to figure 2, which device has a GaAs FET as the active element.

First of all, a semi-insulating AlGaAs etching stopper layer lb, a semiinsulating GaAs layer 1c, and an n type GaAs operating layer 10 are epitaxially grown in this order on a semi-insulating GaAs substrate la as illustrated in figure 2(a). Next, source electrodes 5a, drain electrodes 5b, and gate electrodes 5c are formed on the operating layer 10 thereby to form transistor cells 15 as illustrated in figure 2(b).

Next, a wet etching is carried out to the principal surface of the semiconductor substrate 1 except portions thereof on which the transistor cells 15 are disposed, up to reaching the surface of the etching stopper layer lb using an etchant which etches GaAs but does not etch AlGaAs as illustrated in figure 2(c).

Next, an Au film 14 is formed between the transistor cells 15 and between the both end transistor cells 15 and the semiconductor substrate 1 as illustrated in figure 2(d). The metal film 14 fixes the transistor cells 15 to the peripheral part ofthe semiconductor substrate 1 later. The metal film 14 is formed by forming a resist pattern at required portions of the surface of the semiconductor substrate 1, forming a thin Au film by sputtering, evaporation or electroless plating, forming thick Au film 14 by electrolytic plating, and then removing the resist film. The metal film 14 serves as a source wiring between adjacent source electrodes 5a or a wiring between the both end source electrodes 5a and the rear surface metal 9.

The semi-insulating semiconductor substrate 1 is polished from its rear surface to 10 to 150 pm thickness as illustrated in figure 2(e).

Next, a wet etching is carried out only to a part of the semiconductor substrate 1 on which the transistor cells 15 are disposed from the rear surface of the substrate 1 to reaching the rear surface of the etching stopper layer lb using an etchant which etches GaAs but does not AlGaAs. Further, the etching stopper layer lb is etched so as to 1 expose the metal film 14 fixing the transistor cells 15 by a wet etching using an etchant which, etches AlGaAs but does not etch GaAs, thereby separating the transistor cells 15 from the peripheral semiconductor substrate 1 and forming the via-hole 13 as illustrated in figure 2(f).

Subsequently, an Au film 9 is formed on the entire inner surface of the via-hole 13 and on the entire rear surface of the semiconductor substrate 1 by sputtering or evaporation as illustrated in figure 2(g) and, thereafter, the via-hole 13 is filled in with metal 13a, for example, Au as illustrated in figure 2(h). Here, this metal 13a may be of other material of a low thermal resistance.

Subsequently, a signal input pad 2, a signal output pad 3, an input impedance matching circuit 6, and an output impedance matching circuit 7 are formed by metal patterns, and air bridge wirings 23 and 24 are formed as base wirings and collector wirings, thereby completing the semiconductor device of this first embodiment illustrated in figure l(a).

Here, in the process of figure 2(c), the etching stopper layer lb remains not only at regions directly under the transistor cells 15 but also at the other regions. In this process, however, the etching stopper layer lb at the regions except the region under the transistor cells 15 may be removed by wet etching using an etchant which etches AlGaAs but does not etch GaAs. In the process of figure 2(f), the etching may be stopped at the rear surface of the etching stopper layer lb so as to remain the etching stopper layer lb only on the rear surfaces of the transistor cells 15.

In the processes shown in figures 2(c) and 2(f of this first embodiment, the semiconductor substrate including the etching stopper layer lb is employed to control the etching to obtain a desired shape and a desired depth. However, the etching may be controlled by time, without employing the etching stopper layer lb.

A description will be given of the operation.

Heat generated at directly below the gates 5c of the respective transistors is radiated from the rear surface of the substrate 1 through the operating layer 10, the semiinsulating substrate 12, and the metal 13a comprising Au filled in the via-hole 13.

As described above, in the semiconductor device of this first embodiment, portions of the semi-insulating substrate 12 below the transistors 15 which are heat generating parts of the semiconductor device, are formed in a small thickness, whereby the respective unit transistor cells have an improved heat radiation property. Further, the transistor cells 15 are formed on the via-hole 13 filled with the Au metal 13a having a favorable ductility, whereby stress applied to the semiconductor substrates of the FET cells is suppressed. Therefore, a semiconductor device having an improved heat radiation property as well as a small grounding inductance is obtained.

Additionally, according to the method for producing a semiconductor device of this first embodiment, the metal film 14 is formed between the adjacent transistor cells 15 and between the transistor cell 15 and the semiconductor substrate 1 to fix the transistor cells 15 to the semiconductor substrate 1. Thereafter, only parts of the substrate 1 under the transistor cells 15 are etched from the rear surface of the substrate 1 up to exposing this metal film 14 to form the via-hole 13 and thereby to separate the transistor cells 15 from the peripheral semiconductor substrate 1. Further, the metal film 9 is formed on the entire inner surface of the via-hole 13 and the entire rear surface of the substrate 1 and, thereafter, the via hole 13 is filled with the metal 13a. In this way, the transistor cells 15 are formed on the via-hole 13 filled with the metal 13a having a favorable ductility so as to be independent from the semiconductor substrate 1. Therefore, a semiconductor device having an improved heat radiation property, and thereby not having been adversely affected even when thermal stress or the like is applied to the semiconductor substrate 1 during soldering in the manufacture of the device, is realized.

- jr, - Embodiment 2.

Figures 3(a) and 3(b) are views illustrating a semiconductor device in accordance with a second embodiment of the present invention in which HBTs are employed as active elements. Figure 3(a) is a perspective view of the device, and figure 3(b) is a cross-sectional view of the device in a line 3b-3b of figure 3(a). Figures 4(a) to 4(h) are cross-sectional views for explaining a method for producing the device. In the figures, the same reference numerals as those in figures 1 and 7 designate the same or corresponding parts. Reference numeral 16 designates an emitter electrode, numeral 17 designates an emitter wiring, numeral 18 designates an emitter layer, numeral 19 designates a base layer, numeral 20 designates a collector layer, numeral 21 designates a collector electrode, and numeral 22 designates a base electrode. A mask 31 is one for provisionally fixing transistor cells during separating the transistor cells from the semiconductor substrate 1.

An MMIC device according.to this second embodiment includes HBTs as active elements each formed on the Au metal 13a that is filled in the via- hole 13, including a semiinsulating substrate 12, a collector layer 20, a base layer 19, and an emitter layer 18 laminated in this order, and a collector electrode 21, a base electrodes 22, and an emitter electrode 16 disposed on the collector layer 20, the base 1 Z - 17 layer 19, and the emitter layer 18, respectively. These HBT elements are formed separated from on the semiconductor substrate 1.

The method for producing the semiconductor device of this second embodiment will be described with reference to figures 4(a) to 4(h), which device has an HBT as active element.

The transistor cells 15 each forming a HBT are formed on the semiconductor substrate 1. Each transistor cell 15 includes the collector layer 20, the base layer 19, and the emitter layer 18 laminated on the semiconductor substrate, in this order, and the emitter electrode 16, the collector electrodes 21, and the base electrodes 22, formed on the collector layer 20, the base layer 19, and the emitter layer 18 respectively, as illustrated in figure 4(a).

Next, parts of the princ ipal surface of the semiconductor substrate 1 except under the transistor cells 15 are etched to 1 to 10 pm depth, as illustrated in figure 4(b).

Next, a mask 31 covering the transistor cells 15 and provisionally fixing these cells 15 is formed on the entire principal surface of the semiconductor substrate 1, as illustrated in figure 4(c).

Next, the semiconductor substrate 1 is polished from its rear surface to leave 10 to 150 pm thick, as illustrated in figure 4(d).

Next, only a portion of the semiconductor substrate 1 on which the transistor cells 15 are disposed is etched from its rear surface up to exposing the mask 31 so as to provisionally fix the transistor cells 15 and separate the transistor cells 15 from the semiconductor substrate 1, and thereby forming the via-hole 13, as illustrated in figure 4(e).

Next, the metal film 9 is formed on the entire inner surface of the viahole 13 and the entire rear surface of the semiconductor substrate 1, as illustrated in figure 4(f).

Next, the metal 13a is filled in the via-hole 13, as illustrated in figure 4(g). Then, the metal 13a may be other material of a low thermal resistance.

Next, the mask 31 is removed and, thereafter, an emitter wiring is connected forming an air bridge wiring 17, as illustrated in figure 4(h). The signal input pad 2, the signal output pad 3, the input impedance matching circuit 6, and the output impedance matching circuit 7 are formed by a metal pattern, and further, a base wiring and a collector wiring are connected, thereby completing the semiconductor device illustrated in figure 3(a).

In this second embodiment, in the processes of figures 4(b) and 4(e), the etched configuration may be controlled by - 19 employing an etching stopper layer as in the above-described first embodiment.

Next, a description is given of the operation.

Heat generated at the respective transistors is radiated from the rear surface of the substrate through the semi-insulating substrate 12 and the Au metal 13a which is fill ed within the via-hole 13.

As described above, in the semiconductor device of this second embodiment, the semi-insulating substrate 12 is thin under the transistors generating heat, and the transistor cells are formed on the via-hole 13 filled with the Au metal 13a, whereby each unit transistor cell has an excellent heat radiation property, and stress applied to the semiconductor substrate of the respective HBT cells is suppressed. Therefore, it results in a semiconductor device having an excellent heat radiation property as well as a small grounding inductance.

In addition, according to the production method of a semiconductor device of this second embodiment, the mask 31 is formed on the entire principal surface of the semiconductor substrate 1 on which the transistor cells 15 are formed, covering these cells 15 and provisionally fixing these cells 15, only portions of the substrate 1 on which the transistor cells 15 are disposed are etched from its rear surface up to exposing the mask 31 to form the via-hole 13 and separate the transistor cells 15 from the semiconductor substrate 1, the metal film 9 is formed on the entire inner surface of the via-hole 13 and the entire rear surface of the substrate 1 and, thereafter, the metal 13a is filled in the via-hole 13, and the mask 32 is removed. In this way, the transistor cells 15 are formed on the via-hole 13 filled with the metal 13a having a favorable ductility so as to be separated from the semiconductor substrate 1. Therefore, a semiconductor device having an excellent heat radiation property and which is not adversely affected even when thermal stress or the like is applied to the substrate 1 during soldering in the manufacture of the device, is easily produced. Embodiment 3.

Figures 5(a) and-5(b) are views illustrating a semiconductor device including HBTs as active elements in accordance with a third embodiment of the present invention. Figure 5(a) it a perspective view of the device, and figure 5(b) is a cross-sectional view of the device in a line 5b-5b of figure 5(a). Figures 6(a) to 6(g) are cross-sectional views for explaining a method for producing the device. In the figures, the same reference numerals as those shown in figures 1 and 3 designate the same or corresponding parts. Reference numerals 25 and 26 designate air bridge wirings as a base wiring and a collector wiring, respectively. A mask 3 k 32 is one for provisionally fixing transistor cells 15 during separating the transistor cells 15 from the semiconductor substrate 1.

The semiconductor device of this third embodiment includes HBTs as active elements. Each HBT includes an emitter layer 18, a base layer 19 and a collector layer 20 which are laminated in this order on Au metal 13a filled in a via-hole 13, and further a base electrode 22 and a collector electrode 21 which are formed on the base layer 19 and the collector layer 20, respectively. The HBTs are separated from the semiconductor substrate 1.

Next, a description is given of a method for producing the semiconductor device of this third embodiment including HBTs as active elements with reference to figures 6(a) to 6(g).

First of all, the transistor cells 15 each forming an HBT are formed on the semiconductor substrate 1, as illustrated in figure 6(a). Each transistor cell 15 includes the emitter layer 18., the base layer 19, and the collector layer 20 which are laminated'in this order, and further the collector electrode 21 and the base electrodes 22 formed on the collector layer 20 and the base layer 19, respectively.

Thereafter, the mask 32 is formed on the entire principal surface of the semiconductor substrate 1 covering the transistor cells 15 and provisionally fixing the transistor cells 15P as illustrated in figure 6(b). Then, the semiconductor substrate 1 is polished from its rear surface to

10 to 150 pm thick, as illustrated in figure 6(c).

Subsequently, only portions of the semiconductor substrate 1 on which the transistor cells 15 are disposed are etched from its rear surface up to exposing the mask 32 and the emitter layers 18 of the transistor cells 15, whereby a via-hole 13 is formed so that the transistor cells 15 are separated from the semiconductor substrate 1, as illustrated in figure 6(d).

Next, the metal film 9 is formed on the entire inner surface of the viahole 13 and the entire rear surface of the semiconductor substrate I to form an emitter electrode as an ohmic electrode, as illustrated in figure 6(e).

Then, the metal 13a is filled in the via-hole 13 as illustrated in figure 6(f), and the mask 32 is removed as illustrated in figure 6(g).

A signal input pad 2, a signal output pad 3, an input matching circuit 6, and an output matching circuit 7 are formed from a metal pattern, and further a base wiring and a collector wiring are connected by air bridge wirings 25 and 26, respectively, whereby a semiconductor device of the third embodiment illustrated in figure 5(a) is completed.

23 - Also in this third embodiment, the etched configuration may be controlled by employing an etching stopper layer in the process of figure 6(d) as in the first embodiment.

A description is given of the operation.

In this third embodiment, the transistor cells 15 are separated from the semiconductor substrate 1 by etching the semiconductor substrate 1 from its rear surface, whereby a structure in which the transistor cells 15 are directly mounted on the via-hole 13 that is filled with the metal 13a. Therefore, heat generated at the respective transistors is radiated from the rear surface of the substrate 1 through the Au metal 13a comprising Au filled within the via-hole 13.

According to the semiconductor device of this third embodiment, the transistor cells 15 are formed separated from the semiconductor substrate 1, and the emitter layers 18 of the respective transistor cells 15 are formed directly on the via-hole 13 filled with the metal 13a having a good ductility. Therefore, a semiconductor device having an improved heat radiation property, in which a reduced stress is applied to the HBT cells, and having a small grounding inductance as well, is obtained.

In addition, according to this third embodiment, the mask 32 covering the transistor cells 15 and provisionally fixing these cells is formed on the entire principal surface 24 - of the semiconductor substrate 1 on which the transistor cells 15 are formed, and only a portion of the substrate 1 on which the transistor cells 15 are disposed is etched from its rear surface up to exposing the mask 32 whereby the viahole 13 is formed so that the transistor cells 15 are separated from the semiconductor substrate 1, and the metal film 9 is formed on the entire inner surface of the via-hole 13 and the entire rear surface of the substrate 1, and thereafter, the metal 13a is filled in the via-hole 13 and the mask 32 is removed. Thus, the transistor cells 15 are formed on the via-hole 13 filled with the metal 13a separated from the peripheral semiconductor substrate 1. Therefore, a semiconductor device, which is not adversely affected even when thermal stress or the like is applied to the semiconductor substrate I during soldering in the manufacture of the device, and having an improved heat radiation property, is easily realized.

In addition, in the above-described production method of a semiconductor device of this third embodiment, the emitter layer 18, the base layer 19, and the collector layer 20 are successively disposed in this order, which is reverse to that of the second embodiment, ohmic contact of the emitter layer 18 and the metal film 9 is produced on the via-hole 13, and an emitter electrode and an emitter wiring are simultaneously formed. Therefore, production of a particular emitter electrode and a particular emitter wiring is not required, resulting in that production process of the semiconductor device is simplified. Embodiment 4.

In the above-described first, second, and third embodiments, a semiconductor device including FETs or HBTs as active elements is described. However, the active elements may be HEMTs, and in this case the semiconductor device is produced by the same production process as that described in the first embodiment. The same effects as those in the first embodiment are obtained.

Claims

WHAT IS CLAIMED TR

1. A semiconductor integrated circuit device including transistors operating at a high frequency band, comprising: a semiconductor substrate having a front and a rear surface opposite to each other; a via-hole penetrating said substrate from the rear surface of said substrate to the front surface of substrate; a material disposed in said via-hole penetrating from the front surface of said substrate to the rear surface of said substrate, said material being of a low thermal resistance; at least one transistor cell disposed on the material filled in the via-hole; and said transistor cell formed on said material of low thermal resistance filled in said via-hole at the front surface of said semiconductor substrate being separated from said semiconductor substrate surrounding said transistor cells.

2. The semiconductor device of claim 1 wherein said transistor cells are field effect transistors, each said transistor cell comprising a semiinsulating substrate, semiconductor layers including an operating.layer disposed 1 1 on said substrate, and a source electrode, a drain electrode, and a gate electrode which are disposed on said operating layer.

3. The semiconductor device of claim 1, wherein said transistor cells are heterojunction bipolar transistors, each said transistor cell comprising semiconductor layers including a semi-insulating substrate, a collector layer, a base layer, and an emitter layer which are disposed in this order, and comprising a collector electrode, a base electrode, and an emitter electrode which are disposed on the collector layer, the base layer, and the emitter layer, respectively.

4. The semiconductor device of claim 1, wherein said transistor cells are heterojunction bipolar transistors, each said transistor cell comprising semiconductor layers including an emitter layer, a base layer and a collector layer which are disposed in this order, and a base electrode and a collector electrode which are disposed on the base layer and the collector layer, respectively.

5. A method for producing a semiconductor device, comprising: forming one or more transistor cells on a front 1 I_I J surface of a semiconductor substrate having a rear surface and a rear surface opposite to each other; etching the rear surface of said semiconductor substrate expect for a portion on which said transistor cells are disposed, to a prescribed depth; forming a metal film for fixing said transistor cells to said semiconductor substrate, between adjacent said transistor cells and between both end side transistor cells and portions of said semiconductor substrate on the side of the front surface of said semiconductor; etching only a portion of said semiconductor substrate under a region where said transistor cells are disposed, from the rear surface of the semiconductor substrate up to exposing said metal film fixing said transistor cells to produce a via- hole, and thereby separating said one or more transistor cells and portions of said semiconductor substrate under said transistor cells from said semiconductor substrate surrounding said transistor cells; and filling in said via-hole with a material of a low thermal resistance.

6. The production method of claim 5, further comprising:

before forming said transistor cells on said 29 - semiconductor substrate, forming an etching stopper layer on said semiconductor substrate; and etching the rear surface of said semiconductor substrate expect for a portion on which said transistor cells are disposed, up to exposing a surface of said etching stopper layer.

7. A method for producing a semiconductor device, comprising: forming transistor cells on a semiconductor substrate; etching the rear surface of said semiconductor substrate at a portion expect for a portion on which said transistor cells are disposed, to a prescribed depth; forming a mask covering said transistor cells thereby to provisionally fix said transistor cells on the entire main surface of said semiconductor substrate; etching only a portion of said semiconductor substrate on which said transistor cells are disposed, from the rear surface of said semiconductor substrate up to exposing said mask provisionally fixing said transistor cells to form a via-hole, and thereby separating said transistor cells from said semiconductor substrate surrounding said_transistor cells; and filling in said via-hole with a material of a low a - 30 thermal resistance.

8. The production method of claim 7, in which said transistor cells include semiconductor layers including a collector layer, a base layer, and an emitter layer disposed on said semiconductor substrate in this order, and a collector electrode, a base electrode, and an emitter electrode formed on said collector layer, said base layer, and said emitter layer, respectively, each said transistor cell forming a heterojunction bipolar transistor.

9. The production method of claim 7, in which said transistor cells including an emitter layer, a base layer and a collector layer disposed on said semiconductor substrate in this order, and an emitter electrode, a base electrode, and a collector electrode formed on said emitter layer, said base layer, and said collector layer, respectively, each said transistor cell forming a heterojunction bipolar transistoi.

31

10. A semiconductor integrated circuit device substantially as herein described with reference to figures 1 and 2, figures 3 and 4 or figures 5 and 6 of the accompanying drawings.

11. A method of producing a semiconductor device substantially as herein described with reference to figure 2, figure 4 or figure 6 of the accompanying drawings.