JPH11150113A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device in which a via hole can be formed from the back face, without the use of special division matching device, and the positioning precision of the via hole can be improved. SOLUTION: This method for manufacturing a semiconductor device is provided with a process (1) for forming a positioning pattern 3 on the surface of a semiconductor substrate 1, a process (2) for forming a through-hole 10 for allowing the positioning pattern 3 to be viewed from the back face side of the semiconductor substrate 1 on the back face of the semiconductor substrate 1, and a process (3) for forming a via hole 12 to be communicated from the back face to the surface of the semiconductor substrate through the use of the positioning pattern 3 as the positioning reference. Thus, those processes are successively executed in the order of the process (1) to the process (3).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a via hole forming process is improved.

[0002]

2. Description of the Related Art In recent years, semiconductor devices having excellent high-frequency performance have been developed.
For example, a Schottky gate field effect transistor (F) using a III-V group compound semiconductor represented by GaAs.
ET) is widely used in satellite communication, mobile communication, microwave backbone communication and the like, and its performance is required to be improved.

In this type of semiconductor device, a via-hole grounding method is used to reduce the parasitic inductance and improve the high-frequency performance. This involves forming a via hole, which is a through-hole, in a semiconductor chip, filling the via hole with a conductive material such as a metal, and electrically connecting the electrode on the front surface of the semiconductor chip to the metal on the back surface of the semiconductor chip. This is the method of grounding.

When forming a via hole, the positioning of the via hole is performed in accordance with the ground electrode pattern on the surface of the semiconductor chip. Conventionally, via holes have been positioned using a matching device such as a double-sided aligner or an infrared aligner capable of simultaneously viewing the front and back surfaces of a semiconductor substrate, and the via holes have been formed by photolithography.

[0005] However, the above-mentioned aligning device is expensive, and the handling thereof is complicated, so that there is a problem that it is difficult to accurately align from the back surface.

Accordingly, for example, Japanese Patent Application Laid-Open No. 60-74432 is disclosed.
Japanese Patent Application Laid-Open No. 4-78445 proposes a method of manufacturing a semiconductor device in which a via hole is formed without using a special aligning device.

FIG. 7 is a process chart showing a method for manufacturing a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 60-74432.
First, as shown in FIG. 7A, a photoresist pattern 33 having a metal electrode 32 and an opening 43 is formed on the surface of a semi-insulating wafer 31, and a photoresist film 34 is formed over the entire back surface. Then, a hole 42 penetrating from the front surface to the rear surface of the wafer 31 is formed by etching.

Next, as shown in FIG. 7B, after removing the photoresist pattern 33 and the photoresist film 34, the photoresist pattern 33 and the photoresist film 34 are aligned by using an opening on the back surface of the hole 42 to form a photoresist pattern 36. A photoresist film 35 is formed over the entire wafer surface.

Next, as shown in FIG. 7C, the back surface of the wafer 31 is etched to form a hole 44.

Next, as shown in FIG. 7D, the entire photoresist film is removed. Then, a plating power supply metal 38 is deposited on the back surface of the wafer 31, and a photoresist film 37 is formed over the entire surface of the wafer 31, and then gold plating 39 is performed.

Thereafter, as shown in FIG. 7E, when the photoresist film 37 is removed, the electrode 32 is electrically connected to the back surface of the wafer by a via hole.

FIG. 8 is a process chart showing a method for manufacturing a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 4-7845. First, as shown in FIG. 8A, a semi-insulating GaAs substrate 5 is formed.
After the operation layer is formed on the surface of the first electrode by ion implantation and epitaxial growth, the source electrode 52a and the drain electrode 52 are formed.
b, a gate electrode 53 is provided.

Next, as shown in FIG. 8B, a photoresist pattern 54 having an opening at a position where a via hole is to be formed is formed, and the GaAs substrate 51 is formed by using this as a mask by reactive ion etching (RIE). The hole 55 is formed by etching.

Next, as shown in FIG. 8C, the inside of the hole 55 is filled with a photoresist 56 or the like.

Next, as shown in FIG. 8D, a metallization pattern 57a of Au or the like connected to the source electrode 52a, a wiring pattern 57b connected to the drain electrode, and a wiring connected to the gate electrode so as to cover the hole 55. A pattern (not shown) is formed.

Next, as shown in FIG.
The back surface of the s-substrate 51 is processed and thinned to a predetermined thickness.

After that, as shown in FIG. 8F, the photoresist 56 filled in the hole 55 is removed with an organic solvent or the like, and then the rear surface metallization 58 is performed. 52a and is electrically connected.

[0018]

Problems to be Solved by the Invention
The method disclosed in Japanese Patent Laid-Open Publication No. 2 (1999) -1995 has an advantage that a special aligning device such as the infrared aligner or the double-side aligner described above is not required. However, since a hole penetrating a GaAs wafer having a thickness of several tens of μm or more is used as an alignment pattern, the size of the alignment pattern and its alignment accuracy are about 10 μm. Therefore, there is a problem that the electrode pattern cannot be miniaturized.

On the other hand, in the method disclosed in Japanese Patent Application Laid-Open No. Hei 4-7845, the positioning accuracy is improved as compared with the above-mentioned conventional technique. However, the adhesion between the filler material such as a photoresist filled in the holes of the GaAs substrate and the metallized pattern on the surface is poor, and the metallized pattern on the surface is peeled off during the process, thereby lowering the yield in the via hole process. There is.

Further, since the via holes are formed from the front surface of the GaAs substrate, the via holes tend to have an inversely tapered shape when viewed from the back surface, and it is difficult to metallize the back surface by sputtering or the like from both sides. .

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is intended to provide a semiconductor device which can form a via hole from the back surface without using a special aligning device and improves the positioning accuracy of the via hole. It is intended to provide a manufacturing method.

[0022]

According to the method of manufacturing a semiconductor device of the present invention, there are provided (1) a step of forming a positioning pattern on a front surface of a semiconductor substrate, and (2) a step of forming a positioning pattern on a back surface of the semiconductor substrate. Forming a first through hole for viewing from the back side of the semiconductor substrate; and (3) forming a second through hole penetrating from the back side to the front side of the semiconductor substrate using the positioning pattern as a reference for positioning. And performing the steps in the order of (1) to (3).

According to another method of manufacturing a semiconductor device of the present invention,
(1) a step of forming a positioning pattern on the front surface of a semiconductor substrate having electrodes on the front surface; and (2) a first through hole for viewing the positioning pattern on the back surface of the semiconductor substrate from the back surface side of the semiconductor substrate. (3) forming a second through-hole penetrating from the back surface of the semiconductor substrate to the electrode on the front surface using the positioning pattern as a positioning reference; and (4) forming the second through hole on the back surface of the semiconductor substrate. Covering a conductive layer electrically connected to the electrode through the second through-hole, and performing the steps in the order of (1) to (4).

According to still another method of manufacturing a semiconductor device of the present invention, there are provided (1) a step of forming a positioning pattern on a surface of a semiconductor substrate having electrodes on the surface, and (2) a step of forming a positioning pattern on a back surface of the semiconductor substrate. Forming a first resist pattern for forming a first through hole for viewing the pattern from the back side of the semiconductor substrate; and (3) using the first resist pattern as a mask to form a back surface of the semiconductor substrate. Forming a first through hole by etching; and (4) forming a second resist pattern on the back surface of the semiconductor substrate using the positioning pattern as a positioning reference;
(5) using the second resist pattern as a mask, etching the back surface of the semiconductor substrate to form a second through hole penetrating from the back surface of the semiconductor substrate to the electrode on the front surface;
(6) covering the back surface of the semiconductor substrate with a conductive layer that is electrically connected to the electrode via the second through hole;
It is characterized in that it is performed in the order of (1) to (6).

It is preferable that the first and second through holes are formed while the surface of the semiconductor substrate is adhered to the supporting substrate.

The positioning pattern is formed of an insulating film or a metal formed on the surface of the semiconductor substrate.

The formation of the first through hole is performed using, for example, an orientation flat formed in the semiconductor substrate as a reference for positioning.

[0028]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 6 are process diagrams showing a method for manufacturing a semiconductor device according to the present invention.

First, as shown in FIG.
A positioning pattern 3 made of a metal or an insulating film is formed on the surface of the semiconductor substrate 1 on which is formed. Here, the semiconductor substrate 1 is made of GaAs or InP, which is a group III-V semiconductor suitable for a high frequency device. The element pattern 2 is a Schottky junction gate field effect transistor, a PN junction gate field effect transistor, a hetero bipolar transistor, or the like having excellent high frequency performance.

The material of the positioning pattern 3 is a metal or an insulating film used for forming the element pattern 2.
In addition, a material that is not etched when the semiconductor substrate 1 is dry-etched later is selected. The positioning pattern 3 is formed, for example, in a cross shape.

Next, as shown in FIG.
Is turned upside down and fixed on the support substrate 7 via the adhesive 8. The support substrate 7 is used for facilitating handling after the semiconductor substrate 1 is polished and thinned, and for imparting mechanical strength. As the support substrate 7, for example, a sapphire plate or a quartz glass plate is used. Wax or the like is usually used as the bonding material 8, but a photoresist different from a photoresist used at the time of processing the back surface of the semiconductor substrate 1 in a later process and a peeling liquid may be used.

Next, as shown in FIG.
Is polished to make the semiconductor substrate 1 thinner. Thereafter, the through-hole 10 is formed so that the positioning pattern 3 formed on the surface of the semiconductor substrate 1 can be seen. Therefore, the first photoresist 9 is applied to the back surface of the semiconductor substrate 1, the ordinary contact aligner or the stepper aligner is used, and the orientation flat 6 of the semiconductor substrate 1 is used as a reference for positioning.
Is performed, and a pattern for forming a through hole is formed in the first photoresist 9. Then, using the first photoresist 9 as a mask, the semiconductor substrate 1 is etched from the back surface to form a through hole 10.

Next, as shown in FIG. 4, after removing the first photoresist 9, the second photoresist 11 is spin-coated on the back surface of the semiconductor substrate 1, and the positioning pattern 3 is passed through the through hole 10. Used as
A pattern for forming a via hole is formed in the second photoresist 11 on the back surface of the semiconductor substrate 1 at the position of the ground electrode 4 using a normal contact aligner or stepper aligner. The via hole 12 is formed by etching the semiconductor substrate 1 using the via hole forming pattern as a mask.

Next, as shown in FIG.
After a thin electroplating base metal layer 13 is deposited on the entire back and back sides by sputtering, a plating metal 14 serving as a heat sink is formed.
(See FIG. 6A) is formed by an electrolytic plating method.

Thereafter, as shown in FIG.
After the semiconductor substrate 1 is separated from the support substrate 7 by removing the semiconductor substrate 1, the semiconductor substrate 1 is cut into a predetermined size to complete the semiconductor device.

[0036]

Embodiments of the present invention will be described below with reference to the drawings. First, as shown in FIG. 1, a high power GaAs Schottky junction gate type field effect transistor (hereinafter, high power GaAs FET) is formed on a semiconductor substrate 1 which is a GaAs substrate.
Is formed. Then, on the surface of the semiconductor substrate 1, silicon dioxide (SiO ₂ , 500 nm thick) formed by CVD as an insulating film 5 is placed underneath, and WSi / Au (thickness) which is a gate electrode material of a high-power GaAs FET is formed. A positioning pattern 3 formed of a repetitive pattern of 10 μm in length and 10 μm in width is formed using ordinary photolithography and etching.

Next, as shown in FIG. 2, electron wax is applied as a bonding material 8 on a support substrate 7 made of quartz glass, and the surface of the semiconductor substrate 1 is attached.

Next, the back surface of the semiconductor substrate 1 is polished to reduce the thickness of the semiconductor substrate 1 to about 80 μm. Thereafter, the entire back surface of the semiconductor substrate 1 is further etched with an aqueous solution of phosphoric acid and hydrogen peroxide (phosphoric acid: hydrogen peroxide: water = 1: 1: 8) to reduce the thickness of the semiconductor substrate 1 to about 50 μm. Then, as shown in FIG. 3, the positioning pattern 3 formed on the surface of the semiconductor substrate 1 can be seen.
A through hole 10 is formed from the back surface of the semiconductor substrate 1. The formation of the through holes 10 is performed by a normal photolithography method from the back surface of the semiconductor substrate and the same etching method as when the entire back surface is etched.

The size of the through hole 10 is 500 μm square,
The positioning by the photolithography method with respect to the positioning pattern 3 is performed with reference to the orientation flat 6 of the semiconductor substrate 1. Specifically, the first photoresist 9 is spin-coated on the back surface of the semiconductor substrate 1, the through hole 10 is positioned using the orientation flat 6 of the semiconductor substrate 1 using a normal contact aligner, and the first photoresist 9 is formed. A pattern for forming a through hole is formed in the resist 9. Then, using the first photoresist 9 as a mask, the semiconductor substrate 1 is etched from the back surface to form a through hole 10.
To form

Next, as shown in FIG. 4, after removing the first photoresist 9, the second photoresist 11 is spin-coated on the back surface of the semiconductor substrate 1, and the positioning pattern 3 is passed through the through hole 10. Used as
A pattern for forming a via hole is formed in the second photoresist on the back surface of the semiconductor substrate 1 at the position of the ground electrode 4 using a normal contact aligner or stepper aligner.

Using the via hole forming pattern as a mask, the semiconductor substrate 1 is dry-etched using a mixed gas of SiCl ₄ and CF ₄ to form a via hole 12.

When forming the via hole 12,
The positioning accuracy of the via hole forming pattern with respect to the ground electrode 4 is about 1 μm. Also, via hole 1
Since the depth 2 is about 50 μm, which is the thickness of the semiconductor substrate 1, the shape of the via hole 12 is deformed by about 5 μm by dry etching when forming the via hole. Therefore, it is necessary to make the ground electrode 4 about 6 μm larger on one side than the via hole 12.

Next, as shown in FIG.
Of Ti /
After depositing Pt (film thickness 50 nm / 100 nm) by a sputtering method, a plating metal 14 (FIG. 6) serving as a heat sink is formed.
As shown in (a)), Au is formed to a thickness of about 10 μm by electrolytic plating.

Next, as shown in FIG.
After the wax is melted and separated from the semiconductor substrate 1 and the support substrate 7, the semiconductor substrate 1 is washed with an organic solvent to remove the wax, and cut into a predetermined size to obtain a semiconductor chip.

The positioning accuracy between the via hole 12 and the ground electrode 4 is as follows when a conventional double-sided positioning aligner is used.
It is about 10 μm. On the other hand, in the present invention, about 1 μm
It is greatly improved. As a result, a high-power GaAs FET
The size of the ground electrode 4 can be reduced by about 9 μm on one side.

In the device electrode pattern of the high-power GaAs FET shown in FIG. 6B, when the depth of the via hole 12 is 50 μm, the size W of the source electrode 15 having the via hole is increased in the conventional high-power GaAs FET. If the minimum dimension Wmin of the via hole pattern formed on the back surface of the semiconductor substrate 1 is 10 μm, the dimension expansion Δ1 by dry etching is about 5 μm on one side, and the positioning accuracy Δ2 of the via hole is about 10 μm on one side, W = Wmin + ( Δ
1 + Δ2) × 2 = 10 + (5 + 10) × 2 = 40 μm.

On the other hand, in the present invention, W = 10 + (5 + 1)
× 2 = 22 μm, and the size of the source electrode can be reduced by half.
As shown in FIG. 6B, in the electrode arrangement of a high-power GaAs FET in which the source electrode 15, the gate electrode 16, and the drain electrode 17 are repeatedly arranged in a comb shape, the pitch between the source electrodes conventionally needs to be about 50 μm. However, according to the present invention, it can be reduced to about 32 μm.

By this shortening, the chip yield of the high-output GaAs FET is increased by about 1.5 times (50/32), and the high-frequency performance is improved by the decrease in the chip width.

When the element pattern 2 is a hetero bipolar transistor using a semiconductor heterojunction, the source electrode 1 of the high-output GaAs FET in the above-described embodiment is used.
By rephrasing 5 to the ground electrode of the hetero-bipolar transistor, the description will be made in the same manner as in the above-described embodiment with reference to FIGS.

[0050]

According to the present invention, a positioning pattern is formed on the front surface of a semiconductor substrate, and a first through hole for viewing the positioning pattern from the back surface side of the semiconductor substrate is formed on the back surface of the semiconductor substrate. The via hole (second through hole) penetrating from the back surface to the front surface of the semiconductor substrate is formed using the positioning pattern as a positioning reference, so that a special alignment device such as a double-sided aligner or an infrared aligner is used. Without using the via holes, the positioning accuracy of the via holes can be improved. As a result, the electrode pattern can be miniaturized, and the high-frequency characteristics and the productivity of the semiconductor device can be improved.

[Brief description of the drawings]

1A and 1B are process diagrams showing a method for manufacturing a semiconductor device according to the present invention, wherein FIG. 1A is a plan view, FIG. 1B is a cross-sectional view taken along the line AA ′ of FIG. It is a BB 'line sectional view.

2A and 2B are process diagrams showing a method for manufacturing a semiconductor device according to the present invention, wherein FIG. 2A is a plan view, FIG. 2B is a cross-sectional view taken along the line CC ′ of FIG. It is DD 'line sectional drawing.

3A to 3C are process diagrams showing a method for manufacturing a semiconductor device according to the present invention, wherein FIG. 3A is a plan view, FIG. 3B is a cross-sectional view taken along line CC ′ of FIG. It is DD 'line sectional drawing.

4A to 4C are process diagrams showing a method for manufacturing a semiconductor device according to the present invention, wherein FIG. 4A is a plan view, FIG. 4B is a cross-sectional view taken along the line CC ′ of FIG. It is DD 'line sectional drawing.

FIG. 5 is a process chart showing a method for manufacturing a semiconductor device of the present invention.

6A and 6B are process diagrams showing a method for manufacturing a semiconductor device of the present invention, wherein FIG. 6A is a cross-sectional view and FIG. 6B is a plan view.

FIG. 7 is a process chart showing a method for manufacturing a semiconductor device disclosed in Japanese Patent Application Laid-Open No. Sho 60-74432.

FIG. 8 is a process diagram showing a method for manufacturing a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 4-7845.

[Explanation of symbols]

 1: Semiconductor substrate 2: Element pattern 3: Positioning pattern 4: Ground electrode 5: Insulating film 6: Orientation flat 7: Support substrate 8: Adhesive material 9: First photoresist 10: Through hole (First through hole) 11: Second photoresist 12: Via hole (second through hole) 13: Base metal layer for electroplating 14: Plated metal 15: Source electrode 16: Gate electrode 17: Drain electrode

Claims (7)

[Claims] 1. A step of: (1) forming a positioning pattern on a front surface of a semiconductor substrate; and (2) a first step for viewing the positioning pattern on the back surface of the semiconductor substrate from the back side of the semiconductor substrate. (1) forming a through hole; and (3) forming a second through hole penetrating from the back surface to the front surface of the semiconductor substrate using the positioning pattern as a positioning reference. ) To (3) in that order. And (2) a step of forming a positioning pattern on the front surface of the semiconductor substrate having electrodes on the front surface, and (2) viewing the positioning pattern on the back surface of the semiconductor substrate from the back surface side of the semiconductor substrate. (3) forming a second through hole penetrating from the back surface of the semiconductor substrate to the electrode on the front surface using the positioning pattern as a reference for positioning; (4) covering a back surface of the semiconductor substrate with a conductive layer electrically connected to an electrode via the second through hole;
A method for manufacturing a semiconductor device, wherein the method is performed in the order of (1) to (4). 3. A step of forming a positioning pattern on a front surface of a semiconductor substrate having electrodes on the front surface, and (2) viewing the positioning pattern on the back surface of the semiconductor substrate from the back side of the semiconductor substrate. Forming a first resist pattern for forming a first through hole for
(3) using the first resist pattern as a mask, etching the back surface of the semiconductor substrate to form a first through hole, and (4) using the positioning pattern as a positioning reference to form the semiconductor. Forming a second resist pattern on the back surface of the substrate; and (5) etching the back surface of the semiconductor substrate using the second resist pattern as a mask, and penetrating from the back surface of the semiconductor substrate to the electrode on the front surface. (1) a step of forming a second through-hole; and (6) a step of coating a back surface of the semiconductor substrate with a conductive layer electrically connected to an electrode via the second through-hole. ) To (6), in which order. 4. The semiconductor device according to claim 1, wherein the first through hole and the second through hole are formed in a state where a surface of the semiconductor substrate is attached to a supporting substrate. 13. The method for manufacturing a semiconductor device according to the above item. 5. The method of manufacturing a semiconductor device according to claim 1, wherein said positioning pattern is formed on an insulating film formed on a surface of said semiconductor substrate. . 6. The method of manufacturing a semiconductor device according to claim 1, wherein said positioning pattern is formed of a metal. 7. The semiconductor device according to claim 1, wherein the first through hole is formed using an orientation flat formed in the semiconductor substrate as a reference for positioning. Of manufacturing a semiconductor device.