JP2001267331A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To readily form vias in a semiconductor substrate at a low cost. SOLUTION: In the manufacturing method for a semiconductor device, having semiconductor elements on a semiconductor substrate main surface, an light transmissive film is adhered to the semiconductor substrate main surface, the backside of the semiconductor substrate is polished to remove the film. According to this means, the film covering the semiconductor substrate main surface uses a low-cost film, allowing vias to be easily formed at a low cost, and the sued film is light transmissive, allowing the semiconductor substrate main surface to be observed with the film adhered. Thus the aligning, etc., is easy in forming the vias.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a technique effective when applied to forming a via hole penetrating a semiconductor substrate.

[0002]

2. Description of the Related Art A compound semiconductor such as GaAs has a high electron mobility as compared with silicon, thereby enabling high-speed operation, and a low power consumption because a semi-insulating substrate can be obtained. Because of these advantages, they are used as substrates for high-frequency semiconductor devices. GaAs power FET used for mobile communication terminal equipment, GaAs MMIC (Monolithic used for vehicle-mounted millimeter wave radar equipment)
High-frequency semiconductor devices such as Microwave Integrated Circuits are required to have higher performance such as high gain, low distortion, and low current operation.

In such high-frequency operation, source resistance is a major problem. For this reason, in order to reduce source resistance and parasitic capacitance and improve performance,
A method of forming a source electrode on the back surface of a semiconductor substrate and connecting the source electrode to a source region of the main surface of the semiconductor substrate by via hole wiring formed in a via hole (via hole) penetrating the semiconductor substrate to reduce source resistance Is used. In the formation of such a via hole, the step of forming the via hole can be shortened by forming the via hole after polishing the back surface of the wafer to thin the semiconductor substrate.

In this backside polishing, the backside is polished while the main surface of the semiconductor substrate of the wafer on which the elements are formed is adhered to a quartz glass jig with wax. The wax used is one that melts at a low temperature in order to separate the jig from the wafer by heating and melting after polishing the wafer. For this reason, the melting temperature of the wax imposes a limit on the temperature of the subsequent processing, and there is no margin in the process of raising the temperature.

Also, since the quartz glass jig needs to be slightly larger than the wafer to be attached, the mass production apparatus designed for a normal wafer size when the wafer is attached to the jig is required. May not be available. Also, since the quartz glass used for the jig is expensive,
The price of a semiconductor device manufactured using the same increases.

[0006]

In order to solve such a problem, a hole in a non-penetrating state is first formed from the main surface of the semiconductor substrate, and the back surface is polished until the hole is exposed, thereby forming a penetrating state. A method of forming a via hole has been considered and was announced in 1998 by the Institute of Electronics, Information and Communication Engineers (IEICE). However, in this method, it is necessary to control the depth of the hole in the non-penetrating state with high accuracy, and there is a problem of uniformity. in addition,
There are also problems such as complicated processes.

An object of the present invention is to provide a technique capable of easily forming a via hole in a semiconductor substrate at low cost. The above and other problems and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

In a method of manufacturing a semiconductor device having a semiconductor element formed on a main surface of a semiconductor substrate, a light-transmitting film is attached to the main surface of the semiconductor substrate, and the back surface of the semiconductor substrate is polished to remove the film. .

According to the above-described means, since the via hole is formed using a low-cost film as the film covering the main surface of the semiconductor substrate, the via hole can be formed easily and at low cost. Since the light-transmitting film is used, the main surface of the semiconductor substrate can be observed with the film attached. For this reason, the alignment at the time of forming a via hole becomes easy.

Hereinafter, embodiments of the present invention will be described. In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.

[0012]

FIG. 1 is a longitudinal sectional view showing a semiconductor device manufactured according to an embodiment of the present invention. In the figure,
1 is a semiconductor substrate using semi-insulating GaAs, 2 is an epitaxial layer formed on the semiconductor substrate 1, and the epitaxial layer 2 has a mesa shape for element isolation.
As the epitaxial layer 2, a buffer layer 2 a in which AlGaAs and GaAs not containing impurities are alternately stacked on the semiconductor substrate 1, AlGaAs containing n-type impurities
An electron supply layer 2b made of s, a cover layer 2c made of GaAs containing a low concentration of n-type impurities, and a cap layer 2d containing a high concentration of n-type impurities are sequentially laminated.

Reference numeral 3 denotes a gate electrode formed on the cover layer 2c. For example, Pt is used, and a portion of the cap layer 2d and the cover layer 2c immediately below the gate electrode is dug down to obtain a desired channel thickness and to obtain a parasitic. It has a recess structure in which the area is kept thick. The drain electrode 4 is formed on the n + type cap layer 2d for reducing series resistance,
A laminated film in which AuGe / Ni is laminated is used.

The source electrode 5a is formed on the back surface of the semiconductor substrate using, for example, Au, and is connected to the source region on the main surface of the semiconductor substrate by a wiring 5b formed in a via hole integrally with the source electrode 5a. In the present embodiment, in order to enable connection on the semiconductor substrate main surface side, a source electrode 6 having the same configuration as the drain electrode 4 is also provided on the semiconductor substrate main surface side, separately from the source electrode 5a on the back surface. is there.

The entire surface of the main surface of the semiconductor substrate is covered with an insulating film 7 using, for example, a silicon oxide film or a PSG film doped with phosphorus by CVD, and the drain electrode 4 or the main surface side is formed through an opening provided in the insulating film 7. The source electrode 6 is connected to a wiring layer (not shown).

Next, a method of manufacturing the semiconductor device shown in FIG. 1 will be described. First, an epitaxial layer 2 is grown on a semi-insulating GaAs semiconductor substrate 1 by MBE (Molecular Beam Epitaxy). As the epitaxial layer, for example, a buffer layer 2a in which AlGaAs and GaAs containing no impurities are alternately stacked on the semiconductor substrate 1, an electron supply layer 2b made of AlGaAs containing n-type impurities, a low-concentration n-type impurity G containing
A cover layer 2c made of aAs and a cap layer 2d made of GaAs containing a high concentration of n-type impurity are grown.

Next, for device isolation, the epitaxial layer 2 is etched in a mesa shape until the epitaxial layer 2 reaches the buffer layer 2a, and then a part of the cap layer 2d and the cover layer 2c in the region where the gate electrode 3 is formed. Is removed by etching to form a gate electrode 3 on the exposed cover layer 2c,
A source electrode 6 and a drain electrode 4 are formed on the cap layer 2d, and a silicon oxide film or a phosphorus-doped PSG film is deposited by CVD on the entire surface to form an insulating film 7.
A source electrode 6 and a drain electrode 4 to a wiring layer (not shown)
An opening is provided for connection to

FIG. 2 shows a wafer in which the elements shown in FIG. 1 are formed by such a process. A light-transmitting film 9 over the entire surface of the semiconductor substrate main surface of the wafer 8;
More specifically, a negative dry film resist having a thickness of, for example, about 100 μm to 120 μm is subjected to UV irradiation or overall exposure using a contact aligner to be polymerized. This state is shown in FIG.

The element formed on the main surface of the semiconductor substrate can be protected by the film 9 attached to the entire surface. However, if it is desired to secure the protection more, it is superimposed on the film 9 and indicated by a broken line in the figure. As shown, a normal BG tape 10 may be attached.

Next, the thickness of the semiconductor substrate is 80 μm to 10 μm.
The back surface of the semiconductor substrate is polished to about 0 μm, and wet etching or polishing is performed to about 5 μm to 10 μm to remove distortion due to polishing. This state is shown in FIG.

Next, a resist mask 11 for forming a via hole is formed on the back surface of the semiconductor substrate. In the resist mask 11, it is desirable to use a novolak resin-based positive resist that can be alkali-developed so as not to dissolve the film 9 during development. BG tape 10
Is applied, the BG tape 10 is peeled and removed before the formation of the resist mask 11. This state is shown in FIG.
Shown in

Next, via holes are formed by dry etching using the resist mask 11. When the film 9 may be etched by this etching, the film 9 is covered with a jig 12 having a concave portion for accommodating the film portion using quartz or the like as shown by a broken line in the drawing. What is necessary is just to protect the film 9.
This state is shown in FIG.

Next, the resist mask 11 is removed using, for example, a parallel plate type asher. If there is a possibility that the film 9 will be affected by this removal, the film 9 is covered with a jig 12 provided with a concave portion for accommodating the film portion by using quartz or the like as described above to protect the film 9. I just need. This state is shown in FIG.

Next, a metal film 13 is formed by sputtering or the like on the entire back surface of the semiconductor substrate on which the via holes have been formed.
This state is shown in FIG.

Next, the entire surface of the back surface of the semiconductor substrate is plated by using Au, for example, by using the metal film 13 as a seed electrode.
A metal film 5 serving as a source electrode 5a and a via hole wiring 5b is formed. This state is shown in FIG.

Next, the film 9 is removed using a stripping solution such as an aqueous KOH solution, and the surface is cleaned with an asher. This state is shown in FIG.

In this embodiment, a light-transmitting film is used as a film covering the main surface of the semiconductor substrate, so that the main surface of the semiconductor substrate can be observed with the film attached. For this reason, the alignment at the time of forming a via hole becomes easy. On the other hand, in the case of a BG film conventionally used for backside polishing, the main surface of the semiconductor substrate could not be observed in a state where the film was adhered due to light-shielding properties. When the film is peeled off for the observation, there are problems such as warpage of the wafer or insufficient strength of the wafer.

The dry film resist used in the present embodiment is widely used for a resist mask of a printed wiring board or a liquid crystal panel, etc., and has a high reliability at a low cost and can be dissolved and removed. In this case, it is possible to avoid applying a force to the semiconductor substrate.

The method of the present invention can be applied to ordinary backside polishing without forming a via hole. In this case, when the semiconductor substrate is thinned by polishing, when a conventional BG tape is used, a force is applied to the semiconductor substrate attached at the time of peeling. If the thickness is further reduced in the future, the semiconductor substrate may be damaged. According to the method of the present invention, since the film can be dissolved and removed, no force is applied to the semiconductor substrate, and the semiconductor substrate is not damaged.

The manufacturing method described above can be applied to the MMIC semiconductor substrate shown in FIG. MMI
In the case of C, a p-type HEMT (High Electron Mobility Transistor) formed on the main surface of the GaAs semiconductor substrate 1
The drain electrode 14a is connected to a resistor 15 made of WSiN also formed on the main surface of the semiconductor substrate 1 by a transmission line 17a of a metal film such as Au formed on the main surface of the semiconductor substrate via an insulating film 16. . Further, an end of another transmission line 17b connected to the resistor 15 is overlapped with an end of another metal film 19 such as Au via a dielectric film 18 such as SiN to form a metal insulator metal (MIM). Form capacitance.

An electrode 20a is formed on the back surface of the semiconductor substrate 1 by plating with Au or the like. A via-hole wiring 20b integrated with the electrode 20a is connected to a source electrode 14b of the HEMT 14 via another transmission line 21. Have been.

As described above, the invention made by the present inventor is:
Although a specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention.

[0033]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. (1) According to the present invention, there is an effect that a via hole can be easily formed in a semiconductor substrate. (2) According to the present invention, the above-mentioned effect (1) allows the FET
And the parasitic capacitance can be reduced. (3) According to the present invention, the effect (2) has an effect that the performance of the semiconductor device can be improved.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a longitudinal sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention for each process.

FIG. 3 is a longitudinal sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention for each process.

FIG. 4 is a longitudinal sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention for each step.

FIG. 5 is a longitudinal sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention for each step.

FIG. 6 is a longitudinal sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention for each process.

FIG. 7 is a longitudinal sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention for each step.

FIG. 8 is a longitudinal sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention for each step.

FIG. 9 is a vertical cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention for each step.

FIG. 10 is a longitudinal sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention for each process.

FIG. 11 is a longitudinal sectional view showing an MMIC according to a method of manufacturing a semiconductor device according to an embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Epitaxial layer, 2a ... Buffer layer, 2b ... Electron supply layer, 2c ... Cover layer, 2d ... Cap layer, 3 ... Gate electrode, 4 ... Drain electrode, 5a ... Source electrode, 5b ... Via hole Wiring, 6 ... source electrode,
7 insulating film, 8 wafer, 9 film, 10 BG tape, 11 resist mask, 12 jig, 13 metal film, 14 HEMT, 14a drain electrode, 14b
Source electrode, 15: resistance, 16: insulating film, 17a, 17
b, 21: transmission line, 18: dielectric film, 19: metal film, 2
0a: electrode, 20b: via-hole wiring.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/095 H01L 29/80 H 29/778 F term (Reference) 4M104 AA05 CC01 DD07 DD15 DD37 DD52 FF02 GG12 GG13 5F033 GG02 HH13 MM05 MM30 PP15 PP27 QQ07 QQ37 QQ46 XX10 XX24 5F102 FA03 GA16 GA17 GB02 GC01 GD01 GJ05 GK04 GM05 GM05 GM06 GN05 GQ01 GR04 GT03 GV07 HC00 HC01 HC15 HC29 HC30

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor device having a semiconductor element formed on a main surface of a semiconductor substrate, wherein: a step of attaching a light transmissive film to the main surface of the semiconductor substrate; and a step of polishing a back surface of the semiconductor substrate. And a step of removing the film. 2. A via hole is formed from the back side of the semiconductor substrate, an FET is formed as the semiconductor element, and a source electrode of the FET is formed on the back side of the semiconductor substrate.
2. The semiconductor device according to claim 1, wherein the via electrode connects the source electrode to a source region on a main surface of the semiconductor substrate.
13. The method for manufacturing a semiconductor device according to item 5. 3. The method according to claim 1, wherein the film is made of a photosensitive resin. 4. The method according to claim 3, wherein the film is a dry film resist. 5. The method according to claim 4, wherein the dry film resist is a negative type.