JPH01109754A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01109754A JPH01109754A JP62268438A JP26843887A JPH01109754A JP H01109754 A JPH01109754 A JP H01109754A JP 62268438 A JP62268438 A JP 62268438A JP 26843887 A JP26843887 A JP 26843887A JP H01109754 A JPH01109754 A JP H01109754A
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- semiconductor substrate
- scribe line
- chip
- scribe
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000002184 metal Substances 0.000 claims abstract description 47
- 229910052751 metal Inorganic materials 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000005498 polishing Methods 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- 238000002955 isolation Methods 0.000 abstract 1
- 238000007747 plating Methods 0.000 description 9
- 238000000926 separation method Methods 0.000 description 6
- 238000009713 electroplating Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012267 brine Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007688 edging Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- HPALAKNZSZLMCH-UHFFFAOYSA-M sodium;chloride;hydrate Chemical compound O.[Na+].[Cl-] HPALAKNZSZLMCH-UHFFFAOYSA-M 0.000 description 1
Landscapes
- Dicing (AREA)
- Junction Field-Effect Transistors (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
乙の発明は、半導体装置の製造方法に関し、特にプレー
テイッドヒートシンクの形成方法に関するものである、
。[Detailed Description of the Invention] [Industrial Application Field] The invention of B relates to a method for manufacturing a semiconductor device, and in particular to a method for forming a plated heat sink.
.
第２図（、）〜（ｅ）は従来の半導体装置におけるプレ
ーテイツドヒートシンク（以下ＰＨＳと称する）の主要
製造工程を示す断面図である。FIGS. 2(a) to 2(e) are cross-sectional views showing the main manufacturing steps of a plated heat sink (hereinafter referred to as PHS) in a conventional semiconductor device.
第２図において、１は半導体基板、２は配線パターン、
３はバイアホール、３ａは第１金属層、５は第２金属層
、５ａは前記第２金属層５の突起部、４４ｔｔスクライ
ブラインフォトレジストパターン
第３図は、第２図（ｄ）の工程における問題点を示した
主要部の拡大断面図で、５））は前記スクライブラ，ｆ
ンフォトレジストパターン４４下への第２金属層５のま
わり込み成長部であり、その他の符号１１第２図中の符
号と同一部分をそれぞれ示している。In FIG. 2, 1 is a semiconductor substrate, 2 is a wiring pattern,
3 is a via hole, 3a is a first metal layer, 5 is a second metal layer, 5a is a protrusion of the second metal layer 5, 44tt scribe line photoresist pattern FIG. 3 shows the process of FIG. 2(d) 5)) is an enlarged sectional view of the main part showing problems in the scriber, f
This is a wrap-around growth portion of the second metal layer 5 under the photoresist pattern 44, and other reference numerals 11 indicate the same parts as the reference numerals in FIG. 2, respectively.
次に製造」−程について説明する。Next, the manufacturing process will be explained.
まず、第２図（ａ）に示すように、半導体基板１の第１
の面上に配線パターン２を形成し、さらにバイアホール
３を湿式エツチング等によってあけ、このバイアホール
３の四部にｆ８Ｍメツキ等によって第１金属Ｊｉ！ｄ３
ｎを形成する。次に、第２図（ｂ）に示すように、半導
体基板１の第１の面とは反対側の第２の面（以下、第１
の面を表面、第２の面を裏面と称する。）に研磨・湿式
エツチングを順次施し、バイアホール３の底部に相当す
る第１金属層３ａ（Ｄ一部分を半導体基板１の裏面側に
露出させる。次に、第２図（Ｃ）に示すように、半導体
基板１の裏面上に蒸着または無電解メツキ等によってメ
ツキ給電金属層５５を形成し、さらに写真製版によりス
クライブラインフォトレジストパターン
ｄ）に示すように、スクライブラインフォトレジストパ
ターン
い、第２金属層５を形成し、その後、スクライブライン
フォトレジストパターン
ツチングまたはダイシングによってチップ分離を行って
、第２図（０）にその外観を示ずような゛ト導体装置を
１りろ。First, as shown in FIG. 2(a), the first
A wiring pattern 2 is formed on the surface of the via hole 3, and a via hole 3 is formed by wet etching, etc., and a first metal Ji! is formed on the four parts of the via hole 3 by f8M plating or the like. d3
form n. Next, as shown in FIG. 2(b), a second surface (hereinafter referred to as a first surface) opposite to the first surface of the semiconductor substrate 1 is
The surface is called the front surface, and the second surface is called the back surface. ) is sequentially polished and wet-etched to expose a portion of the first metal layer 3a (D) corresponding to the bottom of the via hole 3 on the back side of the semiconductor substrate 1.Next, as shown in FIG. 2(C), , a plating power supply metal layer 55 is formed on the back surface of the semiconductor substrate 1 by vapor deposition or electroless plating, and then a scribe line photoresist pattern is formed by photolithography as shown in d), and a second metal is formed. Layer 5 is formed, followed by chip separation by scribe-line photoresist patterning or dicing to produce a single conductor device, the external appearance of which is shown in FIG. 2(0).
以上のー【：稈によって製造された半導体装置において
、バイアホール３，このバイアホール３Ｕ）四部に形成
した第１金属層３ａおよび第２金属層５は、半導体基板
１の表面側に形成した配線パターン２から裏面側への接
地効果，並びに放熱体としての効果を有する。０１１記
放熱体としての効果を充分に発揮させるため、半導体基
板１の厚みは研肋エッヂングにより薄（調整され、また
、チップ強度を得るため、第２金属層５は電解メツキに
よりＪ（形成される。このような厚メツキ放熱体構造は
、１） ＩＩ Ｓ構造と呼ばれ、主に高出力電界効果ト
ランジスクに用いられている。In the above-mentioned semiconductor device manufactured by culm, the first metal layer 3a and the second metal layer 5 formed in the four parts of the via hole 3 and this via hole 3U) are interconnections formed on the surface side of the semiconductor substrate 1. It has a grounding effect from the pattern 2 to the back side and an effect as a heat sink. 011. In order to fully demonstrate the effect as a heat dissipation body, the thickness of the semiconductor substrate 1 is adjusted to be thin by grinding rib edging, and in order to obtain chip strength, the second metal layer 5 is formed by electrolytic plating. This type of thick plating heat sink structure is called 1) II S structure, and is mainly used in high-power field effect transistors.
従来の半導体装置の製造方法では、第３図に示すように
、第２金属層５の形成１ニ程（第２図（（］）の工程）
において、前述のごとく厚メツキを行うため□、長時間
処理によるレジスト剥離部分で第２金属層５のまわり込
み成長部５ｂが生じ、次工程（第２図（ｅ）の工程）で
チップ分離が困難となり、かつチップ寸法も制御が困難
となっていた。また、バイアホール３の四部に形成した
第１金属層３ａが半導は基板の裏面側に突出した部分が
第２金属ｊｍ５の突起部５ａとなるため、半導体装置裏
面の平坦度が得られなかった。In the conventional semiconductor device manufacturing method, as shown in FIG. 3, the second metal layer 5 is formed in one step (step in FIG. 2 (())).
In order to perform thick plating as described above, wrap-around growth portions 5b of the second metal layer 5 are generated in the parts where the resist is peeled off due to long-time processing, and chip separation occurs in the next process (the process shown in FIG. 2(e)). This has made it difficult to control the chip size. In addition, when the first metal layer 3a formed in the four parts of the via hole 3 is a semiconductor, the portion that protrudes toward the back side of the substrate becomes the protruding portion 5a of the second metal jm5, making it impossible to obtain the flatness of the back surface of the semiconductor device. Ta.
以上のＪ：うに、従来の半導体装置の製造方法では、グ
ーツブ分離が困難ｔで、かつ歩留りが悪いばかりでなく
、チップ寸法やチップ裏面の平坦度の精准が悪（、シｔ
こがって、チップの実装を行うにあたり組立てが困難で
あるという問題点があった。J: In the conventional manufacturing method of semiconductor devices, not only is it difficult to separate grooves and the yield is low, but also the precision of the chip dimensions and the flatness of the back surface of the chip is poor.
As a result, there is a problem in that assembly is difficult when mounting the chip.
この発明は、上記のような問題点を解消するなめになさ
れたもので、チップ分離が容易で、かつチップ寸法・チ
ップ裏面平坦度の精度の良好な半導体装置の製造方法を
得ることを目的とする。This invention was made to solve the above-mentioned problems, and aims to provide a method for manufacturing a semiconductor device that allows easy chip separation and has good accuracy in chip dimensions and chip back surface flatness. do.
この発明に係る半導体装置の製造方法は、半導体基板上
に回路パターンを形成し、的記半導体基板の裏面に形成
する第２金属層形成コニ程前に、半導体基板裏面をスク
ライブラインを残してエツチングすることによって、ス
クライブライン凸部を形成１， ｔ−後、第２金属層を
形成し、その後、第２金属層面を研暦し、ｒ１ｉ１記ス
クライブライン凸部の頭出しを行い、乙の頭出し部分よ
りダイシングしてデツプ分離を行うようにしたものであ
る。A method for manufacturing a semiconductor device according to the present invention includes forming a circuit pattern on a semiconductor substrate, and etching the back surface of the semiconductor substrate leaving a scribe line before forming a second metal layer on the back surface of the semiconductor substrate. After forming the scribe line convex part 1, t-, the second metal layer is formed, and then the surface of the second metal layer is polished, and the beginning of the scribe line convex part r1i1 is located. Dicing is performed from the exposed part to perform depth separation.
この発明においては、エツチングによってスクライブラ
イン凸部を形成することにより、第２金属層形成時のメ
ツキの横方向成長に影響されることなしにチップ幅を制
御できる。また、第２金属層の表面研磨工程は、的記ス
クライブライン凸部の頭出しによってチップ分離をｔＹ
Ｊ能にし、かつ基板裏面の第２の金ＴＡＪ！！表面が平
坦化される。In this invention, by forming the scribe line convex portion by etching, the chip width can be controlled without being affected by the lateral growth of plating during formation of the second metal layer. In addition, in the surface polishing process of the second metal layer, chip separation is achieved by locating the convex portion of the scribe line.
J function and the second gold TAJ on the back side of the board! ! The surface is flattened.
以下、乙の発明の一実施例を第１図（ａ）〜（（＋）に
ついて説明する。Hereinafter, an embodiment of the invention of B will be described with reference to FIGS. 1(a) to ((+)).
第１図（ａ）〜（ｅ）はこの発明の主要製造工程を示す
断面図で、１はＧ ａ Ａ ｓ等の半導体基板、１ａは
スクライブライン凸部、２は配線パターン（回路パター
ン）、３はバイアホール、３ａは第１金属層、４はスク
ライブラインフ第１・レジストパターン、５は第２金属
層、５ａは前記第２金属層５の突起部、５５はメツキ給
電金属層である。1(a) to (e) are cross-sectional views showing the main manufacturing steps of the present invention, in which 1 is a semiconductor substrate such as GaAs, 1a is a scribe line convex portion, 2 is a wiring pattern (circuit pattern), 3 is a via hole, 3a is a first metal layer, 4 is a scribe line first resist pattern, 5 is a second metal layer, 5a is a projection of the second metal layer 5, and 55 is a plating power supply metal layer. .
次に製造方法について説明する。Next, the manufacturing method will be explained.
まず、第１図（ａ）に示すように、半導体基板１上に配
線パターン２を形成し、さらに開式エツチング等により
バイアホール３を形成し、このバイアホール３の四部に
電解メツキ等によって第１金属層３ａを形成する。次に
、基板ｉＦ磨によって半導体基板１の厚みを約８０〜１
００−とする。次に、第１図（ｂ）に示すように、半導
体基板１裏面にスクライブラインフ第１・レジストパタ
ーン４を写真製版により形成し、このスクライブライン
フォトレジストパターン
板１裏面側を約５０〜７０ｐｍ程度湿式エツチングし、
バイアホール３の凹部に形成した第１金属廐３ａの一部
を半導体基板１の裏面側に露出せしめると共に、スクラ
イブラインフォトレジストパターン４のドのゝト導体基
板１部分をスクライブライン凸部１ａとする，、次に、
スクライブライン凸部１・レジストパターン４を除去し
、半導体基板１裏面側全面に蒸着，無電解メツキ等によ
ってメツキ給電金属層５５を形成した後、第１図（ｅ）
に示すように、メツキ給電金属層５５をカソード電極と
して電解メツキを行い、５０〜７〇−厚の第２金属層５
を形成する。続いて、第１図（ｄ）に示すように、第２
金属層５面を研磨し、第２金属層５の突起部５ａを除去
するとともに、スクライブライン凸部１ａの頭出しを行
う。その後、スクライブライン凸部１ａでグイシングし
、チップ分離を行って、第１図（ｅ）に示すような′Ｉ
４導体装置を得る。First, as shown in FIG. 1(a), a wiring pattern 2 is formed on a semiconductor substrate 1, a via hole 3 is formed by open etching, etc., and four parts of the via hole 3 are plated by electrolytic plating or the like. 1 metal layer 3a is formed. Next, the thickness of the semiconductor substrate 1 is reduced to about 80 to 1
Set to 00-. Next, as shown in FIG. 1(b), a scribe line first resist pattern 4 is formed on the back surface of the semiconductor substrate 1 by photolithography, and the back surface side of the scribe line photoresist pattern plate 1 is approximately 50 to 70 pm thick. Wet etching to a certain extent,
A part of the first metal protrusion 3a formed in the recess of the via hole 3 is exposed on the back side of the semiconductor substrate 1, and a portion of the conductive substrate 1 of the dot of the scribe line photoresist pattern 4 is exposed to the scribe line convex part 1a. Do,, then,
After removing the scribe line convex portion 1 and the resist pattern 4, and forming a plating power supply metal layer 55 on the entire back side of the semiconductor substrate 1 by vapor deposition, electroless plating, etc., as shown in FIG. 1(e).
As shown in FIG. 2, electrolytic plating is performed using the plating power supply metal layer 55 as a cathode electrode, and a second metal layer 5 with a thickness of 50 to 70 mm is formed.
form. Next, as shown in Figure 1(d), the second
The surface of the metal layer 5 is polished to remove the protrusions 5a of the second metal layer 5 and to locate the scribe line protrusions 1a. After that, the chips are separated by guising with the scribe line convex portion 1a, resulting in 'I' as shown in FIG. 1(e).
A four-conductor device is obtained.
なお、上記’Ａｋ例では、バイアホール３をイｊする半
導体装置の！！Ｉ！！造方法について説明したが、バ、
イアホール３を有しない半導体装ＩＩ？＃の製造方法に
おいても同様の効果を右する。また、半導体基板１とし
てＧａＡｇを用いた場合について説明したが、化合物半
導体基板，Ｓｉ基板ｐ Ｓｔ基板上に同種または異種の
半導体をエピタキシャル成長させた基板等についても同
様に適用できるものである。In addition, in the above example 'Ak, the semiconductor device in which the via hole 3 is ! ! I! ! Although I explained the manufacturing method,
Semiconductor device II without earhole 3? Similar effects can be obtained in the manufacturing method of #. Further, although the case where GaAg is used as the semiconductor substrate 1 has been described, the invention can be similarly applied to a compound semiconductor substrate, a substrate in which the same or different types of semiconductors are epitaxially grown on a Si substrate or a pSt substrate.
以上説明したように、この発明は、半導体基板の第１の
面に回路パターンを形成する工程，半導体基板の第１の
面と反対側の第２の面に、スクライブラインフォトレジ
ストパターンを形成する工程，スクライブラインフォト
レジストパターンマスクとして半導体基板をエツチング
し、スクライブラインフォトレジストパターン
ブライン凸部を形成する工程，スクライブラインフ第１
・レジストパターンを除去した後、半導体基板の第２の
面全面に厚い金属層を形成する工程。As explained above, the present invention includes a step of forming a circuit pattern on a first surface of a semiconductor substrate, and a step of forming a scribe line photoresist pattern on a second surface of the semiconductor substrate opposite to the first surface. Process: Etching the semiconductor substrate as a scribe line photoresist pattern mask to form scribe line photoresist pattern brine convex parts; scribe line photoresist pattern first
- After removing the resist pattern, a step of forming a thick metal layer over the entire second surface of the semiconductor substrate.
半導体基板の第２の面に形成した厚い金属層の面を研暦
して、スクライブライン凸部の頭出１ノを行うと共に、
半導体基板の第２の面に形成した厚い金属層の面を平坦
化する工程，スクライブライン凸部をグイシングし、チ
ップ分離を行う工程とからなるので、スクライブライン
幅は第２金ｈ１５層の横方向成長に影響されず、したが
って、チップ寸法やチップ裏面の平坦度の精度が良好で
、かつチップ分離が容易に行え、さらに半導体装置慨向
側の凡ビ坦度も得られるという効果があ６。The surface of the thick metal layer formed on the second surface of the semiconductor substrate is polished to locate the convex portion of the scribe line, and
The process consists of a process of flattening the surface of the thick metal layer formed on the second surface of the semiconductor substrate, and a process of guising the scribe line convex part and separating the chips. It is unaffected by directional growth, and therefore has good accuracy in chip dimensions and flatness on the back side of the chip, facilitates chip separation, and also provides approximately flatness on the front side of the semiconductor device. .
第１図（ａ）〜（ｅ）はこの発明の一実施例の半導体装
置の製造方法を示す主要工程断面図、第２図（ｎ）〜（
ｅ）は従来の半導体装置の製造方法の主要−り程を示す
断面図、第３図は、第２図（ｄ）の工程における問題点
を示した主要部の拡大断面図である。
図において、１ば半導体基板、１ａはスクライブライン
凸部、２は配線パターン、３−はバイアホール、３ａは
第１金属層、４はスクライブラインフォトレジストパタ
ーン、５は第２ 金属層、５ ａは第２金属層の突起部
、５５はメツキ給電金属層である．。
なお、各図中の同一符号は同一または相当部分を示す。
代理人 大 岩 増 雄 （外２名）第１図
第１図
第２図
第２図
第３図FIGS. 1(a) to (e) are main process cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS. 2(n) to (
FIG. 3 is an enlarged sectional view of the main part showing problems in the process of FIG. 2(d). In the figure, 1 is a semiconductor substrate, 1a is a scribe line convex portion, 2 is a wiring pattern, 3- is a via hole, 3a is a first metal layer, 4 is a scribe line photoresist pattern, 5 is a second metal layer, 5a 55 is a protrusion of the second metal layer, and 55 is a plating power supply metal layer. . Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 Figure 1 Figure 2 Figure 2 Figure 3
Claims (1)
、前記半導体基板の第１の面と反対側の第２の面に、ス
クライブラインフォトレジストパターンを形成する工程
、前記スクライブラインフォトレジストパターンをマス
クとして前記半導体基板をエッチングし、前記スクライ
ブラインフォトレジストパターン下にスクライブライン
凸部を形成する工程、前記スクライブラインフォトレジ
ストパターンを除去した後、前記半導体基板の第２の面
全面に厚い金属層を形成する工程、前記半導体基板の第
２の面に形成した厚い金属層の面を研磨して、前記スク
ライブライン凸部の頭出しを行うと共に、前記半導体基
板の第２の面に形成した厚い金属層の面を平坦化する工
程、前記スクライブライン凸部をダイシングし、チップ
分離を行う工程を含むことを特徴とする半導体装置の製
造方法。forming a circuit pattern on a first surface of a semiconductor substrate; forming a scribe line photoresist pattern on a second surface opposite to the first surface of the semiconductor substrate; etching the semiconductor substrate as a mask to form a scribe line protrusion under the scribe line photoresist pattern; and after removing the scribe line photoresist pattern, etching a thick metal layer over the entire second surface of the semiconductor substrate; The step of forming a thick metal layer formed on the second surface of the semiconductor substrate is performed by polishing the surface of the thick metal layer formed on the second surface of the semiconductor substrate to locate the convex portion of the scribe line. A method for manufacturing a semiconductor device, comprising the steps of flattening a surface of a metal layer, dicing the scribe line convex portion, and separating chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26843887A JPH0777265B2 (en) | 1987-10-22 | 1987-10-22 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26843887A JPH0777265B2 (en) | 1987-10-22 | 1987-10-22 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01109754A true JPH01109754A (en) | 1989-04-26 |
| JPH0777265B2 JPH0777265B2 (en) | 1995-08-16 |
Family
ID=17458498
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26843887A Expired - Lifetime JPH0777265B2 (en) | 1987-10-22 | 1987-10-22 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0777265B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5200641A (en) * | 1990-10-04 | 1993-04-06 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device structure including bending-resistant radiating layer |
| JP2005504445A (en) * | 2001-10-01 | 2005-02-10 | エグシル テクノロジー リミテッド | Processing of substrates, especially semiconductor wafers |
| JP2013243287A (en) * | 2012-05-22 | 2013-12-05 | Disco Abrasive Syst Ltd | Method for processing plate-like object |
-
1987
- 1987-10-22 JP JP26843887A patent/JPH0777265B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5200641A (en) * | 1990-10-04 | 1993-04-06 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device structure including bending-resistant radiating layer |
| JP2005504445A (en) * | 2001-10-01 | 2005-02-10 | エグシル テクノロジー リミテッド | Processing of substrates, especially semiconductor wafers |
| JP2013243287A (en) * | 2012-05-22 | 2013-12-05 | Disco Abrasive Syst Ltd | Method for processing plate-like object |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0777265B2 (en) | 1995-08-16 |
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