JPS63193545A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To decrease grounding inductance and to enhance high frequency characteristics, by depositing a first metal layer the bottom of a through hole in a semiconductor substrate, thinning the semiconductor substrate so as to expose the first metal layer, and forming a second metal layer on the semiconductor substrate. CONSTITUTION:A grounding electrode 16a is formed on the first main surface of a semiconductor substrate 100. The substrate 100 is thinned to a desired thickness. A mask layer 18 having a hole at a part of the other main surface of the substrate 100. The substrate 100 is etched through the hole, and through holes 19 reaching the electrode 16a are formed. First metal layers 20a and 20b are deposited on the other surface of the substrate 100 and the bottom of each through hole 19 so that the layer in the hole is not connected to the layer on the main surface. The metal layer 20b on the mask layer 18 is removed together with the mask layer 18. The substrate 20a is thinned so as to expose the metal layer 20a. A second metal layer 21 is formed on the other main surface of the substrate 100, and the metal layer 21 is connected to the metal layer 20a. Thus the grounding inductance is decreased, and the high frequency characteristics are enhanced.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor integrated circuit, and in particular, to a method for manufacturing a semiconductor integrated circuit, and particularly to a method for grounding a microwave monolithic integrated circuit (hereinafter abbreviated as MMIC) having a via hole structure. Applies to means.

(Prior art) In order to improve the characteristics of MMIC using gallium arsenide (GaAs) and reduce the variation in characteristics, it is necessary to reduce the grounding inductance of the active element (FET) part and the matching circuit part, and to adjust its value. It is necessary to avoid variations. A method using a via hole structure, which is advantageous for reducing inductance and miniaturizing the device, is often used for grounding the IC.

Hereinafter, a conventional example of a method for manufacturing an MMIC in which a source electrode and a lower electrode of a capacitor constituting a matching circuit element are connected to a ground electrode through a via hole structure will be described with reference to FIGS. 2a-e.
Explain with reference to.

As shown in FIG. 2a, an active layer (N layer) 101 is formed on a GaAs semi-insulating substrate 100 by ion implantation. Resistance layer CN layer) 102. After selectively forming an ohmic contact layer (N layer) 1o3, a source, a drain, and a
Patterning is performed for each electrode of the resistance layer, and gold germanium (AuGe) is deposited. Subsequently, after forming each electrode pattern by a lift-off method, it is heated to 450°C to perform alloying, and the source electrode 104s+drain electrode 104 is formed.
d, resistive layer electrode 105a and LO5b are formed. Next, the gate electrode and the capacitor base electrode constituting the matching circuit element are patterned by photolithography, aluminum (Al1) is deposited, and the gate electrode 104g and the capacitor base electrode 1068 constituting the matching circuit are formed by lift-off.

Next, as an insulating film for a capacitor constituting a matching circuit element, for example, a 5LBN4 layer 107 is deposited by plasma CVD (Che
The source electrode 104s, drain electrode 104d,
First, openings are formed on each electrode of the gate electrode 104g, and then the upper surface electrode of the capacitor constituting the matching circuit element is patterned by photolithography, and titanium (Ti), gold (
Au) is sequentially deposited and lifted off to form a matching circuit element. , 106b (FIG. 2b) 6 Next, the front side of the aAs semi-insulating substrate 100 is attached to, for example, a support plate of a quartz plate 108 with wax 109, and the thickness of the substrate is After thinning to about 100p, AZ1350J, an example of photoresist
(trade name, manufactured by Sibley) by photolithography to form a via hole mask M110 (see Fig. 2C).
). This mask layer 110 is a GaAs semi-insulating substrate 100.
A source electrode 104s formed on the surface of the source electrode 104s.

It is aligned with the capacitor base electrode 106a that constitutes the matching circuit element. Next, the GaAs substrate 100 is etched using a phosphoric acid-based etching solution to form a via hole 111 that reaches the source electrode 104s and the capacitor base electrode 106a. Subsequently, the via hole mask layer 110 is formed using, for example, J-100 (trade name).
(Fig. 2d).

Next, the back side of the GaAs semi-insulating substrate 100 and the inside of the via hole 111 are coated with Au by evaporation or plating.
The back electrode 112 is formed by depositing about 1000 ml of oxide, and is electrically connected to the source electrode 104s and the capacitor base electrode 106. Here, FIG. 3 shows a GaAs semi-insulating substrate 1.
00 thickness (depth of via hole 111) is 100 μm
This is a diagram in which the state of electrical continuity between the source electrode surface and the back electrode was investigated by changing the thickness of the back electrode. As is clear from this figure, in order to achieve 100% electrical continuity between the source electrode surface and the back electrode, the back electrode 112
It is necessary to make the thickness 10 μs or more. Therefore, when forming the back electrode, its thickness should be 107ffi or more. Next, elements are separated using a blade dicer, and finally the elements are peeled off from the quartz plate 107 to form an MM as shown in FIG. 2e.
IC is obtained.

(Problems to be Solved by the Invention) The MMIC obtained by the above conventional method has a sufficiently small grounding inductance and excellent high frequency characteristics. However, in this MMIC, the thickness of the A1 layer of the back electrode 112 is 10
Since the thickness is as thick as tIIM, element separation cannot be achieved using a diamond cutter, which is commonly used for element separation, and a blade dicer or the like must be used. As a result, the brittle nature of GaAs causes chipping and cracking of the device, leading to a significant drop in yield, and as a result, the manufacturing cost of the MMIC becomes extremely high upon completion of device separation.

In addition, in order to facilitate separation using a diamond cutter for element isolation, the thickness of the back electrode must be reduced to several thousand layers, and the capacitor electrode and back electrode that constitute the source electrode and matching circuit element must be thinned. The electrical conductivity between the two ends is significantly reduced.

In view of the above conventional problems, the present invention provides an improved method for manufacturing a semiconductor integrated circuit.6 [Configuration of the Invention] (Means for Solving the Problems) A method for manufacturing a semiconductor integrated circuit according to the present invention. teeth.

A process of forming a grounding electrode on one main surface of a semiconductor substrate.

a step of thinning the semiconductor substrate to a desired thickness, a step of forming a mask layer having an opening on a part of the other main surface of the semiconductor substrate, and etching the semiconductor substrate through the opening to form the ground electrode. a step of forming a through hole that reaches the semiconductor substrate, a step of depositing a first metal layer on the other main surface of the semiconductor substrate and the bottom of the through hole without being connected thereto;
removing the metal layer along with the mask layer by lift-off, thinning the semiconductor substrate so that the first metal layer is exposed, and forming a second metal layer on the other main surface of the semiconductor substrate. The method includes a step of connecting this to the first metal layer at the bottom of the through hole.

(Function) In this invention, since the thickness of the back electrode can be made thin, elements can be separated using a commonly used diamond cutter.Furthermore, the electrical connection between the grounding electrode and the back electrode can be made completely, so that the grounding inductance can be reduced. It is possible to form an MMIC with a small resistance and excellent high frequency characteristics.

(Example) An example of the present invention will be described below with reference to FIG.

First, the active layer (N layer) on the GaAs semi-insulating substrate 100
11 and the area where the resistance layer 12 is to be formed.
Silicon (
Si) ions are selectively implanted. Next, an acceleration energy of 120Ke is applied to the area where the ohmic contact layer (N layer) 13 is planned to be formed.
V and 250Ke V, dose amount 2 x 1013an
-'' Si ions are selectively implanted.Subsequently, at 850℃
The active layer 1 is annealed to activate the Si ions.
1. A resistive layer 12° ohmic contact pIj13 is formed (FIG. 1a).

Next, on the ohmic contact layer 13 and the resistive layer 12, patterning for the source, drain, and resistive layer electrodes is performed by photolithography, and AuGe is deposited.

Subsequently, each electrode pattern is formed by a lift-off method, and then alloyed at a temperature of 450° C. to form a source electrode 14s, a drain electrode 14d, and resistance layer electrodes 15a and 15b. Next, the gate electrode 14g and the capacitor base electrode are patterned by photolithography, AQ is deposited, and the electrode 14g and the capacitor base electrode 16a are formed by lift-off (FIG. 1b).

Next, the insulating layer 17 for the capacitor is formed by plasma CVD.
After the film is deposited to a thickness of 2,000 layers using the photolithography method and the plasma etching method using CF, openings are formed on each of the source electrode 14s, drain electrode 14d, and gate electrode 14g. The top electrode is patterned and Ti is deposited by vapor deposition.

Au is sequentially deposited and lift-off is performed to form a capacitor upper mold vi16b (FIG. 1C).

Next, a quartz plate 1 is placed on the surface side of the GaAs semi-insulating substrate 100.
08 is adhered with wax 109, and the first thinning is performed to a thickness of 150p by lapping and chemical boriding. Next, an AZ1350J (trade name, manufactured by Sibley Inc.) layer is formed as a mask layer 18 for via holes and lift-off by forming holes directly below each of the source electrode 14s and the capacitor base electrode 16a by photolithography.

Next, the GaAs substrate 100 is etched using an etching solution of phosphoric acid:hydrogen peroxide:water=3:4:1 to form a via hole 19 reaching the source electrode 14s and the capacitor base electrode 16a. At this time, the via hole mask layer 18 becomes eaves-like with respect to the opening of the via ball 19 due to side etching that occurs when the GaAs substrate 100 is etched.

Next, as the first metal, the Au layer is made of GaAs to a thickness of 10 mm.
First metal layers 20a, 20b are formed by vapor deposition over the entire surface of the semi-insulating substrate 100 from the back side (FIG. 1d). Here, the side surface near the open end of the via hole 19 directly above the eave-like part of the via-hole and lift-off mask layer 17 is not vapor-deposited because the eave-like part blocks the vapor-deposited metal particles. Therefore, the vapor-deposited first metal layer 20a,
20b is divided into a first metal layer 20a deposited from the bottom of the via hole to a portion close to the open end, and a first metal layer 20b deposited on the lift-off mask layer 18.

Next, the first metal layer 20b deposited on the via hole and lift-off mask layer 18 is coated with acetone or J-10.
Lift-off is performed using 0 (trade name, release agent manufactured by Nagase Sangyo Co., Ltd.) (Fig. 1 e).

Note that the portion of the opening of the via hole to which the first metal layer is not deposited is removed in a second thinning process of the substrate performed later, and the first metal layer at the bottom of the via hole is removed during the formation of the back electrode. 420a and the back electrode are connected to achieve electrical connection.

Next, a second thinning process is applied to the GaAs semi-insulating substrate 100, which is achieved by lapping and chemical boring to a thickness of 100 μm. At this time, via hole 19
The end of the first metal M20a formed on the side surface is made of Ga.
The As semi-insulating substrate 100 is fully exposed directly on the surface (the first
Figure f).

Next, an Au layer with a thickness of 5000 mm was deposited as a second metal layer on the back side of the GaAs semi-insulating substrate 100, and the back electrode 21
form. Then, wax 109 is dissolved and GaAs
The semi-insulating substrate 100 is separated from the quartz plate 108. Finally, elements are separated using a diamond cutter to obtain an MMIC (FIG. 1g).

As described above, the back electrode 21 has an Au layer with a thickness of 50 mm.
Since it is formed as thin as 0.00 mm, element isolation can be easily achieved by a commonly used method using a diamond cutter. As a result, the thickness of the first metal layer in the via hole is 10 - without causing a decrease in device yield, and the source electrode 104s and the capacitor base electrode 1
A complete connection between 6a and the back electrode 21 was achieved.

In the above example, AZ1350J was used as a mask for via holes and lift-off, but the material is not limited to this, and other mask materials such as OMR (trade name,
(manufactured by Tokyo Ohka Kogyo), HPR (trade name, manufactured by Fuji Hunt), etc., or a silicon oxide (SiOz) layer, a silicon nitride (Si3 N4) layer, a lift-off metal, etc., or a combination thereof, such as Sun.

10MR, OMR/metal, SL, N,/metal, etc. may be used.

Also, acetone as a solvent for lift-off.

J-100 was used, but the material was SiO□ for the mask material.
.

When a material such as 513 N4 r AR is used, the solvent is changed depending on the material of the mask material, such as using hydrofluoric acid (HF).

Furthermore, although the second thinning of the (1; aAs semi-insulating substrate was performed by lapping and chemical boriding, it may also be performed by wet etching using phosphoric acid, sulfuric acid, etc.).

Further, although an example has been shown in which via holes are formed by wet etching using a phosphoric acid solvent, they can also be formed by reactive ion etching (RIE) or the like. However, in the case of RIE, the mask material for via holes and lift-off is also etched, so the mask material for via holes and lift-off should be a metal-based material with excellent etching resistance, or a material such as S x 3 N 4 /metal. It is preferable to do so.

〔Effect of the invention〕

According to this invention, since the thickness of the back electrode can be reduced as described above, elements can be easily separated using a commonly used diamond cutter, and the electrical connection between the grounding electrode and the back electrode can also be completely established. It can be achieved. This results in an MMIC with low grounding inductance and excellent high frequency characteristics.
It has the remarkable advantage that it can be manufactured with high yield and good reproducibility.

[Brief explanation of the drawing]

Fig. 1 g - y g are cross-sectional views showing the manufacturing process of the MMIC according to the present invention, and Fig. 2 a - e are cross-sectional views showing the manufacturing process of the MMIC according to the present invention.
Both are cross-sectional views showing the manufacturing process of the IC, and FIG. 3 is a diagram showing the conduction yield between the source electrode and the back electrode when the thickness of AJ5 in the via hole is changed. 11, 101... Operating layer 12, 102... Resistance layer 13, 103... Ohmic contact layer 14s, 104s... Source electrode 14d, 104d... Drain electrode 14g, 104
g...Gate electrodes 15a, 15b, 105a, 105b''/resistance layer electrodes 16a, 106a...Capacitor base electrode 16
b, 106b... Capacitor top electrode 17, 107
...Insulating layer 18...Via hole mask layer 19...Via holes 20a, 20b...First metal layer 21...Second metal layer 100...GaAs semiconductor substrate agent Patent attorney I Top - Man (αn 1st figure ζ璽υl) Figure 1 (layer ψ2) /Q2 103 tot 103 2nd cause (N's 1st

Claims (1)

[Claims] a step of forming a grounding electrode on one main surface of the semiconductor substrate, a step of thinning the semiconductor substrate to a desired thickness, a step of forming a mask layer having an opening on a part of the other main surface of the semiconductor substrate, etching the semiconductor substrate through the opening to form a through hole that reaches the grounding electrode; depositing a first metal layer on the other main surface of the semiconductor substrate and at the bottom of the through hole without connection thereto; a step of removing the first metal layer on the mask layer together with the mask layer by lift-off, a step of thinning the semiconductor substrate so that the first metal layer is exposed; A method for manufacturing a semiconductor integrated circuit, including the step of forming a second metal layer on a surface and connecting the second metal layer to the first metal layer at the bottom of the through hole.