JPH11214405A - Sic semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an SiC semiconductor device that can eliminate break of a gate wiring, etc., and realizing IC by making a step of a gentle angle. SOLUTION: On an SiC semiconductor layers 2 and 3, a mask pattern 4 made of a material having an etching speed of more than that of the semiconductor layers 2 and 3, and the SiC semiconductor layers 2 and 3 are etched by an RIE(Reactive Ion Etching) method, and the SiC semiconductor layer 2 and 3 are etched into a tapered shape, and a mesa form is formed. The tapering angle formed by etching is preferably 10 to 75 deg..

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device using a SiC semiconductor and a method for manufacturing the same.

[0002]

2. Description of the Related Art SiC semiconductors, which are being developed as materials for optical semiconductor elements such as light-emitting diodes and semiconductor lasers, are thermally and scientifically stable and have excellent radiation resistance. And as a material for high-power devices.

[0003] SiC semiconductors have been developed as materials for high-frequency semiconductor devices because they have an electron mobility about two to three times larger than GaAs semiconductors.

With respect to conventional SiC semiconductor electronic devices, SiC MESFETs are based on IEEE, GaAs ICs.
Symposium 19, 1993 and the like.

FIG. 7 shows the structure of a conventional SiC MESFET.
It will be described with reference to FIG.

FIGS. 7 to 9 show a state in which a SiC semiconductor layer is etched to separate elements by a conventional RIE (reactive ion etching) method. FIG. 7 is a sectional view, and FIG. FIG. 9 is a sectional view taken along the line cc ′ of FIG.

As shown in FIG. 7, a p-type SiC epitaxial layer 55 is formed on an n-type SiC substrate 54, and an n-type SiC epitaxial layer 56 is further grown thereon. After a Ni vapor-deposited film 57 serving as a mask is patterned on the n-type SiC epitaxial layer 56, an RIE method using CF ₄ gas for element isolation is performed.
Dry etching is performed so as to reach the p-type SiC layer epitaxial layer 55, and a separation groove is formed. A step is formed by the separation groove.

Next, as shown in FIG. 8, nickel (N
The source electrode 58 and the drain electrode 59 are formed by evaporating and patterning i), and gold (A) is formed.
u), a gate electrode 60 composed of a Schottky junction electrode such as platinum (Pt) is formed.

Here, as shown in FIG. 9, the wiring of the gate electrode 60 includes a step.

[0010]

Since the above-mentioned step has an angle of about 90 ° (80 to 90 °), that is, 80 ° or more, the step coverage deteriorates, and the wiring for the gate electrode is formed at the step. Disconnection easily occurs, which has been a major problem in terms of manufacturing electronic devices and reliability.

In order to prevent disconnection at the step,
Although there is a method of increasing the thickness of the gate wiring, there is a problem that thickening the gate wiring deteriorates the passivation provided thereon.

As described above, the step formed by forming the conventional device isolation groove has an angle of 80 ° or more, so that there is a problem that it is extremely difficult to form an IC having various wiring patterns. .

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems. An SiC semiconductor capable of reducing the angle of a step, eliminating disconnection of a gate wiring, etc., and achieving IC integration. Its purpose is to provide a device.

[0014]

SUMMARY OF THE INVENTION According to the present invention, there is provided a SiC semiconductor layer in which an element is separated by a separation groove formed by etching.
A C semiconductor device, wherein the separation groove has a tapered shape.

Further, the present invention is a SiC semiconductor device in which an operating layer made of a SiC semiconductor is thinned by etching, wherein an end of the operating layer is tapered.

According to the manufacturing method of the present invention, a mask made of a material having an etching rate higher than that of the semiconductor layer is provided on the SiC semiconductor layer, and the SiC semiconductor layer is formed by dry etching.
The C semiconductor layer is etched, and the SiC semiconductor layer is etched in a tapered shape.

The taper angle formed by etching is 10 to 75 °.

According to the present invention, a mask is formed with a material having an etching rate higher than that of a SiC semiconductor, and the mask is formed by RIE.
By etching the C semiconductor, the mask is degenerated during the etching process, and the surface of the SiC semiconductor is gradually exposed, so that the SiC semiconductor can be etched in a tapered state.

For example, RIE conditions, 300 W , CF ₄
With a gas of 10 SCCM, the etching rate of the SiC semiconductor is 400 Å / min. The etching rate of a natural rubber-based photoresist or a phenol novolak-based photoresist is 800 Å / min, and that of an Al deposited film is 400 Å / min.

Here, when a natural rubber-based photoresist having an etching rate higher than that of the SiC semiconductor is used as a RIE selection mask, for example, since the etching rate ratio with respect to the SiC semiconductor is twice, about 26 ° C. Mesa etching having a taper angle of? When the Al deposited film is used as a selection mask for RIE, the etching rate ratio with respect to the SiC semiconductor is the same, and the angle is about 75 ° due to the difference between the depth direction and the lateral etching rate of the Al deposited film. Mesa etching becomes possible.

The adjustment of the taper angle of the etching by RIE can be performed by a method such as selecting a material of the mask or forming a taper in the mask in advance.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a SiC semiconductor device having a tapered etching mesa shape according to the present invention will be described below.

FIG. 1 is a sectional view showing a first embodiment of a method of manufacturing a SiC MESFET in each step, and FIG. 2 is a plan view of the same.

First, as shown in FIG.
On a main surface of a C substrate 1, a p-type SiC epitaxial layer 2 having a thickness of about 5.0 μm and an n-type SiC epitaxial layer 3 having a thickness of about 0.2 μm are sequentially formed. On the main surface of this wafer,
For example, an RIE selection mask pattern 4 made of a natural rubber-based photoresist is formed. In this embodiment, the trade name “OMR” manufactured by Tokyo Ohka Co., Ltd. was used as the natural rubber-based photoresist 4. At this time, the mask pattern 4 having the tapered shape 5 is formed by performing the proximity exposure processing. The thickness of the photoresist in the mask pattern 4 is about 2 μm.

Next, as shown in FIG.
W , CF ₄ gas, 10 SCCM, RI for 20 minutes
The process of E6 is performed to etch the n-type SiC epitaxial layer 3 and the p-type SiC epitaxial layer 2 by about 0.8 μm. The etching rate of SiC under the RIE conditions is 400 angstroms / min, and the etching rate of a natural rubber-based photoresist is 800 angstroms / min.

As a result, the etching process of the SiC proceeds while the mask pattern 4 made of the photoresist is degenerated by the RIE process, so that the SiC semiconductor film is etched in a tapered shape to perform element isolation.

In this step, a mesa shape 7 having a taper angle of about 20 ° is formed.

Next, as shown in FIGS. 1C and 1D, after the remaining photoresist film is removed and the surface is cleaned, the source electrode 8 and the drain electrode 9 are subjected to Ni deposition and patterning. , Formed by heat treatment. And
The gate electrode 10 is formed as a Schottky junction electrode using a Pt lift-off technique.

As described above, by forming the gate electrode 10 on the mesa shape 7 having a taper angle of about 20 °, the step coverage of the gate electrode 10 is reduced as shown in FIGS. And the fear of disconnection disappears.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a cross-sectional view showing a second embodiment of the method of manufacturing the SiC MESFET for each process.

As shown in FIG. 3A, as in the first embodiment described above, the n-type SiC substrate 1 has p-type S
For example, a phenol novolak photoresist is applied to the main surface of the wafer on which the iC epitaxial layer 2 and the n-type epitaxial layer 3 are sequentially formed, and exposed and developed to form a mask pattern 4a. In this embodiment, the product name “OFPR8600” manufactured by Tokyo Ohka Co., Ltd. was used.
Incidentally, the thickness of the photoresist of the mask pattern 4a is about 2 μm.

The second embodiment differs from the first embodiment in that no taper is provided in the mask pattern 4a.

Next, as shown in FIG.
W , CF ₄ gas, 10 SCCM, RI for 20 minutes
The process of E6 is performed to etch the n-type SiC epitaxial layer 3 and the p-type SiC epitaxial layer 2 by about 0.8 μm. Under these RIE conditions, the etching rate of SiC is 400 Å / min, and the etching rate of phenol novolak photoresist is 80.
0 Å / min.

As a result, the etching of SiC proceeds while the photoresist 4a is degenerated by the RIE process, so that the SiC semiconductor film is etched in a tapered shape. At this time, since the mask pattern 4a made of the photoresist does not have a taper as in the first embodiment described above, the mask pattern 4a at the edge of the resist due to degeneration is formed.
The time required to expose the C semiconductor surface is longer than in the first embodiment.

Therefore, in this embodiment, a mesa shape 7 having a taper angle of about 30 ° is formed in this step.

Next, as shown in FIG. 3C, after the remaining photoresist film is removed and the surface is cleaned,
The source electrode and the drain electrode are formed by Ni vapor deposition and patterning and heat treatment. Then, a gate electrode 10 composed of a Schottky junction electrode is formed by using a Pt lift-off technique.

In order to further increase the angle of the tapered shape, the difference between the etching rate and the SiC semiconductor may be reduced. For example, if an Al deposited film is used as a mask, the etching rate of the Al deposited film is determined under the above conditions.
400 angstrom / min, and a taper angle of about 75 ° can be obtained due to the difference between the etching rate in the depth direction and the etching rate in the lateral direction. Further, when a taper as shown in FIG.
° can be smaller.

FIG. 4 is a sectional view showing a third embodiment in which the present invention is applied to a SiC bipolar transistor.

An n-type SiC substrate 10 serving as a collector region
After a p-type SiC epitaxial layer 11 serving as a base region is formed on the main surface of the substrate, a portion that is joined to the emitter region is removed by etching to reduce the operating voltage so as to reduce the thickness. In this etching for thinning, the edge of the operation layer is tapered by using the above-described RIE etching method according to the present invention. That is, except for the part to be thinned,
A mask pattern made of a material having an etching rate equal to or higher than the etching rate of the SiC semiconductor is provided, and the operation layer in the base region is thinned by RIE. By this thinning, a mesa shape is formed, and a predetermined taper is formed at the end of the operation layer.

Subsequently, an n-type SiC epitaxial layer 12 to be an emic region is formed by molding. As a result, since the end portions of the base region 11 and the emitter region 12 are formed in a tapered shape, the electric field concentration in this portion is reduced, and
The breakdown voltage is improved.

Next, Ni electrodes 13 and 14 are deposited and patterned on the emitter region 12 and the elector region 10 and then heat-treated.
The electrode 15 is formed. Then, after heat treatment in Ar at about 1000 ° C., for example, a silicon nitride film (Si
₃ N ₄₎ to form a protective film 16 made of, SiC bipolar transistor according to the invention is obtained.

FIG. 5 shows a SiC diode and a SiC ME
FIG. 11 is a sectional view showing a fourth embodiment of the present invention in which an SFET is formed into an IC. The main surface of the n-type SiC substrate 27 has p-type Si
The main surface of the wafer on which the C epitaxial growth layer 28 and the n-type SiC epitaxial growth layer 29 are sequentially formed is subjected to mesa etching 30 having a predetermined taper angle by using the RIE etching method of the present invention.

Next, the source is added to the MESFET region 31.
The Ni electrode serving as the electrode 32 and the drain electrode 33 is
Ni electrode serving as cathode electrode 35 is formed in cathode region 34
I do. The cathode electrode 35 of the diode and the MESFET
The source electrode 32 is made of SiO _TwoThe distribution formed on the film 36
Connected by the Au / Ti film of the line pattern electrode 37
I have. Also, the gate electrode 38 of the MESFET and the diode
Anode electrode 39 is formed by an Al electrode.
You.

By the combination of the diode and the MESFET, the current between the source and the drain of the MESFET can be controlled by the small current of the diode, and this is made possible by realizing the mesa-shaped etching of the SiC semiconductor. is there.

FIG. 6 shows a SiC photodiode and a SiC
FIG. 14 is a sectional view showing a fifth embodiment of the implementation of the MESFET as an IC. The MESFET region 31 and the photodiode region 34 are separated by a V groove 36. Since the diode of FIG. 5 has the same configuration except that it functions as a photodiode, the same portions are denoted by the same reference numerals and description thereof will be omitted to avoid redundant description.

The source / drain current of the MESFET is controlled by a minute current change of the photodiode due to light irradiation 39 on the photodiode. Further, in this embodiment, there is also an effect that the response of light is increased only in the tapered portion.

In each of the above embodiments, S
Although the iC epitaxial layer is removed by etching to form a tapered shape, the SiC substrate itself may be removed by etching to form a tapered shape.

[0048]

As described above, according to the present invention, the disconnection of the wiring at the step can be prevented, and the IC using the SiC semiconductor can be easily achieved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of a method for manufacturing a SiC MESFET for each process.

FIG. 2 is a plan view showing the first embodiment of the method for manufacturing the SiC MESFET.

FIG. 3 is a sectional view illustrating a second embodiment of the method of manufacturing the SiC MESFET for each process.

FIG. 4 is a sectional view showing a third embodiment in which the present invention is applied to a SiC bipolar transistor.

FIG. 5 shows I of SiC diode and SiC MESFET.
It is sectional drawing which shows the 4th Embodiment of this invention which converted into C.

FIG. 6: SiC photodiode and SiC MESFE
It is sectional drawing which shows 5th Embodiment of IC conversion of T.

FIG. 7 shows an example of a conventional RIE method for isolating elements.
It is sectional drawing which shows the state which etched the iC semiconductor layer.

FIG. 8 is a plan view as seen from above in FIG. 7;

9 is a sectional view taken along line c-c 'of FIG.

[Explanation of symbols]

 Reference Signs List 1 n-type SiC substrate 2 p-type SiC epitaxial layer 3 n-type epitaxial layer 4 mask pattern 7 mesa shape

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/8232 H01L 29/72 29/16 29/91 F 21/331 29/73 29/861

Claims (4)

[Claims] 1. An SiC semiconductor device in which an element is separated from a SiC semiconductor layer by a separation groove formed by etching, wherein the separation groove has a tapered shape. 2. An SiC semiconductor device in which an operating layer made of a SiC semiconductor is thinned by etching, wherein an end of the operating layer is tapered.
iC semiconductor device. 3. A mask made of a material having an etching rate higher than that of the semiconductor layer is provided on the SiC semiconductor layer,
A method for manufacturing a SiC semiconductor device, comprising: etching the SiC semiconductor layer by dry etching; and etching the SiC semiconductor layer in a tapered shape. 4. The method according to claim 3, wherein a taper angle formed by etching is 10 to 75 °.