JP2000269236A - Compound semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restrain a gate leakage current from occurring between a gate electrode and a transistor operating region, so as to obtain a compound semiconductor device of high reliability. SOLUTION: A trapezoidal transistor operating layer is formed on a semi- insulating GaAs substrate 1, insulating films 5 and 6 are provided above and around the operating layer, and a source electrode, a drain electrode, and a gate electrode 8 are brought into contact with the operating layer which penetrates through a part of the insulating films formed on the surfaces of the operating layers. An insulating layer is formed of an SiN film 5 and an SiO2 film 6, where the SiN film 5 is provided around the electrode 8 at the upper part of the trapezoid, making its under surface come into contact with the substrate 1 around the trapezoid so as to be flush with or lower than top surface of the trapezoid, and the SiO2 film 6 is provided so as to cover the SiN film 5 except for the top surface of the trapezoid.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a MESFET.
(Metal Semicondoctor Field Effect Transister),
HEMT (High Electron Mobility Transistor) or TMT (Two Mode channel field effect Transistor)
r) and a method for manufacturing the same.

[0002]

2. Description of the Related Art An example of a conventional compound semiconductor device having a hetero junction composed of a plurality of heterogeneous compound semiconductor layers will be described with reference to FIGS. 6 and 7 show a MESFET using a compound semiconductor substrate. FIG. 6 is a plan view, and FIG. 7 is a sectional view taken along line AA of FIG.

As shown in FIG. 1, an MESFET has an n-type GaAs layer 52, an undoped AlGaAs layer 53 and an undoped GaAs layer 5 on a semi-insulating GaAs substrate 51.
4 are formed in this order by epitaxial growth. Then, it is etched and removed in a mesa shape while leaving only the epitaxial layer in a portion to be an operation region of the transistor, and a trapezoidal transistor operation layer is formed on the semi-insulating GaAs substrate 51.

A gate electrode 55 for Schottky contact on the GaAs layer 53 and a source / drain electrode 56 for ohmic contact on the GaAs layer 54 are provided.

The gate electrode 55 extends to a bonding pad electrode 55B disposed on a semi-insulating GaAs substrate 51 in contact with a mesa-like trapezoidal side surface having a thickness of about 0.2 μm. I have. Therefore, the gate electrode 55 has a carrier concentration of about 2 as shown in FIG.
It comes into contact with the n-type GaAs layer 52 formed at about × 10 ¹⁸ cm ^-3 and about 0.02 μm in thickness on the side of the trapezoid. As a result, there is a problem that the gate electrode 55 contacts the n-type GaAs layer 52, the gate leakage current increases, the voltage that can be applied to the transistor is limited, and the output cannot be increased.

[0006]

Therefore, as shown in FIG. 8, it is conceivable to make the operation region of the transistor into an inverted mesa trapezoidal shape. By making the shape of the inverted mesa, the contact between the gate electrode 55 and the n-type GaAs layer 52 can be prevented, and the gate leak current generated on the side surface of the trapezoid can be prevented.

However, the gate electrode 55 has a thickness of about 0.5 μm and a length, that is, a length in a direction perpendicular to the direction in which the gate electrode 55 intersects the trapezoidal portion and in a vertical direction is as small as 0.5 μm. There has been a problem such as disconnection of the gate electrode 55 at the top and bottom of the side surface.

The present invention has been made in view of the above-mentioned conventional problems, and has as its object to provide a compound semiconductor device which suppresses a gate leak current between a gate electrode and a transistor operation region and has high reliability. Aim.

[0009]

According to the present invention, a trapezoidal transistor operation layer is formed on a compound semiconductor substrate, an insulating film is provided on and around the operation layer, and a source electrode, a drain electrode and a gate are provided. An electrode penetrates a part of the insulating film on the surface of the operation layer and comes into contact with the operation layer.

The insulating layer is composed of two layers of insulating films, and the first insulating film is provided around the electrode at the upper part of the trapezoid, and the lower surface thereof is in contact with the substrate around the trapezoid, and is the same as the upper part of the trapezoid. The second insulating film may be provided to a height less than that, and the second insulating film may be provided so as to cover the first insulating film except for the upper part of the trapezoid.

According to the above-described structure, the source electrode, the drain electrode, and the gate electrode are in contact only with the upper portion of the trapezoid, and are not in contact with the compound semiconductor substrate on the side and the bottom of the trapezoid. In addition, disconnection of the electrode can be prevented.

Further, according to the manufacturing method of the present invention, an operation layer of a trapezoidal transistor is formed on a compound semiconductor substrate, an insulating film is provided on and above the operation layer, and a source electrode, a drain electrode and a gate electrode are provided. Is a method of manufacturing a compound semiconductor device that penetrates a part of an insulating film on the surface of the operating layer and is in contact with the operating layer, wherein the insulating layer is composed of two insulating films, and the thickness of the first insulating film is reduced. D1, when the thickness of the second insulating film is D2 and the height of the trapezoid is d, a first insulating film is deposited so that D1 ≦ d, and then a second insulating film is ≧ d−D1, and the CMP is performed until only the first insulating film formed on the trapezoid is exposed.
The method is characterized in that the second insulating film is removed by a method.

When the etching rate of the first insulating film is a and the etching rate of the second insulating film is b, a
> B.

The combination of the first and second insulating films is made of SiN and SiO ₂ , SiN and AlN, SiN and A
l ₂ O _3, SiO ₂ and AlN, may be selected from among SiO ₂ and Al ₂ O _3.

With the above-described structure, the first insulating film is disposed only around the trapezoid to a height equal to or less than the upper portion of the trapezoid, and the second insulating film is formed in the third region excluding the electrode forming region. One insulating film and the trapezoid can be arranged to cover the upper part. As a result, each of the source electrode, the drain electrode, and the gate electrode contacts only the upper portion of the trapezoid and does not contact the compound semiconductor substrate on the side and bottom of the trapezoid, so that gate leakage current can be reduced and disconnection of the electrode can be prevented.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing a field-effect semiconductor device according to one embodiment of the present invention, and FIG.
Is a sectional view taken along line AA of FIG. 1, and FIG. 3 is a sectional view taken along line BB of FIG.

As shown in FIGS. 1 to 3, semi-insulating G
An n-type GaAs having a doping concentration of 1 × 10 ¹⁸ cm ⁻³ and a thickness of 0.03 μm is formed on the aAs substrate 1 by MOCVD or the like.
An s layer 2, an undoped AlGaAs layer 3 having a thickness of 0.02 μm, and an undoped GaAs layer 4 having a thickness of 0.010 μm are sequentially formed by epitaxial growth. A trapezoidal operation layer is formed on the semi-insulating GaAs substrate 1 by mesa etching. In this embodiment, a depth (= d) of 0.
The active layer is formed in a trapezoidal shape having an inverted mesa shape, which is engraved to 2 μm.

Then, an SiN film 5 serving as a first insulating film having a thickness (= D1) of 0.1 μm and a thickness (= D2) of 0.3
The SiO ₂ film 6 serving as a _second insulating film having a thickness of μm is formed by plasma CV.
It is sequentially formed on the entire surface of the substrate by the D method or the like. The total thickness (D1 + D2) of the two insulating films formed is set to be larger than the height (d) between the upper surface of the semi-insulating GaAs substrate 1 and the upper portion of the trapezoid. Further, the types of the first and second insulating films are selected so that the etching rate of the first insulating film is higher than the second etching rate.

These insulating films are formed by chemical mechanical polishing: CMP
(Chemical Mechanical Polishing) method, the substrate surface is polished until the SiN film 5 on the trapezoid is exposed,
It has been flattened. As a result, the lower surface of the SiN film 5 is in contact with the semi-insulating GaAs substrate 1 around the upper and lower portions of the trapezoid, and is provided up to the same height as the upper portion of the trapezoid. The SiO ₂ film 6 is made of Si except for the upper part of the trapezoid.
It is provided so as to cover the N film 5.

Then, using the photoresist pattern having openings only in the source electrode and drain electrode formation portions as masks, unnecessary portions of the SiN film 5 are removed by dry etching, and the undoped GaAs layer 4 is exposed. Au + Ge (750 °) / Ni (70 °) / Au (1
A metal film having a multilayer structure is formed in this order by a vacuum evaporation method, and the source / drain electrodes 7s and 7d are formed by lift-off. This source / drain electrode 7
s.7d is alloyed by heat treatment, has ohmic contact with the GaAs layer 4, and diffuses Ge of the metal layer into the substrate to form an n ⁺ region in the GaAs layer 4.

The SiN film 5 in the gate electrode forming portion is removed by using the photoresist pattern having an opening only in the gate electrode forming portion as a mask, exposing the surface of the undoped GaAs layer 4 and forming the gate electrode metal 8 on the entire surface of the substrate. T
i / Pt / Au (1000/2000/3000)
Å) is formed by a vacuum vapor deposition method, a metal layer that makes Schottky contact with the GaAs layer 4 is formed, and a gate electrode 8 is formed by a lift-off method.

According to the present invention, since the trapezoidal side surface is covered with the insulating layer, the gate electrode 8 does not come into contact with the n-type GaAs layer 3. As a result, the gate leakage current is suppressed and the gate withstand voltage is increased. As a result, a larger voltage can be applied to the gate, which contributes to higher output of transistor characteristics. In addition, disconnection of each electrode at the trapezoidal side can be prevented.

Next, a method for manufacturing a compound semiconductor device according to the present invention will be described. FIG. 4 is a cross-sectional view showing a method for manufacturing a field-effect compound semiconductor device according to an embodiment of the present invention in each step, and is a cross-sectional view corresponding to a cross-sectional view taken along line AA of FIG. .

As shown in FIG. 4A, semi-insulating GaAs
MOCVD of an n-type GaAs layer 2 with a doping concentration of 1 × 10 ¹⁸ cm ⁻³ and a thickness of 0.03 μm, an undoped AlGaAs layer 3 with a thickness of 0.02 μm, and an undoped GaAs layer 4 with a thickness of 0.010 μm on the s substrate 1 It is formed by sequentially epitaxially growing using a method. Thereafter, a mixed aqueous solution of phosphoric acid and hydrogen peroxide is used to a depth that the semi-insulating GaAs substrate 1 is engraved using the photoresist as a mask in the other region, leaving only the epitaxial layer in the active layer region for forming the transistor. Reverse mesa etching.
In this embodiment, it is engraved to a depth (= d) of 0.2 μm.

Next, as shown in FIG. 4B, the film thickness (=
D1) SiN film 5 serving as a first insulating film having a thickness of 0.1 μm and SiO _{2 serving as a second} insulating film having a thickness (= D2) of 0.3 μm
The film 6 is sequentially formed on the entire surface of the substrate by using a plasma CVD method. The total thickness (D1 + D2) of the two insulating films to be formed is set to be larger than the height (d) between the top of the carved semi-insulating GaAs substrate 1 and the top of the inverted mesa trapezoid. Further, the types of the first and second insulating films are selected so that the etching rate of the first insulating film is higher than the second etching rate.

Subsequently, as shown in FIG.
The substrate surface is polished by using the method until the SiN film 5 on the trapezoid is exposed. As an abrasive, a SiN film and SiO ₂
Cerium oxide (CeO ₂ ) having a high film polishing rate is used. Since the film thickness of each part is set so as to satisfy d <(D1 + D2), the SiN film 5 formed on the trapezoidal upper part and the SiN film
The O ₂ film 6 is planarized after the CMP process.

Thereafter, as shown in FIG. 4D, a photoresist pattern 9 having an opening only in the source electrode and drain electrode formation portions is formed. Unnecessary SiN film 5 is removed by dry etching using resist pattern 9 as a mask. This dry etching is performed by plasma etching using a mixed gas of CF ₄ and oxygen. C
In plasma etching in F ₄ and oxygen, the difference between the etching rates of the SiN film and the SiO ₂ film is about 100 times.
Since only the iN film is selectively etched, only the SiN film covering the upper portion of the trapezoid is removed. The etching is stopped when the undoped GaAs layer 4 on the trapezoid is exposed.
After cleaning the surface of the undoped GaAs layer 4 with an aqueous solution, Au + Ge (750 °) / Ni (70 °) / A
u (1300 °) is formed in this order by a vacuum evaporation method to form a metal film 7 having a multilayer structure. At the location where the SIN film 5 has been removed, the metal film 7 is formed in contact with the surface of the GaAs layer 4. Then, unnecessary metal film 7 and photoresist pattern 9 are removed with an organic solvent, and source / drain electrodes 7s and 7d are formed by lift-off.
Thereafter, the alloy is formed by heat treatment at 380 ° C., and an ohmic contact is made to the substrate. By this heat treatment, Ge of the metal film 7 diffuses into the substrate, and an n ⁺ region is formed.

Thereafter, as shown in FIG. 4F, a photoresist pattern 10 having an opening only in the gate electrode forming portion is formed, and CF ₄ is formed using this resist pattern as a mask.
The SiN film 5 in the gate electrode formation portion is removed by performing plasma etching using a mixed gas of oxygen and oxygen. As described above, in plasma etching in CF ₄ and oxygen,
The etching rate difference between the SiN film and the SiO ₂ film is about 100
Since only the SiN film is selectively etched, only the SiN film 5 covering the upper portion of the trapezoid is removed. The etching is stopped when the undoped GaAs layer 4 on the trapezoid is exposed. Then, after cleaning the surface of the undoped GaAs layer 4 with an aqueous solution, the gate electrode metal 8 is formed on the entire surface of the substrate.
Ti / Pt / Au (1000/2000 // 3)
000 °) is sequentially formed by a vacuum evaporation method, and a metal layer which makes Schottky contact with the GaAs layer 4 is formed.

Subsequently, as shown in FIG. 4 (g), the photoresist pattern 10 is removed with an organic solvent, and a gate electrode 8 is formed by a lift-off method, whereby a compound semiconductor device according to the present invention is obtained.

According to the method of the present invention, the end of the trapezoidal operation layer can be covered with the insulating layer, and the gate electrode 8
And the n-type GaAs layer 3 can be reliably separated. For this reason,
As a result of suppressing the gate leak current and increasing the gate breakdown voltage, a larger voltage can be applied to the gate, which contributes to an increase in output of transistor characteristics. In addition, disconnection of each electrode at the trapezoidal side can be prevented.

Next, another embodiment of the manufacturing method of the present invention will be described with reference to FIG. Since the steps up to the formation of the source / drain electrodes are formed in the same manner as described above, the description will be made from the step of forming the gate electrodes onward.

As shown in FIG. 5A, a photoresist pattern 10 having an opening only in a gate electrode forming portion is formed. Then, plasma etching using a mixed gas of CF ₄ and oxygen is performed to remove the SiN film 5 in the gate electrode formation portion. As described above, the SiN film 5 covering the upper part of the trapezoid
Only the undoped GaAs layer 4 on top of the trapezoid.
Etching is stopped when is exposed.

Subsequently, as shown in FIG. 5B, the resist pattern 10 is removed by using an organic solvent, and the surface of the undoped GaAs layer 4 is washed with an aqueous solution. Ti / Pt / Au (1000
{/ 2000} / 3000}) are sequentially formed by a vacuum evaporation method. A metal layer that makes Schottky contact with the GaAs layer 4 is formed.

Subsequently, as shown in FIG.
The substrate surface is polished with a trapezoidal upper metal layer 8 by using the
Polishing is performed until the SiO ₂ film other than the trapezoid is exposed. This C
After the MP process, a flattened gate electrode 8 is obtained.

In each of the above-described embodiments, the operation layer is formed in an inverted mesa shape on the semi-insulating GaAs substrate 1. However, the present invention is similarly applied to an operation layer having a mesa-shaped trapezoidal shape. Can be applied.

Further, in the above embodiment, the first insulating film is made to have an etching rate higher than the second etching rate, the SiN film is used as the second insulating film, and the SiO ₂ Although a film is used, the present invention is not limited to this, and any combination may be used as long as the etching rate of the first insulating film is higher than the second etching rate. For example, SiN and SiO ₂ , SiN and AlN, S
iN and Al ₂ O ₃ , SiO ₂ and AlN, SiO ₂ and Al ₂ O ₃
Can be used.

Further, in the above embodiment,
Although the case where the present invention is applied to the MESFET has been described, the present invention can be applied to another compound semiconductor device in which an operation layer is provided with a step on a substrate.

[0038]

As described above, according to the present invention, since the trapezoidal side surface is covered with the insulating layer, the gate leakage current is suppressed and the gate withstand voltage increases. As a result, a larger voltage is applied to the gate. Since it can be applied, it contributes to high output of transistor characteristics. In addition, disconnection of each electrode at the trapezoidal side can be prevented.

[Brief description of the drawings]

FIG. 1 is a plan view showing a field-effect semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is a sectional view taken along line BB of FIG. 1;

FIG. 4 is a cross-sectional view showing a method of manufacturing the field-effect compound semiconductor device according to one embodiment of the present invention for each step, and is a cross-sectional view corresponding to a cross-sectional view taken along line AA of FIG. is there.

FIG. 5 is a cross-sectional view showing a method of manufacturing a field-effect compound semiconductor device according to another embodiment of the present invention for each step.

FIG. 6 is a plan view showing a conventional MESFET.

FIG. 7 is a sectional view taken along line AA of FIG. 6;

FIG. 8 is a sectional view showing a conventional MESFET.

[Explanation of symbols]

Reference Signs List 1 semi-insulating GaAs substrate 1 2 n-type GaAs layer 3 undoped AlGaAs layer 4 undoped GaAs layer 5 SiN film (first insulating film) 6 SiO ₂ film (second insulating film) 7s source electrode 7d drain electrode 8 gate electrode

Claims (5)

[Claims] An operating layer of a trapezoidal transistor is formed on a compound semiconductor substrate, an insulating film is provided on and above the operating layer, and a source electrode, a drain electrode and a gate electrode are insulated on the surface of the operating layer. A compound semiconductor device which penetrates a part of a film and is in contact with an operation layer. 2. The insulating layer is composed of two insulating films,
The first insulating film is provided around the electrode in the upper portion of the trapezoid, the lower surface thereof is in contact with the substrate around the trapezoid, and is provided up to the same height as or less than the upper portion of the trapezoid, and the second insulating film is The compound semiconductor device according to claim 1, wherein the compound semiconductor device is provided so as to cover the first insulating film except for an upper portion of the trapezoid. 3. An operating layer of a trapezoidal transistor is formed on a compound semiconductor substrate, an insulating film is provided on and above the operating layer, and a source electrode, a drain electrode and a gate electrode are insulated on the surface of the operating layer. A method for manufacturing a compound semiconductor device in which a part of a film penetrates and contacts an operation layer, wherein the insulating layer is composed of two insulating films, the first insulating film has a thickness of D1, and the second insulating film has a thickness of D1. Is D2 and the height of the trapezoid is d.
Then, after depositing the first insulating film so that D1 ≦ d, a second insulating film is deposited thereon so as to satisfy D2 ≧ d−D1, and the first insulating film formed on the trapezoid upper portion is formed. And removing the second insulating film by a CMP method until only the insulating film is exposed. 4. When the etching rate of the first insulating film is a and the etching rate of the second insulating film is b, a
The method according to claim 3, wherein> b. 5. The combination of the first and second insulating films includes SiN and SiO ₂ , SiN and AlN, SiN and Al ₂
O _3, SiO ₂ and AlN, a manufacturing method of a compound semiconductor device according to claim 4, characterized in that it is chosen from among SiO ₂ and Al ₂ O _3.