JPH02188930A - Field-effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent an active layer from coming into direct contact with a gate electrode and to prevent a gate leakage current from flowing while an FET is being operated by a method wherein an insulating film is laid between the active layer exposed at a side wall of a mesa structure part and the gate electrode. CONSTITUTION:An active layer 2 and a semiconductor layer 3 on it are provided in a mesa structure part which has been formed for element isolation use on a substrate 1; the semiconductor layer 3 forms a recess structure 11 after it has been made thin down to a prescribed thickness between a source electrode and a drain electrode 5, 6 which have been formed on said semiconductor layer 3; and a field-effect transistor is formed after a gate electrode 7 has traversed a part between the source electrode and the drain electrode 5, 6 and has come into Schottky contact with said semiconductor layer 3 in the recess structure 11. In this transistor, insulating films 21, 22 are laid between the active layer 2 exposed at side walls of said mesa structure part and the gate electrode 7. For example, inuslating films 21, 22 composed of SiNx, SiO2 or the like are laid between a gate electrode 7 and inverted-mesa-shaped side-wall parts of a mesa structure part.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect transistor and a method for manufacturing the same, and is particularly used for device isolation using a mesa structure.

[Conventional technology]

In a field effect transistor (FET) formed by stacking epitaxial growth layers, device isolation is achieved by forming the device portion into a mesa structure. Figure 2 shows the structure of a conventional element, with (a) being a plan view, and (b) and (C) being the A-A line and the A2 line, respectively.
1 in the cross-sectional view taken along line A2. As shown in the figure, on a substrate 1 made of semi-insulating GaAs, there is an active layer 2 made of n+ type GaAs, and an active layer 2 made of n-type GaAs.
Schottky contact layer 3 consisting of s and n+ type G
An ohmic contact layer 4 made of aAs is sequentially laminated by epitaxial growth, and this is mesa-etched to form a mesa structure 10. A source electrode 5 and a drain electrode 6 are respectively formed on the mesa structure 10, and the mesa structure 10 between these is etched to form a recess structure 11. Then, the Schottky contact layer 3 of the recessed structure portion 11
A gate electrode 7 is provided in Schottky contact.

[Problem to be solved by the invention]

However, in the conventional device shown in FIG. 2, the n+ type operating layer 2 is exposed at the inverted mesa-shaped side wall of the mesa structure 10, and the gate electrode 7 is provided on this. As shown in C), the active layer 2 and the gate electrode 7 come into contact with each other. Therefore, a gate leakage current flows during operation of the FET, resulting in a decrease in gate breakdown voltage and Schottky characteristics, thereby deteriorating the characteristics of the FET. In addition, the gate leakage current as described above is caused not only by step-doped FETs but also by high electron mobility transistors (H1gh1?Icct
ron Nobility Translator;
The same occurs in HE M T ). this is,
Two-dimensional electron gas layer (operating layer) on the side wall of mesa structure 10
This is because the gate electrode is in contact with the gate electrode.

The present invention aims to solve such problems.

[Means to solve the problem]

A field effect transistor according to the present invention has an active layer and a semiconductor layer thereon (for example, a Schottky contact layer and an ohmic contact layer) in a mesa structure formed on a substrate for element isolation, and this semiconductor layer is thinned to a predetermined thickness between the source and drain electrodes formed on the semiconductor layer to form a recessed structure, and the gate electrode is formed on the Schottky contact layer in the recessed structure across between the source and drain electrodes. The field-effect transistor is characterized in that an insulating film is interposed between the gate electrode and the active layer exposed at the inverted mesa-shaped sidewall of the mesa structure.

Further, the method for manufacturing a field effect transistor according to the present invention includes a mesa structure including an active layer and a semiconductor layer thereon (for example, a Schottky contact layer and an ohmic contact layer), and in which the active layer is exposed on the sidewall, on a substrate. A second step of forming an insulating film on the inverted mesa-shaped sidewalls of the mesa structure, and etching the semiconductor layer of the mesa structure between the source and drain electrode formation regions. A third step of reducing the thickness to a predetermined thickness to form a recessed structure, and a fourth step of forming a gate electrode across the source and drain electrode forming regions on the Schottky contact layer in the recessed structure. Features.

[Effect]

According to the present invention, an insulating film is formed on the inverted mesa-shaped side wall portion of the mesa structure portion, and a gate electrode is provided on the insulating film, so that the active layer and the gate electrode do not come into direct contact with each other.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a cross-sectional view of the step-doped FET according to the embodiment according to the manufacturing process. In FIG. The figure corresponds to the cross section taken along line A 2 """ A 2 in FIG.

The field effect transistor according to the present invention is formed in a mesa structure 10 on a substrate 1, as shown in FIG. 1(f). That is, the source electrode 5 and the drain electrode 6 are formed on the forward mesa-shaped side wall part 31 of the mesa structure part 10 and are in contact with the ohmic contact layer 4, and the entire ohmic contact layer 4 between these electrodes 5 and 6 and the Schottky A portion of the contact layer 3 is removed to form a recessed structure 11. A gate electrode 7 is formed across the source electrode 5 and the drain electrode 6 in this recessed structure 11, but between this gate electrode 7 and the inverted mesa-shaped sidewall 32 of the mesa structure 10. , SiN or S
Insulating films 21, 22 such as tO2 are interposed. According to this structure, the active layer 2 and the gate electrode 7 do not come into contact with each other, so that no gate leakage current flows during the operation of the FET.

Here, if the insulating film is provided on this inverted mesa-shaped side wall portion 32, it is sufficient to prevent gate leakage current, and the substrate 1 and the gate electrode 7 may be in contact with each other at other portions. However, if the insulating film is formed by the first insulating film 21 on the lower side and the second insulating film 22 on the upper side as shown in FIG. 1
Cracks in the insulating film 21 can be prevented. This is because the first insulating film 21 is made of thickly deposited SiN as will be described later.
This is because if the protective second insulating film 22 is not provided on the first insulating film 21, thermal cracking or chipping is likely to occur.

The above FET is manufactured, for example, as shown in FIG.

First, a substrate 1 made of, for example, semi-insulating GaAs is prepared, and an active layer 2 is formed on the substrate 1 by epitaxial growth.
The Schottky contact layer 3 and the ohmic contact layer 4 are dried. Here, the active layer 2 has an impurity concentration of 3
x 10” am-3 or so with a thickness of about 150A
The Schottky conductive layer 3 is made of GaAs type, and has an impurity concentration of about 1×1017, -3 and a thickness of 400 nm.
The ohmic contact layer 4 is made of n+ type GaAs with an impurity concentration of about 5×10 18 CI 11 −3 and a thickness of about 1000 Å. Next, a mask (not shown) is formed with a photoresist film or the like, and mesa etching of about 3000A is performed, as shown in FIG. 1(a).
A mesa structure 10 is formed.

As shown in the figure, the mesa structure 10 has forward mesa-shaped sidewalls 31 on one both sides and inverted mesa-shaped sidewalls 32 on the other both sides, depending on the crystal orientation of the substrate 1.

Next, a SiN film as a first insulating film 21 is formed on the substrate 1 which has been isolated by the mesa structure as described above.
Deposit. This first insulating film 21 may be made of S102 or the like, but its thickness is made to be approximately the same as the height of the mesa structure 10 (as shown in FIG. 1(b)). In addition, as a deposition method, plasma CVD (Chea+Ical Vapo
Although a method such as a sputtering method or a sputtering method may be used, it is desirable to use a method that allows a relatively strong film quality to be obtained even on the inverted mesa-shaped side wall portion 32.

Next, RI E (Reactive Jon Etc.
When the first insulating film 21 is removed (etched back) by the etch-back method, the forward mesa-shaped sidewalls 31 of the mesa structure 10 are exposed, and the first insulating film 21 remains on the reverse mesa-shaped sidewalls 32. (as shown in FIG. 1(C)). Thereafter, a second insulating film 22 is deposited to a thickness of about 1500 Å for surface protection, resulting in the structure shown in FIG. 1(d).

Next, another mask consisting of photoresist (not shown)
Using the RIE method, the second insulating film 22 is removed from the forward mesa-shaped sidewall portion 31 of the recessed structure portion 10, and the mesa structure portion 10 is exposed in the formation region of the source electrode 5 and drain electrode 6. Then, by forming the source electrode 5 and drain electrode 6 by the lift-off method, the structure shown in FIG. 1(e) is obtained.

Next, using yet another mask (not shown) made of photoresist, the second insulating film 22 on the mesa structure 10 between the source electrode 5 and the drain electrode 6 is removed by R1/E method or the like. Then, ohmic contact layer 4 and Schottky contact layer 3 are etched. Here, the Schottky contact layer 3 is etched so that it remains at a constant thickness, thereby forming a recess structure 11 in the mesa structure 10. Thereafter, when the gate electrode 7 is formed using the lift-off method, the structure shown in FIG. 1(f) will be obtained.

〔Effect of the invention〕

As described above in detail, according to the present invention, an insulating film is formed on the inverted mesa-shaped side wall of the mesa structure, and a gate electrode is provided on this, so that the active layer and the gate electrode are directly connected to each other. Never come into contact with.

Therefore, a field effect transistor with excellent Schottky characteristics such as gate breakdown voltage, n value, and ΦB can be obtained. Such field effect transistors have excellent noise characteristics, especially at high frequencies.

DESCRIPTION OF SYMBOLS 1... Substrate, 2... Operating layer, 3... Schottky contact layer, 4... Ohmic contact layer, 5...
... Source electrode, 6... Drain electrode, 7... Gate electrode, 10... Mesa structure, 11... Recess structure, 21... First insulating film, 22... Second Insulating film.

Patent applicant: Sumitomo Electric Industries, Ltd. Representative Patent Attorney Yoshi Itsuki Hase

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a device according to steps for manufacturing a field effect transistor according to the present invention, and FIG. 2 is a diagram showing the structure of a conventional device.

Claims (1)

[Claims] 1. A mesa structure formed on a substrate for device isolation has an active layer and a semiconductor layer thereon, and this semiconductor layer has source and drain electrodes formed on the semiconductor layer. In the field effect transistor, the field effect transistor is formed by being thinned to a predetermined thickness between the source and drain electrodes to form a recess structure, and a gate electrode is formed in Schottky contact with the semiconductor layer in the recess structure by crossing between the source and drain electrodes. A field effect transistor characterized in that an insulating film is interposed between the active layer exposed at the side wall of the mesa structure and the gate electrode. 2. The field effect transistor according to claim 1, wherein the active layer is a highly impurity concentration layer. 3. The field effect transistor according to claim 1, wherein the active layer is a layer containing a two-dimensional electron gas. 4. A first step of forming on a substrate a mesa structure including an active layer and a semiconductor layer thereon, with the active layer exposed on the sidewalls; and forming an insulating film on the reverse mesa-shaped sidewalls of the mesa structure. a second step of forming a recessed structure by etching the semiconductor layer of the mesa structure between the source and drain electrode forming regions to a predetermined thickness; a third step of forming a recessed structure of the semiconductor layer of the mesa structure; A method for manufacturing a field effect transistor, comprising: a fourth step of forming a gate electrode in Schottky contact with the semiconductor layer in the recessed structure so as to cross between drain electrode formation regions.