JPH05182991A - Heterojunction fet and its manufacture - Google Patents

Abstract

PURPOSE:To provide a heterojunction FET wherein the generation of a gate leakage current can be suppressed at the sidewall part of an active layer and a good high-frequency characteristic is displayed and to provide a manufacturing method for obtaining it. CONSTITUTION:A gate electrode 9b is formed on a semiconductor layer provided with a heterojunction; then, the semiconductor layer is etched; a mesa-shaped active layer 20b is formed; after that, an insulating film 18 is formed on the surface of the active layer 20b so as to bury the circumference of the gate electrode 9b; a gate extraction electrode 17 one part of which is joined to the surface of the gate electrode 9b which is exposed from the insulating film 18 is formed on the surface of the insulating film 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heterojunction FET and a method for manufacturing the same, and more particularly to a heterojunction FET with suppressed gate leakage and a method for manufacturing the same.

[0002]

2. Description of the Related Art FIG. 9 is a diagram showing the structure of a conventional InP-based selectively doped heterojunction FET (hereinafter referred to as HEMT). FIG. 9 (a) is a plan view seen from above, and FIG. 9] is a cross-sectional view taken along line IXb-IXb in FIG.
In these figures, 20 is an active layer, 21 is a gate electrode formed of Au-based or Al-based material, 22 and 23 are source and drain electrodes respectively formed of AuGe-based alloy, and 24 is a side wall of the active layer. Mesa step, 25 is InP
Substrate, 26 is i-InAlAs buffer layer, 27 is i-
The InGaAs channel layer, 28 is an n-InAlAs electron supply layer, 29 is an i-InAlAs Schottky formation layer, and the active layer 20 is the i-InAlAs buffer layer 2.
6, i-InGaAs channel layer 27, i-InAlA
The s schottky formation layer and the i-InAlAs schottky formation layer 29 are composed of a semiconductor layer having a multilayer structure.

Next, the operation of the HEMT will be described. When a bias is applied between the source electrode 22 and the drain electrode 23, which are two ohmic electrodes, i-InG
The two-dimensional electron gas formed in the vicinity of the n-InAlAs electron supply layer 28 in the aAs channel layer 27 becomes a channel, and a current flows. The FET operation is performed by controlling this current with the voltage applied to the gate electrode 21.

Here, the In which the gate electrode 21 is formed
The AlAs Schottky forming layer 29 is usually formed of a low concentration layer having a low impurity concentration as described above or an undoped layer, and by using these, the leak current of the gate electrode 21 is suppressed.

[0005]

DISCLOSURE OF THE INVENTION Conventional heterojunction FE
T is configured as described above, and the InAlAs Schottky forming layer 2 having the gate electrode 21 formed on the upper surface thereof is formed.
9 is formed by a low-concentration layer having a low impurity concentration or an undoped layer to suppress the leak current of the gate electrode 21. However, as shown in FIG. 9 (b), the active layer 20
Since the gate electrode 21 comes into contact with each layer forming the active layer 20 on the side wall portion 24, a gate leak current is generated at this contact portion, and the high frequency characteristics of the device deteriorate. In particular, there was a problem of doing. In particular, the gate electrode 21 cannot form a good Schottky junction with the n-InAlAs electron supply layer 28 and the i-InGaAs channel layer 27, and if they come into contact with them, the gate leakage current increases and the high frequency characteristics are deteriorated. The deterioration was more pronounced.

The present invention has been made to solve the above problems, and a high-performance heterojunction FET which can suppress the generation of a gate leak current in the side wall portion of an active layer and exhibits excellent high frequency characteristics. It is an object to provide a method for producing this.

[0007]

In a heterojunction FET according to the present invention, a semiconductor layer which is hard to form a Schottky junction with a gate electrode exposed on the side wall of an active layer is side-etched, and the semiconductor layer and the gate electrode are separated from each other. It was designed so that it would not come into contact with them.

Further, the heterojunction FET according to the present invention
Is an insulating film inserted between the side wall of the active layer and the gate electrode.

Further, the heterojunction FET according to the present invention
Forming a gate electrode only on the upper surface of the active layer, and disposing a gate extraction electrode, a part of which is joined to the surface of the gate electrode, on an insulating film formed so as to fill the periphery of the gate electrode. It is a thing.

Further, the heterojunction FET according to the present invention
In the method for manufacturing the same described above, a mesa-shaped active layer is formed on a semiconductor substrate, and then a semiconductor layer that is hard to form a Schottky junction with the gate electrode exposed on the side wall of the active layer is side-etched. It extends from the upper surface of the active layer toward the upper surface of the semiconductor substrate along the side wall of the active layer.

Further, the heterojunction FET according to the present invention
In the manufacturing method of (1), a mesa-shaped active layer is formed on a semiconductor substrate, and then an insulating film is formed on a side wall of the active layer. Thereafter, a gate electrode is formed from the upper surface of the active layer to the upper surface of the semiconductor substrate. To extend along the insulating film.

Further, the heterojunction FET according to the present invention
In the manufacturing method of (1), a gate electrode is formed on the upper surface of the semiconductor layer having a multi-layer structure, then the semiconductor layer is etched to form a mesa-shaped active layer, and then the periphery of the gate electrode is embedded. An insulating film is formed on the entire surface of the active layer, and a gate extraction electrode, a part of which is joined to the surface of the gate electrode, is formed on the insulating film.

[0013]

According to the present invention, the side wall of the active layer is side-etched with the semiconductor layer that is less likely to make a Schottky junction with the gate electrode, so that the semiconductor layer does not come into contact with the gate electrode and the generation of the gate leakage current is suppressed. can do.

Further, in the present invention, since the insulating film is inserted between the side wall of the active layer and the gate electrode,
The gate electrode does not come into contact with the side wall of the active layer, so that the generation of gate leakage current can be suppressed.

Further, according to the present invention, the gate electrode is formed only on the upper surface of the active layer, and the gate lead-out electrode, a part of which is joined to the surface of the gate electrode, is formed on the insulating film filling the periphery of the gate electrode. Since the gate electrode is formed, the gate electrode does not come into contact with the side wall of the active layer, and the generation of the gate leak current can be suppressed.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a heterojunction F according to an embodiment of the present invention.
FIG. 1A is a view showing a cross section of the structure of ET, and FIG. 1A is a cross section in which the device is divided in a direction along the source electrode and the drain electrode,
FIG. 1B is a sectional view taken along line Ib-Ib in FIG. In these figures, 1 is a semi-insulating InP substrate,
2 is an AlInAs buffer layer, 3 is an InGaAs channel layer, 4 is an AlInAs spacer layer, and 5 is n-AlIn.
As electron supply layer, 6 AlInAs Schottky formation layer, 7 n-InGaAs contact layer, 8a Au G
A source electrode made of an e-based alloy, 8b a drain electrode made of an Au Ge-based alloy, 9 a gate electrode made of a refractory metal such as Au-based, Al-based, or WSi, 9a a gate electrode lead portion, 11 an ion-implanted portion. High resistance active layer region, 12 is I formed by side etching
The depression of the nGaAs channel layer 3, 20a is an active layer, 24
Is the sidewall of the active layer. Here, the InGaAs channel layer 3 on the side wall portion 24 of the active layer 20a is side-etched to form the depression 12, and the side wall portion 24 of the active layer 20a does not come into contact with the gate electrode 9.

FIG. 2 is a heterojunction FE shown in FIG.
It is sectional drawing according to process which shows the manufacturing process of T. In the figure,
7a is a depression of the n-InGaAs contact layer 7, 14,
Reference numeral 15 is a resist pattern.

The manufacturing process of the heterojunction FET shown in FIG. 1 will be described below with reference to FIG. First, semi-insulating InP
On the substrate 1, AlInAs buffer layer 2, InGaAs channel layer 3, AlInAs spacer layer 4, n-AlIn
The As electron supply layer 5, the AlInAs Schottky formation layer 6, and the n-InGaAs contact layer 7 are sequentially crystal-grown. Next, a resist is applied on the entire surface, and a resist pattern 14 is formed by a usual photoengraving and etching technique. Next, using the resist pattern 14 as a mask, as shown in FIG. 2A, the AlInAs obtained above is obtained.
Buffer layer 2, InGaAs channel layer 3, AlInA
s spacer layer 4, n-AlInAs electron supply layer 5, Al
Boron ions are ion-implanted into the end portions of the InAs Schottky formation layer 6 and the n-InGaAs contact layer 7 to increase the resistance of this portion. Next, the resist pattern 1
After removing 4, the resist is applied again on the entire surface, and a resist pattern 15 is formed by a usual photolithography and etching technique. Next, as shown in FIG. 2B, each of the semiconductor layers 2, 3, 4, 5, 6 and 7 is etched by wet etching using the resist pattern 15 as a mask and using a tartaric acid-based etching solution. When the mesa-shaped active layer 20a is formed and the active layer 20a is side-etched by plasma etching using a CH ₄ -based gas, the InGaAs channel layer 3 and the n-InG are formed.
The aAs contact layer 7 and the depression 7a and the depression 12 respectively.
Is formed. After that, when the source and drain electrodes 8a and 8b and the gate electrode 9 as the ohmic electrodes are formed by the normal ohmic electrode forming process and the gate recess lift-off process, the gate electrode 9 and the sidewall portion 24 of the active layer 20a shown in FIG. 1 are formed. InGaAs channel layer 3
A heterojunction FET that is not in contact with is completed.

Next, the operation will be described. The operation is basically the same as that of the conventional heterojunction FET shown in FIG. 9, and in the heterojunction FET of this embodiment, when the source and drain electrodes 8a and 8b are biased, InGaA
A two-dimensional electron gas is formed in the vicinity of the AlInAs spacer layer 4 in the s-channel layer 3 and serves as a channel to flow a current. Then, the FET operation is performed by controlling this current by the voltage applied to the gate electrode 9.

FIG. 3 shows that the heterojunction FET of this embodiment and the conventional heterojunction FET, that is, the semiconductor layer (channel layer) which is hard to form a Schottky junction with the gate electrode on the side wall of the active layer is not side-etched. FIG. 3A is a diagram showing static characteristics of a heterojunction FET in which no dent is formed, FIG. 3A shows gate leakage current-gate voltage characteristics, and FIG. 3B shows drain current-gate voltage characteristics. Shows. As is clear from the figure, the heterojunction FET of this embodiment has a InG that is hard to form a Schottky junction with the gate electrode.
It can be seen that since the aAs channel layer 3 has a structure in which it does not contact the gate electrode 9 due to the depression 12, the generation of a gate leak current is suppressed and the FET characteristics are improved.

In the manufacturing process of the heterojunction FET of this embodiment, since the recess 12 is formed by side etching in the InGaAs channel layer 3 which is hard to make a Schottky junction with the gate electrode of the sidewall 24 of the active layer 20a, The gate electrode 9 and the InGaAs channel layer 3 do not come into contact with each other at the side wall portion 24 of the active layer 20a, and as a result, the resulting device suppresses the generation of a gate leak current and obtains excellent high frequency characteristics. Further, in the manufacturing process of the heterojunction FET of the present embodiment, since the side end of the active layer is made to have a high resistance by ion implantation, the generation of gate leakage current is further suppressed, and the FET characteristics can be further improved. ..

FIG. 4 is a sectional view showing the structure of a heterojunction FET according to the second embodiment of the present invention, and FIG. 4 (a) is a sectional view taken along the source and drain electrodes 8a and 8b. 4B is a sectional view taken along line IVb-IVb in FIG. In these figures, the same reference numerals as those in FIG. 1 indicate the same or corresponding portions, and 13 is an insulating film made of SiO2. In the heterojunction FET of this embodiment, the insulating film 13 is provided on the side wall portion 24 of the active layer 20,
The gate electrode 9 is formed on the insulating film 13.

FIG. 5 is a heterojunction FE shown in FIG.
It is sectional drawing according to process which shows the manufacturing process of T. In the figure,
16 is a resist pattern.

The heterojunction FET will be described below with reference to FIG.
The manufacturing process of will be described. First, the semi-insulating InP substrate 1
AlInAs buffer layer 2, InGaAs channel layer 3, AlInAs spacer layer 4, n-AlInAs electron supply layer 5, AlInAs Schottky formation layer 6 and n
-The InGaAs contact layer 7 is successively crystallized.
Next, a resist is applied on the entire surface, and a resist pattern 16 is formed by ordinary photoengraving and etching techniques. Then, by wet etching using a tartaric acid-based etching solution with the resist pattern 16 as a mask,
By etching each semiconductor layer, as shown in FIG. 5 (a),
A mesa-shaped active layer 20a is formed. Then, FIG. 5 (b)
As shown in FIG. 3, SiO2 is vapor-deposited on the entire surface by electron beam vapor deposition while leaving the resist pattern 16 to form the SiO2 film 13 on the side wall portion 24 of the active layer. At this time, the SiO2 film 13 is also formed on the resist pattern 16.
Then, as shown in FIG. 5C, SiO is lifted off.
2 A resist pattern 16 having a film 13 formed on its upper surface
To remove. Then, after that, the source / drain electrodes 8a and 8b and the gate electrode 9 are formed by the normal ohmic electrode formation step and the gate recess lift-off step, whereby the heterojunction FET shown in FIG. 4 is completed.

In the manufacturing process of the heterojunction FET of this embodiment, the insulating film 13 made of a SiO2 film is formed on the side wall portion 24 of the mesa-shaped active layer 20a.
Since the gate electrode 9 is extended on the gate electrode 9, the n-AlInAs electron supply layer 5 and the InGaAs channel layer 3 which are hard to form a Schottky junction with the gate electrode 9 do not come into contact with the gate electrode 9 at the side wall 24 of the active layer 20a. As a result, the obtained device is the heterojunction FE of the above-mentioned embodiment shown in FIG.
Similar to T, generation of a gate leak current is suppressed, and good high frequency characteristics can be obtained.

6A and 6B are views showing the structure of a heterojunction FET according to a third embodiment of the present invention. FIG. 6A is a plan view seen from above, and FIG. 6B is FIG. 6A. VIb-VIb in
It is sectional drawing in a line. In these figures, the same reference numerals as those in FIGS. 1 and 9 indicate the same or corresponding parts.
a is an i-AlInAs buffer layer, 3a is i-InGa
As channel layer, 6a is an i-AlInAs Schottky formation layer, 9b is a gate electrode made of a refractory metal such as Au, Al, WSi, 17 is a gate lead electrode made of Au, Al and 18 is an insulating film. Is. The active layer 20b of the heterojunction FET of this embodiment has basically the same layer structure as the active layer 30 of the conventional heterojunction FET shown in FIG. , The gate electrode is not formed, the gate electrode 9b is formed on the upper surface of the active layer 20b, and the gate lead portion is
On the insulating film 18 provided on the entire surface of the active layer 20b so as to fill the periphery of the gate electrode 9b, the surface of the gate electrode 9b and a part thereof are formed by the gate lead electrode 17.

FIG. 7 is a heterojunction FET shown in FIG.
6A to 6C are cross-sectional views showing the manufacturing process of each of the steps,
11 is a cross-sectional view taken along line II-VII.

The manufacturing process will be described below with reference to this drawing. First, as shown in FIG. 7A, the i-AlInAs buffer layers 2a and i-InGa are formed on the semi-insulating InP substrate 1.
The As channel layer 3a, the n-AlInAs electron supply layer, and the i-AlInAs Schottky formation layer 6a are sequentially crystal-grown. Next, the gate electrode 9b is formed on the i-AlInAs Schottky formation layer 6a by a vapor deposition lift-off method or a sputtering method + reactive ion etching method (RIE method).
To form. Next, the semiconductor layer is etched by wet etching to form a mesa-shaped active layer 20b, and the source and drain electrodes 8 are further formed by vapor deposition lift-off method.
a and 8b are formed, and the active layer 20 as shown in FIG. 7 (b) is formed.
the gate electrode 9b is formed on the upper surface of the gate electrode 9b.
From the upper surface of the active layer 20b in a direction orthogonal to
The source and drain electrodes 8a and 8b are extended toward the side wall 24 and the upper surface of the semi-insulating InP substrate 1. Next, ECR using microwave ECR plasma
By the CVD method, the periphery of the gate electrode 9b and the active layer 2 are
An insulating film 18 made of SiO or the like is formed so as to fill the entire area above 0b. In addition, in order to prevent the insulating film from remaining on the gate electrode 9b in the step of forming the insulating film by the ECRCVD method, the width of the gate electrode 9b is formed to be thin and constant in the above-described step of forming the gate electrode 9b. This is because, when there is a wide portion, the insulating film remains there and the surface of the gate electrode 9b is not exposed from the insulating film 18. Then, when the gate extraction electrode 17 whose part is joined to the gate electrode 9b is formed on the gate electrode 9b whose surface is exposed from the insulating film 18 by the vapor deposition lift-off method, the state shown in FIG. 7C is obtained. A heterojunction EFT having a structure in which the gate metal does not contact the sidewall portion 24 of the active layer 20b shown in FIG. 6B is obtained.

In the process of manufacturing the heterojunction FET of this embodiment, the gate electrode 9b is formed on the upper surface of the mesa-shaped active layer 20b, and the active layer 20b is exposed so that the surface of the gate electrode 9b is exposed. Since the insulating film 18 is formed on the upper surface and the gate extraction electrode 17 partly joined to the surface of the gate electrode 9b is formed on the insulating film,
At the side wall 24 of the active layer 20b, the n-AlInAs electron supply layer 5 and the i-InGaAs channel layer 3a are not in contact with the gate metal at all, and as a result, the device obtained is the same as the first embodiment shown in FIG. Similar to the heterojunction FET, the generation of gate leakage current is suppressed, and a good FET
It is a characteristic. Further, in the heterojunction FET of this embodiment, the gate electrode 9b and the gate extraction electrode 17 are
Since a T-shaped gate electrode can be realized by and, the gate resistance can be reduced and the device characteristics can be further improved. Furthermore, since the material of the gate extraction electrode 17 can be selected separately from the gate electrode 9b, it is possible to further reduce the gate resistance by selecting the material.

FIG. 8 is a sectional view showing the structure of a heterojunction FET according to the fourth embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 6 indicate the same or corresponding portions,
This heterojunction FET has a structure in which a recess is formed in the i-AlInAs Schottky formation layer 6a and a gate electrode 9b is formed in this part. Then, this heterojunction FET is pre-formed i before forming the gate electrode 9b.
The gate lead-out portion, that is, the gate lead-out portion, that is, the gate lead-out portion, is manufactured by the same process as that of the third embodiment except that the recess is formed in the AlInAs Schottky formation layer 6a by using the ordinary photoengraving and etching techniques. Since the electrode 17 is formed on the insulating film 18 that fills the periphery of the gate electrode 9b as in the third embodiment, the gate metal is not brought into contact with the active layer 20b as in the third embodiment. , A T-type gate can be formed, and the obtained device has excellent FET characteristics in which generation of a gate leak current is suppressed.

Although the InGaAs channel layer 3 is either an undoped layer or a low-concentration layer in the above embodiment, even in the case of a heterojunction FET using an n-type doped InGaAs channel layer, the InGaAs channel layer 3 is an active layer. Needless to say, the present invention can be applied to the case where a gate leak occurs at the side wall.

In the above embodiment, the channel layer is made of In
GaAs was used, but InAs, InSb, InAsS
Needless to say, even when b is used, the present invention can be applied when the active layer has a layer structure in which a gate leak occurs due to contact between the side wall of the active layer and the gate metal.

[0033]

As described above, according to the present invention, the semiconductor layer which is hard to form a Schottky junction with the gate electrode exposed on the side wall of the mesa-shaped active layer is side-etched, and then the gate electrode is formed into the active layer. Since the semiconductor layer is formed from the upper surface of the layer to the upper surface of the semiconductor substrate along the side wall of the active layer, the semiconductor layer does not contact the gate electrode on the side wall of the active layer, and as a result, the gate leakage current is generated. High-performance heterojunction FET with improved high-frequency characteristics
There is an effect that can be obtained.

Further, according to the present invention, an insulating film is formed on the side wall of the mesa-shaped active layer, and then the gate electrode is directed from the upper surface of the active layer to the upper surface of the semiconductor substrate. Since the semiconductor layer which is formed along the gate electrode does not easily contact the gate electrode at the side wall of the active layer, the semiconductor layer that is hard to make a Schottky junction with the gate electrode is suppressed. As a result, the generation of the gate leakage current is suppressed, and the high frequency characteristics are improved. There is an effect that a high-performance heterojunction FET can be obtained.

Further, according to the present invention, the gate electrode is formed only on the upper surface of the active layer, and a part of the gate electrode is bonded to the surface of the gate electrode on the insulating film filling the periphery of the gate electrode and the active layer. Since the extraction electrode is formed, the semiconductor layer that is hard to make a Schottky junction with the gate electrode does not come into contact with the gate electrode on the side wall of the active layer, and as a result, the generation of gate leakage current is suppressed, and high frequency characteristics It is possible to obtain a high-performance heterojunction FET with improved characteristics. Moreover, since the T-shaped gate is formed by the gate electrode and the gate extraction electrode, the gate resistance can be reduced, and the device characteristics can be further improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a cross section of a structure of a heterojunction FET according to an embodiment of the present invention, FIG.
A cross section of the device cut along the direction of the drain electrode, FIG.
1B is a sectional view taken along line Ib-Ib in FIG.

2A to 2D are cross-sectional views of respective steps showing a manufacturing process of the heterojunction FET shown in FIG.

3A and 3B are diagrams showing static characteristics of the heterojunction FET shown in FIG. 1 and a conventional heterojunction FET, FIG. 3A showing a gate leakage current vs. gate voltage characteristic, and FIG. It is a figure which shows a drain current-gate voltage characteristic.

FIG. 4 is a heterojunction FE according to a second embodiment of the present invention.
4A is a sectional view showing the structure of T, and FIG. 4A is a sectional view taken along the source and drain electrodes 8a and 8b.
4B is a sectional view taken along line IVb-IVb in FIG.

5A to 5C are cross-sectional views for each process showing a manufacturing process of the heterojunction FET shown in FIG.

FIG. 6 is a heterojunction F according to the third embodiment of the present invention.
It is a figure which shows the structure of ET, FIG.6 (a) is the top view seen from above, FIG.6 (b) is sectional drawing in the VIb-VIb line in FIG.6 (a).

7A to 7C are cross-sectional views showing the manufacturing process of the heterojunction FET shown in FIG. 6, which are taken along the line VII-VI in FIG. 6A.
It is a cross section taken along line I.

FIG. 8 is a sectional view showing the structure of a heterojunction FET according to the fourth embodiment of the present invention.

9 is a diagram showing a structure of a conventional InP-based HEMT, FIG. 9 (a) is a plan view seen from above, and FIG. 9 (b) is IXb-IXb in FIG. 9 (a). It is sectional drawing in a line.

[Explanation of symbols]

1 semi-insulating InP substrate 2 AlInAs buffer layer 2a i-AlInAs buffer layer 3 InGaAs channel layer 3a i-InGaAs channel layer 4 AlInAs spacer layer 5 n-AlInAs electron supply layer 6 AlInAs Schottky formation layer 6a i-AlInAs Schottky formation Layer 7 n-InGaAs contact layer 7a Indentation of contact layer formed by etching 8a Source electrode 8b Drain electrode 9 Gate electrode 9a Gate electrode lead-out part 9b Gate electrode 11 Active layer region made high in resistance by ion implantation 12 Formed by etching Indentation of the formed channel layer 13 Insulating film 14, 15, 16 Resist pattern 17 Gate extraction electrode 18 Insulating film 20, 20a, 20b Active layer 21 Gate electrode 22 Source electrode 3 the drain electrode 24 side wall

Claims (8)

[Claims] 1. An active layer comprising a semiconductor substrate, a semiconductor layer having a multi-layer structure including a channel layer and a semiconductor layer heterojunction to the channel layer, the active layer being arranged in a mesa shape on the semiconductor substrate. A source and drain electrode extending from the upper surface of the semiconductor substrate toward the upper surface of the active layer through a side wall of the active layer, and the semiconductor substrate in a direction orthogonal to the source and drain electrode. What is claimed is: 1. A heterojunction FET comprising: a gate electrode extending from an upper surface to an upper surface of the active layer through a sidewall portion of the active layer, the FET being a Schottky junction with the gate electrode at the sidewall portion of the active layer. A heterojunction FET characterized in that a difficult semiconductor layer is side-etched. 2. The heterojunction FET according to claim 2, wherein the sidewall of the active layer has a high resistance by ion implantation. 3. An active layer comprising a semiconductor substrate, a semiconductor layer having a multi-layered structure including a channel layer and a semiconductor layer heterojunction to the channel layer, the active layer being arranged in a mesa shape on the semiconductor substrate. A source and drain electrode extending from the upper surface of the semiconductor substrate toward the upper surface of the active layer through a side wall of the active layer, and the semiconductor substrate in a direction orthogonal to the source and drain electrode. What is claimed is: 1. A heterojunction FET comprising: a gate electrode extending from a top surface to a top surface of the active layer through a sidewall portion of the active layer, wherein the heterojunction FET is insulated from the sidewall portion of the active layer and the gate electrode. A heterojunction FET having a film inserted therein. 4. A semiconductor substrate, a channel layer and the channel
A multilayer structure including a semiconductor layer heterojunction to the layer
Composed of a semiconductor layer and arranged in a mesa shape on the semiconductor substrate
And the active layer formed from the top surface of the semiconductor substrate.
Extended through the sidewall of the active layer towards the top of the layer
The source and drain electrodes and the source and drain electrodes
Between the poles, in the direction perpendicular to these, on the top surface of the active layer
A heterojunction FET having a formed gate electrode
By embedding the periphery of the gate electrode, the surface of the gate electrode
Are disposed on the active layer so that they are exposed from the top surface.
Part of the insulating film and the surface of the gate electrode
Gate pull extended from the electrode surface to the above-mentioned insulating film
Heterojunction FE characterized in that it is provided with a bare electrode
T. 5. A semiconductor layer having a multi-layer structure including a channel layer and a semiconductor layer heterojunction to the channel layer is formed on a semiconductor substrate, and the semiconductor layer is etched to form a mesa-shaped structure on the semiconductor substrate. Between the step of forming the active layer, the step of forming the source and drain electrodes from the upper surface of the active layer toward the upper surface of the semiconductor substrate along the side wall of the active layer, and between the source and drain electrodes. A step of forming a gate electrode along the side wall of the active layer from the upper surface of the active layer to the upper surface of the semiconductor substrate in a direction orthogonal to these, the gate electrode Prior to the step of forming the semiconductor layer, a semiconductor layer which is hard to form a Schottky junction with the gate electrode exposed on the side wall of the active layer is side-etched. Method for producing a B junction FET. 6. The method for manufacturing a heterojunction FET according to claim 5, wherein prior to the side etching step, ion implantation is performed on the side wall of the active layer to increase the resistance of the side wall. And a method for manufacturing a heterojunction FET. 7. A mesa-shaped semiconductor layer is formed on the semiconductor substrate by forming a semiconductor layer having a multi-layer structure including a channel layer and a semiconductor layer heterojunction to the channel layer on the semiconductor substrate and etching the semiconductor layer. Between the step of forming the active layer, the step of forming the source and drain electrodes from the upper surface of the active layer toward the upper surface of the semiconductor substrate along the side wall of the active layer, and between the source and drain electrodes. A step of forming a gate electrode along the side wall of the active layer from the upper surface of the active layer to the upper surface of the semiconductor substrate in a direction orthogonal to these, the gate electrode Prior to the step of forming the above-mentioned step, an insulating film is formed on the surface of the side wall of the active layer. 8. A mesa-shaped semiconductor layer is formed on a semiconductor substrate by forming a semiconductor layer having a multi-layer structure including a channel layer and a semiconductor layer heterojunction to the channel layer, and etching the semiconductor layer. In a method of manufacturing a heterojunction FET, which comprises forming an active layer and then forming gate, source and drain electrodes on the active layer, a step of forming a gate electrode on the upper surface of the active layer, Forming a source and drain electrode from the upper surface of the active layer toward the upper surface of the semiconductor substrate along the side wall of the active layer in a direction orthogonal to A step of forming an insulating film on the active layer so that the surface of the electrode is exposed from the upper surface; and a gate extraction electrode part of which is bonded to the surface of the gate electrode. The method of manufacturing a heterojunction FET which comprises the step of extending toward from the surface of the gate electrode on said insulating film.