JPH04321237A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To restrain a leakage current from being generated between a mesa- etched channel layer and a gate metal at a high-electron-mobility transistor or the like. CONSTITUTION:An undoped GaInAs layer 2 as a channel layer formed on an InP substrate 1 and an n-AlInAs layer 3 as an electron supply layer are mesa- etched; after that, sidewall parts of the undoped GaInAs layer 2 are etched; recessed parts 6 are formed; an overhang shape is formed. As a result, even when a gate metal 7 is formed, the gate metal 7 does not come into contact with the undoped GaInAs layer 2 due to gaps by the recessed parts 6; a leakage current is suppressed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a field effect transistor having a carrier supply layer and a channel layer, and more particularly to a method for manufacturing a transistor such as a high electron mobility transistor.

0002

[Prior Art] Ultrahigh-speed transistors using compound semiconductors generally have higher electron mobility than silicon;
The scope of its application is expanding, and one such ultra-high-speed transistor is a high electron mobility transistor (2DEG) that utilizes two-dimensional electron gas (2DEG) generated at a hetero interface.
HEMT) type devices are known.

FIG. 7 is a perspective view of a main part of a general conventional high electron mobility transistor, in which a laminated film 72 consisting of a channel layer, an electron supply layer, etc. is formed on a compound semiconductor substrate 71 in a desired mesa-like pattern. is formed. The laminated film 7
Both ends of 2 are expanded into a rectangular shape, and ohmic electrodes 73, 7
3 is formed. A gate metal 74, which is a Schottky electrode, is wired between the electrodes, and the current between the source and drain changes according to a change in the gate voltage applied to the gate metal 74.

FIG. 8 shows a cross section of the gate wiring section. The substrate is an InP substrate 81, and below the gate metal 85, a mesa-etched buffer layer 82, a channel layer 83,
An electron supply layer 84 is laminated, and the channel layer 83 is made of, for example, GaInAs, and the electron supply layer 84 is made of, for example, n-AlI.
nAs. By using the GaInAs layer as a channel layer, mobility is increased and high-speed operation of the transistor is realized.

[0005]

In the mesa-etched active region of FIG. 7, gate metal 74 needs to be deposited over the gate width W. As shown in FIG. 8, gate metal 85 is normally formed so as to be in contact with both sides 86 of the mesa due to the precision of lithography.

However, in high-electron mobility transistors using a GaInAs layer as a channel layer for high speed use, GaInAs
Leakage current occurs because the Schottky barrier between the As layer and the gate metal becomes low. Needless to say, when the leakage current is large, the operating characteristics of the transistor deteriorate.

[0007] In order to reduce leakage current, a method of forming sidewalls of an insulating film such as SiO2 or Si3N4 on both sides of the mesa can be considered, but this method causes leakage paths to occur on the surface of the insulating film formed by CVD. However, organic materials such as polyimide cannot be easily manufactured due to the manufacturing process. It is also conceivable to limit the direction of vapor deposition of the gate metal to the vertical direction rather than the diagonal direction, but this is not practical because it is unstable whether the leakage current can be suppressed after all.

SUMMARY OF THE INVENTION In view of the above-mentioned technical problems, it is an object of the present invention to provide a method for manufacturing a field effect transistor that reliably suppresses the occurrence of leakage current.

[0009]

[Means for Solving the Problems] In order to achieve the above object, in the method for manufacturing a field effect transistor of the present invention, a channel layer and a carrier supply layer are formed on a substrate, and an overhang is formed in the channel layer. The method is characterized in that the channel layer is etched, and then a gate wiring is formed.

0010

[Operation] By etching the channel layer so that an overhang occurs in the channel layer, a hollow recess is formed on the side surface of the mesa. Therefore, even if the gate wiring is provided, the channel layer and the gate wiring do not come into direct contact with each other, and leakage current is suppressed.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described with reference to the drawings.

[First Embodiment] This embodiment is a method of manufacturing a high electron mobility transistor using a semi-insulating InP substrate. Hereinafter, this example will be explained according to its steps.

First, as shown in FIG. 1, semi-insulating InP
Non-doped GaInAs as a channel layer is formed on the substrate 1.
A layer 2 is laminated, and an n-AlInAs layer 3 as an electron supply layer is laminated on the non-doped GaInAs layer 2. These non-doped GaInAs layers 2 and n-Al
The InAs layer 3 is formed by MOCVD or MBE, respectively.
It is epitaxially grown by the method. As an example, the non-doped GaInAs layer 2 has a thickness of about 2000 Å and an n-
The AlInAs layer 3 has a thickness of about 1000 Å. n-
A GaInAs cap layer 4 is formed on the AlInAs layer 3.
is formed as a thin film of about 20 Å. In addition, non-doped G
Between the aInAs layer 2 and the InP substrate 1, there is a non-doped A layer.
A buffer layer, such as a lInAs layer, can be interposed.

Next, a photoresist is formed on the entire surface, selectively exposed to light, and developed after exposure. This development leaves a resist layer 5 with a gate width W only in the active region. After forming the resist pattern, patterning is performed using a non-selective etchant using the resist layer 5 as a mask. This etchant is for example H3PO
4:H2O2 (30%):H2O is 3:1:5
The etching process is carried out at a temperature of 20° C. and a time of 5 minutes. By this patterning, each of the layers 2 to 4 is removed so that the semi-insulating InP substrate 1 is exposed in areas other than the active region, and a mesa of the active region as shown in FIG. 2 is obtained.

Next, without removing the resist layer 5, the side wall of the non-doped GaInAs layer 2 is selectively etched to form a hollow recess 6 serving as an overhang, as shown in FIG. An example of an etchant for selectively etching the sidewalls of the non-doped GaInAs layer 2, which is a channel layer, is, for example, NH4OH.
:H2O2 (30%) in a ratio of 1:30, and etching can be performed at a temperature of 4 to 30 DEG C. for about 10 minutes. In this selective etching, the non-doped GaInAs layer 2 is etched at a rate of 12 to 13 Å/min, and the n-AlInAs layer 3 is etched at a rate of about 2 to 3 Å/min. Since it is etched faster than the AlInAs layer 3, the recesses 6 are formed in alignment with the sidewalls of the mesa.

[0016] Subsequently, the entire body is immersed in an acetone solution or the like,
As shown in FIG. 4, the resist layer 5 and the like are removed. As a result, an active region is formed that reflects the resist pattern and has a recess 6 on the side wall of the mesa of the active region, and does not face the non-doped GaInAs layer 2 serving as a channel layer.

Next, as shown in FIG. 5, gate metal 7 is formed in a fine pattern on the active region. This gate metal 7 becomes a Schottky electrode connected to the surface of the active region. The gate metal 7 is extended from the side wall of the mesa onto the InP substrate 1. On the side wall, the non-doped GaInAs layer 2 is overhanged by the recess 6, and the gate metal 7 is formed by the recess 6 of the cavity. The metal 7 does not directly contact the non-doped GaInAs layer 2 which is a channel layer. Therefore, leakage current between the gate metal 7 and the channel layer is reduced.

The field effect transistor manufactured by such a manufacturing method has a GaInAs layer 2 which is a channel layer.
A two-dimensional electron gas layer is formed at the interface on the n-AlInAs layer 3 side, resulting in extremely high electron mobility. Then, GaInA, which is the channel layer, is formed on the sidewall of the mesa.
Since the recess 6 is formed in the s-layer 2, direct contact between the gate metal 7 and the GaInAs layer 3 having a small band gap is prevented, and an increase in leakage current is suppressed.

In this embodiment, the etching for forming the recess 6 is used separately from the etching for the mesa etching, but it is also possible to perform etching so that the channel layer overhangs at the same time as the mesa etching.

[Second Embodiment] This embodiment is an example of a method for manufacturing a double heterostructure high electron mobility transistor.

First, to briefly explain the final structure of the device, as shown in FIG.
Non-doped AlInAs as a buffer layer is formed on the substrate 11.
layer 12, n-AlInAs layer 13 which is a lower electron supply layer;
, a GaInAs layer 14 as a channel layer, an n-AlInAs layer 15 as an upper electron supply layer, and a cap layer 16 made of GaInAs are stacked, and the layers above the AlInAs layer 12 are processed by mesa etching. A gate metal 17 is deposited on the mesa-shaped active region and further extends outside the active region. Even in a transistor with such a structure, the GaInAs layer 1 which is a channel layer is
Recesses 18, 18 are formed in the side wall portion of 4 to form an overhang shape. The gate metal 17 has a hollow recess 18
without directly contacting the GaInAs layer 14,
Therefore, leakage current can be suppressed.

[0022] Such a double heterostructure transistor is manufactured by sequentially forming each layer 12 to 12 by MOCVD or MBE.
After stacking the GaInAs layer 16, the active region is patterned, and then only the GaInAs layer 14, which is the channel layer, is selectively etched from the sidewalls. Examples of the selective etchant include a solution using NH4OH, as in the first embodiment. After the recesses 18, 18 are formed by selective etching, gate wiring may then be formed.

In this embodiment as well, it is possible to perform etching such that the channel layer is etched from the side surface at the same time as the mesa etching.

Furthermore, the method for manufacturing a field effect transistor of the present invention is not limited to the above-mentioned single heterostructure or double heterostructure, but can also be applied to devices having inverted HEMTs and other structures.

[0025]

According to the method of manufacturing a field effect transistor of the present invention, the channel layer is etched to form an overhang at the same time as or after patterning the active region. Therefore, when forming gate wiring,
Direct contact between the gate wiring and the channel layer is eliminated, and as a result, leakage current is reduced.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of the steps up to the step of laminating each layer on an InP substrate in an example of the method for manufacturing a field-effect transistor of the present invention.

FIG. 2 is a cross-sectional view of the steps from resist pattern formation to etching steps in an example of the method for manufacturing a field-effect transistor of the present invention.

FIG. 3 is a cross-sectional view of the steps up to the selective etching step of the channel layer in an example of the method for manufacturing a field effect transistor of the present invention.

FIG. 4 is a cross-sectional view of the steps up to the resist layer removal step in an example of the method for manufacturing a field-effect transistor of the present invention.

[
FIG. 5 is a cross-sectional view of the steps up to the gate metal formation step in an example of the method for manufacturing a field effect transistor of the present invention

[
FIG. 6 is a cross-sectional view showing the structure of a transistor according to another example of the method for manufacturing a field-effect transistor of the present invention.

[Figure 7
] A perspective view of the main parts of a transistor according to an example of a conventional method for manufacturing a field-effect transistor, cut away.

FIG. 8 is a device cross-sectional view of a gate electrode portion of a transistor according to an example of a conventional field-effect transistor manufacturing method.

[Explanation of symbols]

1, 11...InP substrate 2, 14...Non-doped GaInAs layer 3, 13, 15...n-AlInAs layer 5...Resist layer 6, 18... recess 7,17...Gate metal

Claims (1)

[Claims] 1. A field effect transistor characterized in that a channel layer and a carrier supply layer are formed on a substrate, the channel layer is etched so that an overhang occurs in the channel layer, and then a gate wiring is formed. Production method.