JP2002270821A - Method of manufacturing field effect semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the drain breakdown voltage so that the gate and the channel are not short-circuited while increase in the number of processes is suppressed low in the manufacturing method of a field effect semiconductor device. SOLUTION: A channel layer 3, an etching stop layer 5, a cap layer 6 and a cap layer 7 are formed on a substrate 1. The periphery of a transistor formation scheduled part on the surface of the cap layer 7 is etched over the channel layer 3, and an inter-element isolation region 2A is formed. A gate recess 6A is formed in the cap layer 7 and the cap layer 6, and etching for enlarging the gate recess of the cap layer 7 is conducted. The gate recess is made into a two-stage structure, and the edge of the channel layer 3 exposed to the side of the inter-element isolation region 2A is etched so as to form an air gap 3A. Then, a gate electrode 10 derived to the inter-element isolation region 2A is formed, over the air gap 3A from the gate recess 6A.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a HEMT (hig
electron mobility trans
isor) or MESFET (metal sem)
icon field effect t
The present invention relates to a method suitable for manufacturing a field-effect semiconductor device using a compound semiconductor such as a radiator as a material.

[0002]

2. Description of the Related Art Generally, a field effect type semiconductor device using a compound semiconductor as a material, in particular, a HEMT has an excellent low noise characteristic, and is used for an amplifier used in a frequency band such as a microwave or a millimeter wave, or for optical communication. It is often used for signal processing circuits in the system.

[0003] Among the above-mentioned field effect type semiconductor devices, those using an InP-based material are particularly suitable for use in the above-mentioned fields because of their excellent high-speed operation and low noise. In the case of the InP-based HEMT, when performing isolation between elements, it is difficult to form an insulating region by an ion implantation method. Therefore, isolation between elements is performed by mesa formation.

In the case where the isolation between elements is realized by mesa formation of the stacked semiconductor layers, the side surfaces of the respective semiconductor layers are exposed on the side surfaces of the mesa. Since the portion crawls on the side of the mesa, the gate electrode and the InGaAs channel layer, for example, come into contact with each other.

Therefore, the InGaAs channel layer is side-etched to create a space called an air gap, and the gate electrode does not contact the InGaAs channel layer.

Usually, the InGaAs channel layer is sandwiched between an InAlAs buffer layer and an InAlAs carrier supply layer on the upper and lower sides. Therefore, when performing side etching, it is necessary to selectively etch InGaAs with respect to InAlAs. An air gap can be easily formed by using a possible etchant.

When a gate electrode material film is formed by a vacuum deposition method in the above state, the air gap is maintained as it is, so that a short circuit between the channel and the gate can be avoided. The side etching is
Usually, it is carried out immediately before forming the gate electrode.

[0008] Apart from the above-mentioned problem that the channel and the gate are short-circuited, the InP HEMT is a GaAs HEM.
There is also a problem that the drain withstand voltage is lower than that of T. In order to avoid this problem, a gate recess is formed in two stages to reduce the electric field applied between the gate and the drain to improve the drain withstand voltage. Have been.

However, since the formation of the air gap and the formation of the two-stage gate recess are performed in separate steps, the number of steps is increased and complicated. There's a problem.

[0010]

SUMMARY OF THE INVENTION In the present invention, the gate and the channel are prevented from being short-circuited and the drain withstand voltage can be improved while suppressing the increase in the number of steps.

[0011]

According to the present invention, it is essential that an air gap can be formed during the step of forming a gate recess.

For example, in a semiconductor layer configuration of an InP-based HEMT, an etching stop layer of a gate recess has In
In many cases, a P layer is used, and In is used as a cap layer.
A stacked structure of AlAs (etching stop layer side) / InGaAs (front side) is used.

In the case of this laminated structure, to form a gate recess, an InGaAs layer and an InAlAs layer are formed by an InP layer.
A first recess opening is formed by selectively etching the layer, and an air gap between the second recess and the channel layer is formed simultaneously by selectively etching only the InGaAs layer.

The means, that is, a two-stage recess is automatically formed by forming an air gap during the formation of the gate recess, avoiding a short circuit between the gate and the channel, and
The two problems of the improvement of the drain withstand voltage due to the two-stage recess structure can be easily solved with a small number of steps.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a fragmentary plan view showing a field-effect semiconductor device manufactured according to an embodiment of the present invention. In FIG. 1, reference numeral 5 denotes an i-InP etching stop layer. , 6 are n-InAlAs cap layers, 7 is n-InG
aAs cap layer, 8 is a source electrode, 9 is a drain electrode, and 10 is a gate electrode.

FIGS. 2A and 2B are cutaway side views of the main part showing the field effect type semiconductor device shown in FIG. 1, wherein FIG. 2A is a cutaway side view of the main part along line XX shown in FIG. Is a cutaway side of the main part along the line Y-Y seen in FIG. 1, and the same symbols as those used in FIG. 1 represent the same parts or have the same meanings.

In FIG. 2, 1 is a semi-insulating InP substrate,
2 is an i-InAlAs buffer layer, 3 is i-InGaAs
The s channel layer 3A is an air gap formed by undercutting the channel layer 3, and 4 is an n-InAlAs carrier (in this case, electron) supply layer.

The outermost portion shown in FIG. 1 shows a mesa side wall for element isolation. As is apparent from FIG. 2, a two-stage gate recess is formed between the source electrode 8 and the drain electrode 9. ing.

The gate electrode 10 is formed in the recess through the side surface of the step formed by the mesa for element isolation, and crawls on the step side wall where the edge of the channel layer 3 exists. Since the edge is undercut to form the air gap 3A, a short circuit between the channel layer 3 and the gate electrode 10 does not occur.

FIG. 3 to FIG. 6 are cutaway side views of a main part of a field effect type semiconductor device in a process step for explaining an embodiment of the present invention. The same symbols as used symbols represent the same parts or have the same meanings. In each of the figures, (A) is a cutaway side of a main part along line XX shown in FIG. 1, (B) Is a cut-away side view of the main part along the line Y-Y seen in FIG. 1 and will be described below with reference to these figures.

See FIG. 3 (1) MOCVD (metalorganic che
The buffer layer 2, the channel layer 3, the carrier supply layer 4, the etching stop layer 5, the cap layer 6, and the cap layer 7 are grown on the substrate 1 by applying a physical vapor deposition method.

The main data of each semiconductor portion shown in FIG. 3 is exemplified as follows. Substrate 1 Material: Semi-insulating InP buffer layer 2 Material: i-InAlAs Thickness: 300 [nm] Channel layer 3 Material: i-InGaAs Thickness: 25 [nm] Carrier supply layer 4 Material: n-InAlAs Impurity concentration: 3 × 10 ¹⁸ [cm ⁻³ ] Thickness: 25 [nm] Etching stop layer 5 Material: i-InP Thickness: 6 [nm] Cap layer 6 Material: n-InAlAs Impurity concentration: 5 × 10 ¹⁸ [cm ^{− 3} ] Thickness: 20 [nm] Cap layer 7 Material: n-InGaAs Impurity concentration: 1 × 10 ¹⁹ [cm ⁻³ ] Thickness: 30 [nm]

(2) By applying a resist process in a lithography technique, a resist layer 11 that exposes only a portion where an element isolation region is to be formed is formed.

(3) By applying a wet etching method using a mixture of phosphoric acid + hydrogen peroxide + water as an etchant, the mesa layer reaching the etching stop layer 5 from the exposed surface of the cap layer 7 Perform etching.

By applying a wet etching method using hydrochloric acid as an etchant, the etching stop layer 5 made of InP is removed, and then the mesa / etching solution reaching the inside of the buffer layer 2 using the above-mentioned phosphoric acid-based etching solution. Etching is performed to form the inter-element isolation region 2A.

Referring to FIG. 4, (4) the resist layer 11 is removed by immersion in a resist stripping solution, and then the resist layer in the lithography technique is renewed.
By applying the process, a resist layer that exposes only a portion where a source electrode is to be formed and a portion where a drain electrode is to be formed is formed.

(5) By applying a vacuum deposition method,
From the substrate side, a 10 nm thick Ti film / 30 nm thick Pt film / 300 nm thick Au film is formed.

(6) A lift for removing the resist layer formed in the step (4) together with each metal film formed in the step (5).
The source electrode 8 and the drain electrode 9 are formed by applying the off method.

(7) By applying a resist process in a lithography technique, a resist layer 12 exposing only a portion where a gate recess is to be formed is formed.
In this case, photolithography may be applied to the resist process, but electron beam lithography may be applied if necessary.

(8) The exposed cap layer 7 and cap layer 6 are etched by applying a wet etching method using a mixed solution of phosphoric acid + hydrogen peroxide + water as an etchant. A recess 6A is formed.

In this case, the cap layers 7 and 6
Are etched in substantially the same manner, so that the openings in the gate recesses 6A are equal.

Referring to FIG. 5 (9) By applying a wet etching method using a mixed solution of citric acid + hydrogen peroxide + water as an etchant, as shown in FIG. Channel layer 3 made of InGaAs is formed of InAlAs.
Under etching by selectively etching
Cut to generate an air gap 3A.

Here, during the etching step for generating the air gap 3A, the same etchant is used to form the air gap 3A.
Only the cap layer 7 made of GaAs is side-etched, so that the gate recess 6A composed of the cap layer 7 and the cap layer 6 automatically has a two-stage structure.

Referring to FIG. 6 (10) A resist layer exposing only a portion where a gate electrode is to be formed is formed by applying a resist process in a lithography technique. In this case, photolithography may be applied to the resist process, but electron beam lithography may be applied if necessary.

(11) By applying the vacuum evaporation method, a 10 nm thick Ti film / 30 nm from the substrate side
A thick Pt film / a 600 [nm] thick Au film is formed.

(12) The gate electrode 10 is formed by applying a lift-off method of removing the resist layer formed in the step (10) together with each metal film formed in the step (11).

In the field-effect type semiconductor device manufactured through the above steps, that is, in the HEMT, as shown in FIG. 6A, a gate recess 6A having a two-stage structure is formed. As can be seen in FIG. 1B, even if the gate electrode 10 extends along the mesa side wall, it does not contact the channel layer 3 and has such a structure, namely, the formation of the air gap 3A and the two-stage structure. It is clear that the formation of the gate recess 6A of FIG.

In the above embodiment, an InP-based HEMT has been described. However, the present invention is not limited to this. For example, the present invention can be applied to a GaAs-based HEMT. To
InGaP for the carrier supply layer and InGa for the cap layer.
If As / GaAs or InGaAs / AlGaAs is adopted, the same effect as in the case of the InP-based HEMT described above can be obtained.

The present invention can be similarly applied to other field effect type semiconductor devices such as MISFETs and MESFETs using a semiconductor having a wide energy band gap as a pseudo gate insulating film and using a heterojunction. , And furthermore, the gate electrode 1 shown in the above embodiment.
It is optional to substitute 0 for a T-type gate electrode or a notch-type gate electrode.

As is apparent from the above description, the present invention can be applied to field-effect transistors having various structures in addition to the InP-based HEMT.
In the MT, the first cap layer, that is, the InP etching stop layer underlying the cap layer on the substrate side may be a carrier supply layer in a field-effect transistor having another configuration, or may be a MISFET or the like. In some cases, a semiconductor layer having a wide energy band gap may be used as a cap underlayer.

The present invention can be embodied in many forms, including the above-described embodiment. (Supplementary Note 1) At least a channel layer (for example, an i-InGaAs channel layer 3) and a cap underlayer (for example, an i-InP etching stop layer 5, a field effect transistor having another structure) on a substrate (for example, a semi-insulating InP substrate 1). A carrier supply layer, a semiconductor layer having a wide energy band gap, etc.) and a first cap layer (eg, n-InAl
As cap layer 6) and a second cap layer (for example, nI) etched by the same etching means as the channel layer.
sequentially forming an nGaAs cap layer 7).
Next, the periphery of the portion where the transistor is to be formed is etched from the surface (for example, the surface of the n-InGaAs cap layer 7 as the second cap layer) to the channel layer to form an element isolation region (for example, the element isolation region 2A). Forming, then forming a gate recess (eg, gate recess 6A) in the second cap layer and the first cap layer, and then removing the gate recess formed in the second cap layer. By performing the expanding etching to form a gate recess having a two-stage structure in combination with the gate recess in the first cap layer, the edge of the channel layer exposed on the side surface of the element isolation region is simultaneously removed. A step of forming an air gap (for example, an air gap 3A) by performing etching for cutting, and thereafter, forming a gate;
Forming a gate electrode (eg, gate electrode 10) formed on the cap underlayer exposed in the recess and extending to the device isolation region beyond the air gap. Of manufacturing a field-effect type semiconductor device.

(Supplementary Note 2) The cap underlayer has at least I
The method for manufacturing a field-effect type semiconductor device according to (Supplementary Note 1), comprising a material containing n and P (for example, InP).

(Supplementary Note 3) The first cap layer is made of a material containing at least Al (eg, InAlAs), and the second cap layer is made of a material containing at least In and As (eg, InGaAs). (Supplementary Note 1) The method for manufacturing a field-effect semiconductor device according to (1).

[0044]

In the method of manufacturing a field-effect semiconductor device according to the present invention, at least the channel layer, the cap underlayer, and the first cap layer and the channel layer are etched on the substrate by the same etching means. 2 are sequentially formed in layers, and the periphery of the portion where the transistor is to be formed is etched beyond the channel layer from the surface to form an element isolation region, and a gate recess is formed in the second cap layer and the first cap layer. Is formed and etching is performed to enlarge the gate recess formed in the second cap layer to form a gate recess having a two-stage structure in combination with the gate recess in the first cap layer. At the same time, etching is performed to undercut the edge of the channel layer exposed on the side surface of the element isolation region to form an air gap, and the gate Is formed on the exposed by a cap underlayer in the scan beyond the air gap to form a gate electrode that is derived to the device isolation region.

By adopting the above structure, the formation of the air gap by the undercut of the channel layer is automatically performed during the step of forming the two-step recess, and a short circuit between the gate and the channel can be avoided. Further, a two-step recess structure capable of improving the drain withstand voltage can be easily realized with a small number of steps.

[Brief description of the drawings]

FIG. 1 is a fragmentary plan view showing a field-effect semiconductor device manufactured according to an embodiment of the present invention.

FIG. 2 is a fragmentary side view showing a main part of the field-effect semiconductor device shown in FIG. 1;

FIG. 3 is a fragmentary side view showing a field-effect semiconductor device at a key step in the process for describing one embodiment of the present invention.

FIG. 4 is a fragmentary sectional side view showing a field-effect semiconductor device at a key point in a process for describing an embodiment of the present invention;

FIG. 5 is a fragmentary sectional side view showing a field-effect semiconductor device at an important point in a process for describing an embodiment of the present invention.

FIG. 6 is a fragmentary sectional side view showing a field-effect semiconductor device at an important point in a process for describing an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Buffer layer 2A Element isolation region 3 i-InGaAs channel layer 3A air gap 4 n-InAlAs carrier supply layer 5 Etch stop layer 6 Cap layer (first cap layer) 6A Gate recess 7 Cap layer (first layer) 2 cap layer) 8 source electrode 9 drain electrode 10 gate electrode 11 resist layer

Claims (3)

[Claims] A step of sequentially forming at least a channel layer, a cap underlayer, and a second cap layer etched by the same etching means as the first cap layer and the channel layer on a substrate; Forming a device isolation region by performing etching beyond the channel layer from the surface around the portion, forming a gate recess in the second cap layer and the first cap layer, and Etching to enlarge the gate recess formed in the second cap layer is performed to form a gate recess having a two-stage structure in combination with the gate recess in the first cap layer, and at the same time, an element isolation region A step of undercutting the edge of the channel layer exposed on the side surface to form an air gap, and thereafter, Forming a gate electrode formed on the cap underlayer exposed in the gate recess and extending to the element isolation region beyond the air gap. Of manufacturing a semiconductor device. 2. The method according to claim 1, wherein the cap underlayer is made of a material containing at least In and P. 3. The field effect semiconductor device according to claim 1, wherein the first cap layer is made of a material containing at least Al, and the second cap layer is made of a material containing at least In and As. Manufacturing method.