JP3233207B2 - Method for manufacturing field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a field effect transistor, and more particularly, to a method for manufacturing a Schottky junction field effect transistor (hereinafter referred to as MESFET) and a heterojunction field effect transistor (hereinafter referred to as HJFET). The present invention relates to a method of manufacturing a field effect transistor (hereinafter, referred to as an FET) having a structure in which a gate electrode is buried offset to only the source side by a step recess.

[0002]

2. Description of the Related Art In general, compound semiconductors are characterized by having a higher electron mobility than Si, and are characterized by 1 GHz.
Since high power efficiency can be obtained with the above-mentioned microwave band or millimeter wave band amplification FETs, application to analog signal amplifier circuits, digital signal processing circuits, and the like in which these are integrated is progressing.

A two-stage recess buried gate structure is known as a compound FET structure that is practically used. By embedding the gate electrode in the second recess, the two-stage recess buried gate structure improves the followability of transfer characteristics such as frequency dispersion and pulse dullness due to trapping of the crystal surface level of the first recess. In addition, the first recess secures the withstand voltage. The manufacturing method of this two-stage recess embedded gate structure is as follows.
For example, it is disclosed in "Method of Manufacturing Semiconductor Device" in Japanese Patent Application Laid-Open No. 2-105540 (hereinafter, this technique is referred to as Conventional Example 1).

FIGS. 27 to 34 are cross-sectional views showing the manufacturing method of the conventional example 1 for each process. First, as shown in FIG. 27, the surface of a semiconductor substrate 41, which is a semi-insulating GaAs substrate, is ion-implanted with Si and heat-treated to form an n-type active layer 42.
To form An insulating film 43 such as an SiO ₂ film is coated on the surface of the n-type active layer 42, and a gate opening 44 having a horizontal length of 1.5 μm is formed in the insulating film 43 using dilute hydrofluoric acid by a photoresist technique. .

Then, as shown in FIG. 28, an n-type active layer 42 is dug by 0.2 μm from the gate opening 44,
A first recess 45 is formed. This etching is performed using a mixed solution of sulfuric acid and hydrogen peroxide solution.

Next, as shown in FIG. 29, a sidewall film (SiO ₂ ) 46 is formed on the first recess 45 and the insulating film 43.
Is deposited to a thickness of 0.5 μm.

Next, as shown in FIG. 30, the side wall film 46 is processed into the side wall 47 by anisotropic dry etching. As a result, 1.5 μm of the initial gate opening 44 becomes a gate opening 44 a narrowed to about 0.7 μm by the side wall 47.

Next, as shown in FIG. 31, an n-type active layer 42 is dug by 0.03 μm using the above-mentioned mixed solution to form a second recess 48.

Next, as shown in FIG. 32, a gate metal 49 made of Al is deposited on the entire surface, and a photoresist film 50 is covered so as to cover the gate opening 44.

Next, by processing the gate metal 49, a gate electrode 51 as shown in FIG. 33 is formed.
The gate opening 44a buried in the second recess 48 and defined by the side wall 47 has a gate length.

Next, as shown in FIG. 34, an ohmic source electrode 52 and an ohmic source electrode 53 are provided on the n-type active layer 42 which is not recessed on both sides of the gate electrode 51, thereby forming a two-step recessed buried gate. An FET having the structure is formed. The insulating film 43 for reducing the gate capacitance once removed, growing thinner as a protective film of SiO ₂ again, the amplification FET is completed by forming an electrode wiring in an air bridge type or the like.

The FET structure disclosed in the prior art 1 has a problem that the withstand voltage decreases when the gate length is shortened to increase the cutoff frequency. To solve this problem,
The inventor of the present application has proposed a structure in which the gate electrode is offset only on the source side and embedded in the second recess.
This structure is disclosed in Japanese Patent No. 2685026 entitled "Field Effect Transistor and Manufacturing Method" (hereinafter, this technique is referred to as Conventional Example 2).

The frequency dispersion and pulse dulling in the transient characteristics, the kink phenomenon in the static characteristics, and the deterioration of the drain current saturation are caused by the holes generated by the avalanche on the drain side flowing and the surface level and the source side on the source side. The main factor is to modulate this source resistance. These transient characteristics and static characteristics can be improved by embedding the source side in a semiconductor layer (n-type active layer) and suppressing the influence of fluctuation of the surface state. On the other hand, on the drain side, the gate electrode is removed and the layers are hierarchized into two levels. By pseudo-gradient, the electric field concentration is reduced and the drain breakdown voltage and the like are improved.

FIGS. 35 to 45 are sectional views showing the manufacturing method of the conventional example 2 for each process, and FIG. 46 is a plan view showing patterns of electrodes and the like. FIG. 45 is a sectional view taken along line EE of FIG.

First, as shown in FIG.
An i-type GaAs buffer layer 16 is formed on a semiconductor substrate 1 as an As substrate by metal organic chemical vapor deposition (MOVPE).
an i-type InGaAs electron transit layer 15, an n-type AlGaAs channel layer (electron supply layer) 2, an n-type GaAs lower contact layer 3, an etching stop layer 4 as a lower contact layer,
An n-type GaAs upper contact layer 5 is sequentially epitaxially grown. Here, a high mobility two-dimensional electron gas is generated on the electron transit layer 3 side at the boundary with the electron supply layer 2, and thus the electron transit layer is generally called a channel layer. However, in the depletion type FET, a drain current flows also in the electron supply layer, and acts as a channel. In the following description of the present specification, for simplicity of description, the electron supply layer is represented by a channel layer, and the layers below this are omitted.

On a series of epitaxially grown layers, SiO
₂ is formed on the insulating film 6, and the insulating film 6 has a horizontal length of 1.2 μm.
An m gate opening 7 is formed. The gate opening 7 is formed by low damage magnetron dry etching using CHF ₃ gas.

Next, as shown in FIG. 36, the upper contact layer 5 of n-type GaAs on the etching stopper layer 4 of n-type AlGaAs is opened from the gate opening 7 formed in the insulating film 6.
Is selectively crystal-etched to provide a first recess 45. This etching is magnetron dry etching using a gas obtained by adding SF ₆ 30% to BCl _3. Since aluminum fluoride AlF is formed on the surface of AlGaAs, etching is suppressed and stopped.
The etching selectivity of GaAs / Al _0.2 Ga _0.8 As is 1
More than 00 times.

Next, as shown in FIG. 37, a SiO ₂ film is deposited, and a side wall 8 is provided by magnetron type anisotropic dry etching using the above-mentioned CHF ₃ gas to form a gate opening 7a.

Next, as shown in FIG. 38, the n-type AlGaAs of the exposed etching stopper layer 4 is wet-etched. The etching solution is a mixture of phosphoric acid and aqueous hydrogen peroxide, diluted with pure water, and reduced in etching rate. The exposed lower contact layer 3 of n-type GaAs is subjected to the selective crystal etching described above to form the n-type AlGaAs channel layer 2.
And a second recess 48 is provided.

Next, as shown in FIG. 39, a gate metal 61 made of WSi is sputter deposited to a thickness of 0.2 μm,
It is buried in the second recess 48 and is brought into contact with the side surface of the lower contact layer 3.

Next, as shown in FIG. 40, the gate metal 61 is processed by magnetron type anisotropic dry etching to form a metal side wall 62 having a horizontal length (gate length) of 0.1 μm. As the etching gas, a mixture of CF ₄ and 20% oxygen is used.

Next, as shown in FIG. 41, the metal side wall 64 on the source side is covered with a photoresist film 63, and the other metal side wall 64 is formed by increasing the gas pressure with CF ₄ and oxygen gas to enhance isotropy. By magnetron dry etching. As a result, the remaining metal side wall 62 becomes the gate electrode 6.
It becomes 4.

Next, as shown in FIG. 42, an insulating film 65 of SiO ₂ is deposited, a photoresist film 66 is applied, and the surface is etched back by reactive ion etching (RIE) utilizing this smoothness. As shown in FIG. 43, the upper portion of the gate electrode 64 is exposed from the SiO ₂ insulating film 65.

Next, as shown in FIG.
Are formed by sputtering to form a power supply wiring 67 connected to the gate electrode 64.

Next, as shown in FIG. 45, ohmic source and drain electrodes 13 and 14 are formed on the n-type GaAs upper contact layer 5 on both sides of the gate electrode 64, and the remaining insulating film 65 is removed. By doing so, an FET having an offset structure in which the gate is buried only in the source side by the two-stage recess is formed.

Further, a manufacturing method has been proposed in which a gate electrode is offset-formed with respect to a one-step recess. This method is disclosed, for example, in Japanese Patent No. 2725592, entitled "Method of Manufacturing Field Effect Transistor" (hereinafter, this technique is referred to as Conventional Example 3).

FIGS. 47 to 50 are sectional views showing the manufacturing method of the conventional example 3 for each process. First, as shown in FIG. 47, an i-type semiconductor substrate 71 is a semi-insulating GaAs substrate.
A GaAs channel layer 72, an n-type AlGaAs electron supply layer 73, and an n-type GaAs contact layer 74 are sequentially grown by molecular beam epitaxy (MBE), and an SiO ₂ insulating film 75 is deposited. Gate opening 7
6 is formed. An n-type GaAs contact layer 74 is formed by selective crystal dry etching using BCl ₃ and SF ₆ gases.
And the lower AlGaAs electron supply layer 7
3 is continued after the exposure, and the contact layer 74 is side-etched by 0.1 μm.

As described in Conventional Example 2, GaAs / AlG
aAs has an etching ratio of 100 times or more,
With little etching of the As electron supply layer 73, Ga
The As contact layer 74 can be side-etched.

Next, as shown in FIG. 48, the source side is covered with a photoresist 77 with respect to the inside of the gate opening 76, and n-type G
The aAs contact layer 74 is laterally etched to 0.3 μm from the end of the gate opening 76 in the lateral direction.

Next, as shown in FIG. 49, the photoresist film 77 is removed, and a gate metal is deposited and processed to form a gate electrode 78.

Next, as shown in FIG. 50, ohmic source and drain electrodes 79 and 80 are formed on the n-type GaAs contact layer 74 remaining on both sides of the gate electrode 78, and the remaining insulating film 75 is removed. As a result, an FET having a structure in which the gate electrode 78 is offset by one-stage recess is formed.

[0032]

In the manufacturing method of the offset structure in which the gate is buried only at the source side by the two-stage recess shown in the conventional example 2, the gate length is as short as 0.1 μm and the millimeter wave band is several tens GHz. to obtain a high cutoff frequency f _t of use and require long and complicated process. As a result, there is a problem that the manufacturing time becomes longer and the manufacturing cost and the product price increase. It should be noted that the structure offset by the two-stage recess to improve the gate transfer characteristics including the transient characteristics and ensure the withstand voltage of the device is not limited to the millimeter wave band of several tens of GHz, but several gigahertz.
It is also effective for the microwave band of Hz. In this case, since the cutoff frequency _ft is not so required, the gate length may be large, and there is no need to use a complicated process.

In the method of manufacturing the offset structure in the third conventional example, a single-step recess is used, but this manufacturing principle can be applied to a two-step recess structure. However, FIG.
51, the contact layer 74 is side-etched and there is a large gap when the gate metal 78 is sputtered. Therefore, the metal 82 deposited on the bottom crystal plane and the insulating film 75 are actually formed as shown in FIG. There is a problem that the deposited metal 81 is disconnected without being connected, and may not function as a gate electrode. Insulating film 7 in gate opening 76
Since the sputtered gate metal adheres to the side surface of No. 5 to narrow the opening, if the opening is closed with metal, the deposition on the lower crystal plane stops, and the upper and lower metals are not connected.

The present invention has been made to solve the above-mentioned problems, and has an offset structure in which a gate is buried only in the source side by a two-stage recess, which is simpler and prevents disconnection. It is an object of the present invention to provide a method for manufacturing a field-effect transistor that can be performed.

[0035]

According to the present invention, there is provided a method of manufacturing a field effect transistor, comprising: (1) a step of forming a conductive semiconductor layer on a semiconductor substrate; and (2) a step of engraving the conductive semiconductor layer. (3) depositing an insulating film to form a gate opening located inside the first recess; and (4) further forming the conductive semiconductor layer from the gate opening. Forming a second recess by digging and suppressing lateral side etching; and (5) forming a Schottky gate metal and a low-resistance gate metal as gate electrode materials on the entire surface and in the second recess. A photoresist film is provided so as to cover the source side from the center of the gate opening, and the gate electrode material on the drain side in the second recess is removed by using the photoresist film as a mask, and Forming a gate electrode such that the gate electrode material is left only in the vicinity of the source side including the source side region of the gate opening; (6) a conductive semiconductor layer which is not dug on both sides of the gate electrode Forming a source electrode and a drain electrode having ohmic properties on the region (a), wherein the steps are performed in the order of (1) to (6).

The method of manufacturing a field-effect transistor according to the present invention also includes (1) a step of forming a conductive semiconductor layer on a semiconductor substrate, and (2) a step of digging the conductive semiconductor layer to provide a first recess. (3) depositing an insulating film to form a gate opening located inside the first recess;
(4) a step of further digging the conductive semiconductor layer from the gate opening and providing a second recess while suppressing lateral side etching; and (5) workability so as to cover the inside of the second recess. Forming a lower gate electrode and an upper gate electrode with two different types of gate electrode materials, respectively;
(6) The lower gate electrode and the source side of the upper gate electrode are protected, and only the lower gate electrode is side-etched from the drain side to the middle of the second recess so as to leave the lower gate electrode only near the source side. Process and (7)
Forming ohmic source and drain electrodes on regions of the conductive semiconductor layer that are not dug out on both sides of the lower gate electrode and the upper gate electrode, in the order of (1) to (7). It is characterized by being performed.

The step (6) is performed by dry etching. The gate electrode material of the lower gate electrode is a substance having a high etching rate in dry etching, and the gate electrode material of the upper gate electrode is dry etching. Is preferably a substance having a low etching rate.

A fluorine-based gas is used for the dry etching, and the gate electrode material of the lower gate electrode is WS
i, W, Ti, Mo, Ni, C, a material selected from the group consisting of these silicides or nitrides, and the gate electrode material of the upper gate electrode is selected from the group consisting of Au, Al, and Pt. Preferably, it is a substance.

Another method for manufacturing a field-effect transistor according to the present invention includes: (1) forming a conductive semiconductor layer including an etching stop layer having a low etching rate on a semiconductor substrate; and (2) forming the conductive semiconductor layer on a semiconductor substrate. A step of forming a dug first recess; (3) a step of depositing an insulating film to form a gate opening located inside the first recess; and (4) forming a conductive semiconductor layer from the gate opening. Forming a second recess by digging and stopping at an etching stop layer and suppressing lateral side etching; (5) a second recess;
Protecting the source side of the recess, and side-etching the drain side of the conductive layer having a high etching rate above the etching stop layer to extend the second recess to the drain side; and (6) gate opening And (7) forming ohmic source and drain electrodes on regions of the conductive semiconductor layer that are not dug out on both sides of the gate electrode. Then, the steps are performed in the order of (1) to (7).

The gate opening may be formed by depositing an insulating film and then etching the insulating film to provide a sidewall of the insulating film in the first recess.

The gate opening may be formed by depositing an insulating film and then etching using a resist film having an opening located inside the first recess as a mask.

According to still another method of manufacturing a field effect transistor of the present invention, there are provided (1) a step of forming a conductive semiconductor layer including first and second etching stop layers having a low etching rate on a semiconductor substrate; 2) depositing an insulating film to provide a first gate opening; and (3) digging a conductive semiconductor layer from the first gate opening and stopping at a first etching stop layer to form a first recess. And (4) protecting the source side of the first recess, and side-etching the conductive semiconductor layer having a high etching rate above the first etching stop layer to the drain side to form the first recess. (5) a step of providing a side wall of the insulating film inside the first gate opening and the first recess, and (2) narrowing the second gate opening and the first recess by providing a side wall of the insulating film.
(6) a step of providing a second gate opening, and (6) further digging a conductive semiconductor layer from the second gate opening to stop at the second etching stop layer, and to suppress lateral side etching to form the second gate opening. Providing a recess of (7)
Protecting the source side of the recess, and performing side etching on the drain side of the conductive semiconductor layer having a higher etching rate on the upper side of the second etching stop layer with a width smaller than the etching width of the first recess. (8) a step of forming a gate electrode so as to be buried immediately below the second gate opening, and (9) a region of the conductive semiconductor layer on both sides of the gate electrode which is not dug. And a step of forming an ohmic source electrode and a drain electrode, which are performed in the order of (1) to (9).

It is preferable that the second recess is formed to have a depth of 50 nm or less.

[0044]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIGS. 1 to 4 are cross-sectional views showing steps of a method for manufacturing a field-effect transistor according to a first embodiment of the present invention, and FIG. 5 is a plan view showing patterns of electrodes and the like. FIG. FIG. 4C is a sectional view taken along line AA of FIG.

First, as shown in FIG.
A buffer layer 16, an electron transit layer 15, a channel layer (electron supply layer) 2, a lower contact layer 3, an etching stop layer are formed on a semiconductor substrate 1, which is an s substrate, by metal organic chemical vapor deposition (MOVPE). 4. The upper contact layer 5 is sequentially epitaxially grown.

The buffer layer 16 is formed of i-type GaAs having a thickness of 500 nm. The electron transit layer 15 has a thickness of 1
It is formed of 5 nm i-type In _0.15 Ga _0.85 As.
The channel layer (electron supply layer) 2 is made of n-type Al _0.2 Ga _0.8 A
s and a thickness of 30 nm at a concentration of 2 × 10 ¹⁸ cm ⁻³ and a thickness of 20 nm at a concentration of 1 × 10 ¹⁷ cm ⁻³ (each layer is not shown). Lower contact layer 3
Is n-type GaAs having a concentration of 5 × 10 ¹⁷ cm ⁻³ and a thickness of 20 nm.
s. The etching stop layer 4 formed on the lower contact layer 3 is formed of n-type Al _0.2 Ga _0.8 As with a concentration of 5 × 10 ¹⁷ cm ⁻³ and a thickness of 3 nm. The upper contact layer 5 has a concentration of 3 × 10 ¹⁸ cm ^-3 and a thickness of 10
It is formed of 0 nm n-type GaAs. For simplicity of explanation, the electron supply layer is represented by a channel layer,
The layers below this are omitted.

As shown in FIG. 5, the element region 17 is covered with a photoresist film, and a defect is generated by ion implantation to increase the resistance to make the periphery of the element region 17 an element isolation region 18. The ion implantation conditions are ¹¹ B ⁺ at an acceleration energy of 200 keV and an implantation dose of 1 × 10 ¹³ cm ⁻² .

As shown in FIG. 1, an insulating film 6 made of SiO ₂ having a thickness of 400 nm is coated on the above-described series of epitaxially grown layers, and a gate opening 7 having a lateral length of 1.4 μm is formed in the insulating film 6. . The gate opening 7 is formed by using a photoresist film as a mask and performing low-damage electron cyclotron resonance (ECR) (Electron Cyclotron Resonance) dry etching using SF ₆ gas. And
The photoresist film is removed, the upper contact layer 5 of n-type GaAs is selectively crystal-etched, and a first recess 19 is provided. With low damage ECR dry etching, BCl
₃ is performed at a pressure of 1 mtorr using a mixed gas of 15 sccm and SF ₆ at 5 sccm (25%). GaAs and Al
The etching selectivity of GaAs is 100 times or more, and n-type A
The etching stop layer 4 of lGaAs remains exposed.

Next, as shown in FIG. 2, a SiO ₂ film is deposited to a thickness of 300 nm, and the side walls 8 are formed by ECR dry etching using SF ₆ gas. The lateral thickness of the formed side wall is 0.2 μm, and a new gate opening 7 is formed.
a is reduced to a horizontal length of 1.0 μm.

Next, as shown in FIG. 3, the etching stopper layer 4 is removed to expose the lower contact layer 3 of n-type GaAs. To remove the etching stop layer 4, the crystal surface is oxidized by lightly applying oxygen plasma, and hydrochloric acid (36 wt.
%): Water = 1: 1 diluent (temperature: 20 ° C.) for 2 minutes to remove the oxide layer, wash with water and dry.
Is shaved. Exposed lower contact layer 3 of n-type GaAs
Is subjected to the selective crystal etching described above to obtain n-type AlG
The second recess 20 is provided by exposing the channel layer 2 of aAs. A desired etching time is set so as to reduce lateral over-etching.

Next, as shown in FIG. 4 (a), after the organic crystal is washed with methyl ethyl ketone or the like and immersed in the above-mentioned diluted hydrochloric acid to purify the crystal face, the Schottky gate metal 9 made of WSi _{0.6 having} a thickness of 100 nm is formed. A low-resistance gate metal 10 made of W having a thickness of 300 nm is deposited by sputtering. The gate metal 9 is attached to the side surface of the lower contact layer 3 and is buried. Then, a photoresist film 11 is provided so as to cover the source side from the center of the gate opening 7.

Next, as shown in FIG. 4B, the gate metals 9 and 10 are processed using the photoresist film 11 as a mask to form a gate electrode 12. Gate electrode 12 is EC
It is formed by R method dry etching using SF ₆ gas. Over-etching is performed so that the gate metal does not remain beside the side wall 8, and the gate electrode 12 is side-etched, leaving 0.4 μm as a lateral length on the channel layer 2.
This is the gate length.

Next, as shown in FIG. 4C, Au is formed on the remaining upper contact layer 5 on both sides of the gate electrode 12.
The source electrode 13 and the drain electrode 14 are formed by the ohmic alloy layer of GeNi, and the HJFET of the present invention is formed. Thereafter, in order to reduce the gate capacitance, the remaining SiO ₂ insulating film 6 on the surface is once removed with buffered hydrofluoric acid, and the SiO ₂ film is again deposited as a protective film to a thin thickness of 100 nm using an air bridge method. Are formed to form an amplification FET.

The electrical characteristics obtained by the HJFET according to the present invention are as follows. Note that the gate width W _G = 50 μm × 2 lines = 100 μm, and the gate length L _G =
0.4 μm. Gate threshold _{V T = -0.9V (V D =} 2V, I D = 0.1mA) source resistance R _S = 0.7Ωmm (at 10μA constant current to gate forward _{R S} = _{ΔV G} /
According to [Delta] I _D) maximum transconductance gm = 430mS / mm 3 terminal breakdown voltage BV _D = 16V (I _D = maximum drain voltage when changing the V _G at 0.1 mA) the cutoff frequency f _t = 70 GHz production method of the present invention For example, as compared with the conventional example 2, the gate formation after the formation of the two-stage recess is performed only by depositing and processing the gate metal, so that the process is greatly shortened and simplified. As a result, the manufacturing period is shortened, and the manufacturing cost and the manufacturing cost can be reduced.

As a structure of the semiconductor crystal layer of this HJFET, a low-concentration layer having an n-type concentration of 1 × 10 ¹⁷ cm ⁻³ and a thickness of 20 nm was inserted into the surface of an n-type AlGaAs channel layer immediately below the gate. Of the three terminals is improved. Since a lower contact layer having an n-type concentration of 1 × 10 ¹⁷ cm ⁻³ and a thickness of 20 nm is in contact with the side surface of the gate electrode 12 on the source side, an increase in source resistance due to a lower concentration of the channel surface is suppressed, and a transconductance is reduced. And a cut-off frequency. In addition, since the source side is buried in the lower contact layer 4 in this manner, an increase in drain conductance and kink phenomenon in static characteristics, frequency dispersion and pulse blunting in transient characteristics, and the like are suppressed.

If the depth of the second recess 20 exceeds 50 nm, a disconnection phenomenon in which the gate metal is separated vertically will become remarkable, so that the depth of the second recess 20 must be 50 nm or less. Further, if the depth of the second recess 20 is small, the lateral side etching can be reduced. If the side etching is small, there is wraparound in sputter deposition, and contact of the gate metal to the side surface of the lower contact layer is also ensured. The fact that the depth of the second recess 20 is 50 nm or less is the same in the embodiments described below.

Although the etching stopper layer 4 has been described as being made of AlGaAs, even a P-containing crystal such as InGaP can provide the same etching stopper with a chlorine-based and fluorine-based mixed gas.

Although the epitaxial semiconductor layer including the etching stopper layer has been described as the conductive semiconductor layer, a method of digging a layer formed by ion implantation or simply epitaxially growing is also possible.

Although WSi is used for the gate metal 9, any other material may be used as long as it produces a Schottky junction or a pn junction. For example, high melting point metal tungsten W,
Titanium Ti, molybdenum Mo, and the like, and silicides and nitrides thereof are preferable in terms of reliability, and may be aluminum Al, platinum Pt, or the like. Also, it is possible to diffuse shallow Zn into conductive carbon C as a pn junction, or into a gate metal interface. The pn junction increases the forward voltage of the diode from 0.1 to 0.
It is preferable because the voltage can be increased by 2V. (Modification of First Embodiment) Next, a modification of the manufacturing method according to the first embodiment of the present invention will be described. In the above-described first embodiment, the gate opening is narrowed by self-alignment (self-alignment) using the side wall of the insulating film. By using the side walls, minute dimensions can be formed with high precision. However, for applications that do not require high performance, the two gate openings can be formed by a photoresist process. About this 2
The steps up to the formation of the step recess will be described. 6 to 8
FIG. 4 is a cross-sectional view showing a modification of the manufacturing method according to the first embodiment of the present invention in the order of steps.

As shown in FIG. 6, an epitaxial growth layer is provided on a semiconductor substrate 1, which is a semi-insulating GaAs substrate, to isolate elements, as in the first embodiment. Using the photoresist film 25 as a mask, the upper contact layer 5 of n-type GaAs is selectively crystal-etched to expose the etching stopper layer 4 formed below the upper contact layer 5, and a first recess 19 is provided. Thereafter, the photoresist film 25 is removed by oxygen plasma and organic cleaning, and a diluted hydrochloric acid treatment is performed to remove the oxidized AlGaAs etching stop layer 4.

Next, as shown in FIG. 7, an insulating film 6 made of SiO ₂ is deposited, and the photoresist film 26 having a narrow opening located inside the first recess 19 is used as a mask to form an insulating film.
The gate opening 7 is formed in the insulating film 6 by CR dry etching.
a is formed.

Next, as shown in FIG. 8, the photoresist film 26 is removed, and the lower contact layer 3 of the n-type GaAs is selectively crystal-etched from the gate opening 7a of the insulating film 6 to form the second recess 20. Provide. As a result, a two-stage recessed semiconductor structure is formed.

The distance between the gate and the upper contact layer on the source side needs to be set wider than in the case where the side wall is used, since the alignment accuracy of exposure and the exposure of the gate opening to the concave portion are required. On the other hand, on the drain side, the exposure position of the two-step recess can be adjusted according to the application of the withstand voltage and the mutual conductance (gain) without being limited by the side wall size. Therefore, this modified example is effective especially when a high drain breakdown voltage is required for high output. (Second Embodiment) Next, a manufacturing method according to a second embodiment of the present invention will be described. 9 to 11 are cross-sectional views showing steps of a method for manufacturing a field-effect transistor according to the second embodiment of the present invention, and FIG. 12 is a plan view showing patterns of electrodes and the like. In addition, FIG.
It is a B sectional view.

The steps and conditions for forming a two-step recess structure in the conductive semiconductor layer are the same as those in the first embodiment (see FIGS. 1 to 3).

Gate opening 7 narrowed by SiO ₂ side wall 8
After the formation of the second recess 20a and the second recess 20 (see FIG. 3), as shown in FIG. 9, a Schottky lower gate metal made of WSi _0.6 having a thickness of 200 nm and a low resistance made of Au having a thickness of 600 nm are formed as shown in FIG. Is sputter deposited. A photoresist film 23 is provided so as to cover the gate opening 7 widely by 0.4 μm, two layers of gate metal are processed by Ar ion milling, and a lower gate electrode 21 of WSi and an upper gate electrode 22 of Au are provided.

Next, as shown in FIGS. 10 and 12,
A photoresist film 24 covering the center of the gate electrode and opening near the drain side is provided, and only the lower gate electrode 21 is side-etched from the drain side. Processing method is E
It is performed using SF ₆ gas by CR method dry etching,
Increase the gas pressure to 10 mtorr to enhance isotropy. Since the reaction is chemical, only WSi is selectively etched, and Au is not etched because physical sputtering or the like is suppressed. The side etching of WSi is controlled by the time, and the gate electrode WS is formed on the second recess 20 by observing the cross section of the sample.
i is set so that 0.5 μm remains as the gate length. The finishing accuracy of the gate length was 0.5 ± 0.1 μm.

Then, as shown in FIG. 11, AuGe is formed on the remaining upper contact layer 5 on both sides of the gate electrode 22.
The source electrode 13 and the drain electrode 14 are formed by the Ni ohmic alloy layer, and the HJFET of the present invention is completed. Then, to reduce the gate capacitance, the remaining S
The iO ₂ insulating film 6 is once removed with buffered hydrofluoric acid, and a thin SiO ₂ film is again deposited as a protective film with a thickness of 100 nm as a protective film, and an Au electrode wiring is formed by an air bridge method to form an amplification FET.

According to the manufacturing method of the second embodiment, 2
Since the gate formation after the step recess is formed only by the formation of the gate electrode and side etching from one side, the process is greatly shortened and simplified. As a result, the manufacturing period is shortened, and the manufacturing cost and the manufacturing cost can be reduced.

When the crystal is a compound semiconductor such as GaAs or InP, the crystal is etched by dry etching with a chlorine-based gas and hardly etched by a fluorine-based gas, so that a fluorine-based gas is used. In this embodiment, WSi is used as the metal of the lower gate electrode 21 etched by the fluorine-based gas.
Titanium Ti, molybdenum Mo, nickel Ni, carbon C
Etc., and silicides and nitrides thereof are possible.

Although Au is used as the metal of the upper gate electrode 22 which is not etched by the fluorine-based gas, aluminum Al, platinum Pt or the like may be used, or Au / Pt may be used.
Layers are also possible.

As the conductive semiconductor layer, an epitaxial growth layer including an etching stop layer has been described. However, a method of digging a layer formed by ion implantation or simply epitaxially grown as in the first conventional example is also possible. (Third Embodiment) Next, a manufacturing method according to a third embodiment of the present invention will be described. 13 to 18 are sectional views showing steps of a method for manufacturing a field-effect transistor according to the third embodiment of the present invention, and FIG. 19 is a plan view showing patterns of electrodes and the like. Note that FIG.
FIG. 4 is a sectional view taken along line C of FIG.

The steps and conditions until the formation of the first recess in the conductive semiconductor layer are the same as those of the modification of the first embodiment (see FIG. 6). That is, semi-insulating GaAs
An epitaxial growth layer is provided on a semiconductor substrate 1 as a substrate, and elements are separated. The upper contact layer 5 of n-type GaAs is selectively crystal-etched using the photoresist film 25 having a lateral length of 1.4 μm as an opening mask, and a first recess 19 is formed.
Is provided. Thereafter, the photoresist film 25 is removed by oxygen plasma and organic cleaning, and a diluted hydrochloric acid treatment is performed to remove the oxidized AlGaAs etching stop layer 4.

Next, as shown in FIG. 13, an insulating film 6 made of SiO ₂ having a thickness of 400 nm is deposited on a series of epitaxial growth layers. Using a photoresist film having an opening of 0.8 μm in width at a distance of 0.2 μm from the source side on this insulating film 6 as a mask, a parallel plate type reactive
Using CHF ₃ gas in ion etching (RIE)
The gate opening 3 is formed by leaving the insulating film 6 as thin as 80 ± 30 nm.
1 is formed, and the photoresist film is removed. The RIE has strong anisotropy but damages the crystal significantly, so that the insulating film 6 is left.

[0074] Then, as shown in FIG. 14, the SiO ₂ film thickness of 300nm is deposited, SiO ₂ in the opening by RIE
Etch until the film is as thin as 80 ± 30 nm. Then, the remaining Si is removed by low-damage ECR dry etching.
An O ₂ film is opened, and a gate opening 31 a narrowed to 0.4 μm on the side wall 33 is provided.

Next, as shown in FIG. 15, the lower contact layer 3 of the n-type GaAs is selectively crystal-etched from the gate opening 31a to provide a second recess 20. A desired etching time is set so as to reduce lateral over-etching.

Next, as shown in FIGS. 16 and 19,
A lower contact layer of n-type GaAs having a high etching rate, which is provided on a channel layer 2 having a low etching rate and serving as an etching stop layer, is provided with a photoresist film 34 covering the source side of the second recess 20 and opening the vicinity of the drain. 3 is side-etched, the second recess 20 is widened by 0.3 μm to the drain side, and the photoresist film 34 is removed. The ECR type dry etching conditions increase the isotropic property by increasing the pressure of SF ₆ gas to 10 mtorr, thereby performing side etching. The side etching is controlled by time, and is set by observing the cross section of the sample.

Next, as shown in FIG.
A Schottky gate metal made of _0.6 nm WSi _0.6 and a low-resistance gate metal made of Au having a thickness of 600 nm are sputter deposited. The gate metal WSi contacts the side surface on the source side of the lower contact layer 3 of the n-type GaAs. A photoresist film is provided so as to cover the gate opening 31a widely by 0.4 μm, two layers of gate metal are processed by Ar ion milling, and a lower gate electrode 35 of WSi and an upper gate electrode 36 of Au are provided.

Next, as shown in FIG.
AuGeN on the remaining upper contact layer 5 on both sides of
The source electrode 13 and the drain electrode 14 are formed by the ohmic alloy layer of i, and the HJFET of the present invention is completed. Thereafter, in order to reduce the gate capacitance, the remaining insulating film 6 on the surface is once removed with buffered hydrofluoric acid, and a thin SiO ₂ film is again deposited as a protective film with a thickness of 100 nm as a protective film. Wiring is formed to form an amplification FET. In FIG. 19, reference numeral 38 denotes an upper contact region.

According to the manufacturing method of the third embodiment, 2
After the step recess is formed, only the step of covering the source side of the second step recess and performing side etching on the drain side is added, so that the step is greatly shortened and simplified. As a result, the manufacturing period is shortened, and the manufacturing cost and the manufacturing cost can be reduced. (Fourth Embodiment) Next, a manufacturing method according to a fourth embodiment of the present invention will be described. 20 to 25 are sectional views showing steps of a method for manufacturing a field effect transistor according to the fourth embodiment of the present invention, and FIG. 26 is a plan view showing patterns of electrodes and the like. FIG. 25 corresponds to D in FIG.
FIG. 4 is a sectional view taken along line D.

As shown in FIG. 20, the steps and various conditions up to the formation of the first recess in the conductive semiconductor layer are the same as those in the first embodiment (see FIG. 1). That is, an epitaxial growth layer is provided on the semiconductor substrate 1, which is a semi-insulating GaAs substrate, to separate elements. This epitaxial growth layer includes a first etching stop layer 4a of n-type AlGaAs having a low etching rate and a second etching stop layer 4 of n-type AlGaAs.
And an etching stop layer 4b.

A thickness of 400 is formed on the epitaxial growth layer.
An insulating film 6 made of SiO _{2 of} nm is coated, and a gate opening 31 having a lateral length of 0.8 μm is formed in the insulating film 6.
The gate opening 31 is formed by low-damage ECR dry etching using SF ₆ gas with a photoresist film as a mask. Subsequently, the photoresist film is removed, and the upper contact layer 5 of n-type GaAs is selectively crystal-etched to provide a first recess 19. The upper contact layer 5 has a thickness of 0.1
At 0 μm, side etching is performed by 0.1 μm from the insulating film opening 31.

Next, as shown in FIGS. 21 and 26,
Provided is a photoresist film 34 covering the source side of the first recess 19 and opening the vicinity of the drain, and the n-type Ga with a high etching rate above the first etching stopper layer 4a.
The upper contact layer 5 of As is side-etched. As a result, the first recess 19 is expanded by 0.6 μm from the gate opening 31 of the insulating film 6 to the drain side. ECR type dry etching conditions are SF ₆ gas pressure of 10 mtorr.
To increase the isotropy and perform side etching. The side etching is controlled by time, and is set by observing the cross section of the sample. After that, the photoresist film 34 is removed by oxygen plasma and organic cleaning, and when the diluted hydrochloric acid treatment is performed, the oxidized Al is removed.
The GaAs etching stop layer 4a is removed.

Next, as shown in FIG. 22, a SiO ₂ film is deposited to a thickness of 300 nm, a side wall 37 is formed by low-damage ECR dry etching, and a gate opening 31a narrowed to 0.4 μm is formed. . Although it does not completely reach the inside of the drain side which has been side-etched by the deposition of the SiO ₂ film, there is no problem since there is no gap as a gate opening after the sidewall processing because it is closed in front. From the gate opening 31a, the lower contact layer 3 of n-type GaAs is formed.
Is selectively crystal-etched to provide a second recess 20. A desired etching time is set so as to reduce lateral over-etching.

Next, as shown in FIGS. 23 and 26,
A photoresist film 34 having a source side covered by the second recess 20 and an opening near the drain is provided, and n-type AlGaAs is formed.
The lower contact layer 3 of n-type GaAs having a high etching rate above the second etching stop layer 4b is side-etched. The second recess 20 is widened by 0.3 μm from the gate opening 31a of the side wall 37 to the drain side. Thereafter, the photoresist film 34 is removed.

Next, as shown in FIG.
A sputter-deposited gate metal of Schottky having a thickness of _0.6 nm of WSi _0.6 and a low-resistance gate metal of Au having a thickness of 600 nm are deposited. A photoresist film is provided so as to cover the gate opening 7 widely by 0.4 μm, two layers of gate metal are processed by Ar ion milling, and a lower gate electrode 35 of WSi and an upper gate electrode 36 of Au are provided.

Next, as shown in FIG. 25, AuGe is formed on the remaining upper contact layer 5 on both sides of the gate electrode 22.
The source electrode 13 and the drain electrode 14 are formed by the Ni ohmic alloy layer, and the HJFET of the present invention is completed. Thereafter, in order to reduce the gate capacitance, the remaining insulating film 6 on the surface is once removed with buffered hydrofluoric acid, and a thin SiO ₂ film is again deposited as a protective film to a thickness of 100 nm. It forms an amplification FET.

According to the manufacturing method of the fourth embodiment, since only the step of covering the source side and the step of side-etching the drain side are added for the two-stage recess, the steps are shortened and simplified. . As a result, the manufacturing period is shortened, and the manufacturing cost and the manufacturing cost can be reduced. Further, by applying the insulating film side wall to the gate opening and setting the depth of the second recess to 50 nm or less, disconnection which is a problem in Conventional Example 3 can be prevented.

[0088]

According to the present invention, the offset structure in which the gate is buried only on the source side in the two-stage recess shown in the conventional example 2 is obtained, so that the process is shortened and simplified. As a result, the manufacturing period is shortened, and the manufacturing cost and the manufacturing cost can be reduced.

By applying the insulating film side wall to the gate opening and setting the depth of the second recess to 50 nm or less, disconnection of the gate electrode which is a problem in the conventional example 3 can be prevented. it can.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a method of manufacturing a field-effect transistor according to a first embodiment of the present invention for each process.

FIG. 2 is a cross-sectional view illustrating a method of manufacturing the field-effect transistor according to the first embodiment of the present invention for each process.

FIG. 3 is a cross-sectional view illustrating a method of manufacturing the field-effect transistor according to the first embodiment of the present invention for each process.

FIG. 4 is a cross-sectional view showing a method of manufacturing the field-effect transistor according to the first embodiment of the present invention for each process.

FIG. 5 is a plan view showing a pattern of electrodes and the like.

FIG. 6 is a sectional view illustrating a modification of the manufacturing method according to the first embodiment of the present invention in the order of steps.

FIG. 7 is a cross-sectional view showing a modification of the manufacturing method according to the first embodiment of the present invention in the order of steps.

FIG. 8 is a cross-sectional view showing a modification of the manufacturing method according to the first embodiment of the present invention in the order of steps.

FIG. 9 is a cross-sectional view illustrating a method of manufacturing the field-effect transistor according to the second embodiment of the present invention for each process.

FIG. 10 is a cross-sectional view illustrating a method of manufacturing the field-effect transistor according to the second embodiment of the present invention for each process.

FIG. 11 is a cross-sectional view illustrating a method of manufacturing the field-effect transistor according to the second embodiment of the present invention for each process.

FIG. 12 is a plan view showing a pattern of electrodes and the like.

FIG. 13 is a cross-sectional view showing a method of manufacturing the field-effect transistor according to the third embodiment of the present invention for each process.

FIG. 14 is a cross-sectional view illustrating a method of manufacturing the field-effect transistor according to the third embodiment of the present invention for each process.

FIG. 15 is a cross-sectional view showing a method of manufacturing the field-effect transistor according to the third embodiment of the present invention for each process.

FIG. 16 is a cross-sectional view illustrating a method of manufacturing the field-effect transistor according to the third embodiment of the present invention for each step.

FIG. 17 is a cross-sectional view showing a method of manufacturing the field-effect transistor according to the third embodiment of the present invention for each step.

FIG. 18 is a cross-sectional view showing a method of manufacturing the field-effect transistor according to the third embodiment of the present invention for each step.

FIG. 19 is a plan view showing a pattern of electrodes and the like.

FIG. 20 is a cross-sectional view showing a method of manufacturing the field-effect transistor according to the fourth embodiment of the present invention for each step.

FIG. 21 is a cross-sectional view illustrating a method of manufacturing the field-effect transistor according to the fourth embodiment of the present invention for each process.

FIG. 22 is a cross-sectional view showing a method of manufacturing the field-effect transistor according to the fourth embodiment of the present invention for each process.

FIG. 23 is a cross-sectional view showing a method of manufacturing the field-effect transistor according to the fourth embodiment of the present invention for each step.

FIG. 24 is a cross-sectional view showing a method of manufacturing the field-effect transistor according to the fourth embodiment of the present invention for each step.

FIG. 25 is a cross-sectional view showing a method of manufacturing the field-effect transistor according to the fourth embodiment of the present invention for each step.

FIG. 26 is a plan view showing a pattern of electrodes and the like.

FIG. 27 is a cross-sectional view showing a manufacturing method of Conventional Example 1 for each process.

FIG. 28 is a sectional view illustrating the manufacturing method of Conventional Example 1 for each process.

FIG. 29 is a cross-sectional view showing a manufacturing method of Conventional Example 1 for each step.

FIG. 30 is a cross-sectional view showing a manufacturing method of Conventional Example 1 for each process.

FIG. 31 is a cross-sectional view showing a manufacturing method of Conventional Example 1 for each step.

FIG. 32 is a cross-sectional view showing a manufacturing method of Conventional Example 1 for each process.

FIG. 33 is a cross-sectional view showing a manufacturing method of Conventional Example 1 for each process.

FIG. 34 is a cross-sectional view showing a manufacturing method of Conventional Example 1 for each process.

FIG. 35 is a cross-sectional view showing a manufacturing method of Conventional Example 2 for each process.

FIG. 36 is a cross-sectional view showing a manufacturing method of Conventional Example 2 for each process.

FIG. 37 is a cross-sectional view showing a manufacturing method of Conventional Example 2 for each step.

FIG. 38 is a cross-sectional view showing a manufacturing method of Conventional Example 2 for each process.

FIG. 39 is a cross-sectional view showing a manufacturing method of Conventional Example 2 for each process.

FIG. 40 is a cross-sectional view showing a manufacturing method of Conventional Example 2 for each process.

FIG. 41 is a cross-sectional view showing a manufacturing method of Conventional Example 2 for each process.

FIG. 42 is a cross-sectional view showing a manufacturing method of Conventional Example 2 for each process.

FIG. 43 is a cross-sectional view showing a manufacturing method of Conventional Example 2 for each process.

FIG. 44 is a cross-sectional view showing a manufacturing method of Conventional Example 2 for each process;

FIG. 45 is a cross-sectional view showing a manufacturing method of Conventional Example 2 for each process;

FIG. 46 is a plan view showing a pattern of electrodes and the like.

FIG. 47 is a cross-sectional view showing a manufacturing method of Conventional Example 3 for each process;

FIG. 48 is a cross-sectional view showing a manufacturing method of Conventional Example 3 for each process;

FIG. 49 is a cross-sectional view showing a manufacturing method of Conventional Example 3 for each process.

FIG. 50 is a cross-sectional view showing a manufacturing method of Conventional Example 3 for each process;

FIG. 51 is a cross-sectional view for explaining a problem of the conventional example 3;

[Explanation of symbols]

1: semiconductor substrate (semi-insulating GaAs) 2: channel layer (n-type AlGaAs) 3: lower contact layer (n-type GaAs) 4: etching stop layer (n-type AlGaAs) 4a: first etching stop layer (n 4b: second etching stop layer (n-type AlGaAs) 5: upper contact layer (n-type GaAs) 6: insulating film (SiO ₂ ) 7, 7a: gate opening 8: side wall (SiO ₂ ) 9: Gate metal (WSi) 10: Gate metal (W) 11: Photoresist film 12: Gate electrode 13: Source electrode 14: Drain electrode 15: Electron transit layer (i-type InGaAs) 16: Buffer layer (i-GaAs) 17: Element Region 18: Device isolation region 19: First recess 20: Second recess 21: Lower gate electrode (WSi) 22: Upper gate electrode (Au) 3: photoresist film 24: on one side working photoresist film 25: photoresist film 26: photoresist film 31, 31a: gate opening 33: the side wall (SiO ₂₎ 34: one working photoresist film 35: Gate electrode (WSi) 36: Gate Electrode (Au) 37: Side wall (SiO ₂ ) 38: Upper contact area

──────────────────────────────────────────────────続 き Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/338 H01L 21/337 H01L 29/417 H01L 29/808 H01L 29/812

Claims (9)

(57) [Claims] (1) a step of forming a conductive semiconductor layer on a semiconductor substrate; (2) a step of digging the conductive semiconductor layer to provide a first recess; and (3) depositing an insulating film. Forming a gate opening located inside the first recess by using the method described above. (4) digging the conductive semiconductor layer further from the gate opening and suppressing lateral side etching to form a second opening. (5) depositing a Schottky gate metal and a low-resistance gate metal as a gate electrode material on the entire surface and in the second recess so as to cover the source side from the center of the gate opening. A gate electrode material on the drain side in the second recess is removed by using the photoresist film as a mask to form a gate only near the source side including the source side region of the gate opening. Forming a gate electrode while leaving the electrode material; and (6) forming ohmic source and drain electrodes on regions of the conductive semiconductor layer that are not dug on both sides of the gate electrode. A method for manufacturing a field effect transistor, comprising: performing the steps in the order of (1) to (6). 2. A process for forming a conductive semiconductor layer on a semiconductor substrate, a process for forming a first recess by digging the conductive semiconductor layer, and a process for depositing an insulating film. Forming a gate opening located inside the first recess by the step (4) further digging the conductive semiconductor layer from the gate opening and suppressing lateral side etching in the second step. (5) forming a lower gate electrode and an upper gate electrode with two types of gate electrode materials having different workabilities so as to cover the inside of the second recess, and (6) forming the lower layer. The gate electrode and the source side of the upper gate electrode are protected, and only the lower gate electrode is side-etched from the drain side to the middle of the second recess so that the lower gate electrode is left only in the vicinity of the source side. And (7) forming ohmic source and drain electrodes on regions of the conductive semiconductor layer that are not dug on both sides of the lower gate electrode and the upper gate electrode, and (7) To (7). A method for manufacturing a field-effect transistor, comprising: 3. The step (6) is performed by processing by dry etching, wherein a gate electrode material of the lower gate electrode is a substance having a high etching rate in the dry etching, and a gate electrode material of the upper gate electrode. 3. The method according to claim 2, wherein the material is a substance having a low etching rate in the dry etching. 4. A fluorine-based gas is used for the dry etching, and a gate electrode material of the lower gate electrode is WSi, W,
A material selected from the group consisting of Ti, Mo, Ni, C, and a silicide or nitride thereof, wherein the gate electrode material of the upper gate electrode is Au, Al,
The method for manufacturing a field-effect transistor according to claim 3, wherein the material is selected from the group consisting of Pt. 5. A step of: (1) forming a conductive semiconductor layer including an etching stop layer having a low etching rate on a semiconductor substrate; and (2) providing a first recess by digging the conductive semiconductor layer. (3) depositing an insulating film to form a gate opening located inside the first recess; and (4) further digging the conductive semiconductor layer from the gate opening to etch away. Providing a second recess by stopping at a time and suppressing lateral side etching; and (5) protecting the source side of the second recess and providing a high etching rate above the etching stop layer. (6) a step of side-etching the drain side of the conductive semiconductor layer to extend the second recess to the drain side;
Forming a gate electrode so as to be buried immediately below the gate opening; and (7) forming ohmic source and drain electrodes on a region of the conductive semiconductor layer which is not dug on both sides of the gate electrode. And performing the steps in the order of (1) to (7). 6. The method according to claim 1, wherein the gate opening is formed by depositing an insulating film and then performing etching to provide a sidewall of the insulating film in the first recess. A method for manufacturing a field-effect transistor according to one item. 7. The gate opening is formed by depositing an insulating film and etching using a resist film having an opening located inside the first recess as a mask. A method for manufacturing a field-effect transistor according to claim 1. 8. A step of: (1) forming a conductive semiconductor layer including first and second etching stop layers having a low etching rate on a semiconductor substrate; and (2) depositing an insulating film to form a first gate. Providing an opening; and (3) providing a first recess by digging the conductive semiconductor layer from the first gate opening and stopping at a first etching stop layer.
(4) Protecting the source side of the first recess, side-etching the conductive semiconductor layer above the first etching stop layer with a high etching rate to the drain side to spread the first recess to the drain side. (5) providing a narrowed second gate opening by providing a sidewall of an insulating film inside the first gate opening and the first recess;
(6) further digging the conductive semiconductor layer from the second gate opening, stopping at the second etching stop layer, and providing a second recess by suppressing lateral side etching; (7) Protecting the source side of the second recess, and side-etching the conductive semiconductor layer having a high etching rate above the second etching stop layer toward the drain side with a width smaller than the etching width of the first recess. And (8) forming a gate electrode so as to fill immediately below the second gate opening, and (9) digging both sides of the gate electrode. Forming an ohmic source electrode and a drain electrode on a region of the conductive semiconductor layer which is not embedded, wherein the step is performed in the order of (1) to (9). Method for producing a register. 9. The method for manufacturing a field-effect transistor according to claim 1, wherein the second recess is formed to have a depth of 50 nm or less.