JP3380139B2 - High electron mobility transistor and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a method of manufacturing a high electron mobility transistor (HEMT). More specifically, AlInAs / GaIn formed on the InP substrate
As-related HEMT.

[0002]

2. Description of the Related Art In recent years, AlGa has been used as an element for a power MMIC (monolithic microwave IC) for millimeter waves.
Instead of As / GaAs HEMT, AlInAs / GaInAs with higher operating frequency and higher cutoff frequency
The system HEMT is drawing attention. However, this system HE
Although MT has excellent high frequency characteristics, it is important to reduce the gate-source resistance Rs when attempting to achieve higher performance.

It is easily conceivable to increase the carrier concentration in order to reduce the resistance Rs between the gate and the source, but when the carrier concentration is increased, the capacitance Cgd between the gate and the drain becomes large, and the high frequency characteristics are impaired, and , D
Also in the C characteristic, there are problems that the gate leakage current becomes large and the breakdown voltage decreases.

Further, a method of adopting an asymmetric gate structure in which the distance between the gate and the drain is increased and the distance between the gate and the source is reduced can be easily considered.

12 to 17 show an asymmetric gate structure A.
It is a schematic sectional drawing which shows an example of the manufacturing process of 1GaAs / GaAs type HEMT.

As shown in FIG. 12, n-type semi-insulating Ga is used.
The following layers are epitaxially grown on the surface of the As substrate 21 by, for example, the MBE method. Undoped AlGa
As buffer layer 22, undoped GaAs channel layer 2
3, n-type AlGaAs Schottky layer 24, n-type GaAs
Each layer is the contact layer 25 and the like.

Next, as shown in FIG. 13, in order to isolate the element, the growth layer on the surface of the unnecessary portion of the element is etched to expose the GaAs substrate 21.

Next, as shown in FIG. 14, in order to form an ohmic electrode, a source electrode 26 and a drain electrode 27 made of AuGe / Ni / Au are formed through a normal photo process, a vapor deposition process and an alloy process. , N-type GaAs contact layer 25.

Next, as shown in FIG. 15, in order to form a Schottky electrode, a gate electrode forming pattern is formed by a photolithography process by a normal process, and the n-type GaAs contact layer 25 is etched by using a photoresist as a mask and vapor-deposited. Gate electrode 2 made of Ti / Pt / Au through the steps
9 is formed on the Schottky layer 24.

Next, as shown in FIG. 16, a pattern having an opening at the drain end of the gate is formed with a photoresist 15, and the n-type GaAs contact layer 25 immediately below the drain end of the gate is etched, as shown in FIG. HE where the gate-drain distance is longer than the gate-source distance
MT is configured.

However, due to the variation in the recess and the alignment of the Schottky electrode (gate electrode) in the current process technology, a large variation in the resistance Rs between the gate and the source occurs, resulting in a variation in the high frequency characteristic.
The high frequency characteristics of C cannot be improved.

From these facts, it is very important to achieve a low gate-source resistance Rs and to keep the gate-drain capacitance Cgd and the gate leakage current low in order to improve the performance of the HEMT. It can be seen that it is.

Achieving a low gate-source resistance Rs,
Further, as an attempt to suppress the gate-drain capacitance Cgd and the gate leakage current to a low level and improve the high frequency characteristics, for example, in the case of AlGaAs / GaAs HEMT, there is a method described in Japanese Patent Application Laid-Open No. 7-86309.

In FIG. 16, a photoresist 15 is applied to the surface including the gate electrode 29 and patterned, and the photoresist and the gate electrode 29 are used as a mask for n.
The type GaAs contact layer 25 is etched. At this time, it is necessary to etch the n-type GaAs contact layer 25 without etching the n-type AlGaAs Schottky layer 24. For this purpose, the etching rate of GsAs is set to about 100 times or more the etching rate of AlGaAs (JP-A-7-86309 [00]).
21]). The etching of the n-type GaAs contact layer 25 reduces the electron concentration of the channel layer at the drain end of the gate. As a result, a low gate-source resistance Rs is achieved and a gate-drain capacitance C is obtained.
gd, gate leak current is kept low.

[0015]

Problems to be Solved by the Invention AlInAs / GaI
In the nAs system, if the same process as described above is applied, the etching rate of GaInAs is set to AlI.
It must be 100 times or more the etching rate of nAs. However, in this system of dry etching, AlG
Unlike the aAs / GaAs system, such a selection ratio has not been obtained. Therefore, it is difficult to control the etching time because part of AlInAs is etched, and the dry etching of this system lacks stability.

Further, in our experiments, wet etching using a citric acid-based etching solution tends to cause a large difference in finish depending on temperature and time.
It was found that this is a method with poor controllability in a process that requires uniformity and reproducibility.

Therefore, in the AlInAs / GaInAs system, it is necessary to reduce the electron concentration of the channel layer at the drain end of the gate by a method other than etching the n-type GaInAs contact layer.

Further, conventionally, AlInAs / GaInA has been used.
In the s-based HEMT, oxygen or fluorine is mixed into the semiconductor layer and then heat-treated to produce n ^- A
It is known that the electron concentration of the lInAs layer decreases, and efforts have been made to minimize the mixing of oxygen or fluorine. However, the conditions for controlling the mixing have not been examined.

[0019]

Means for Solving the Problems The present inventor has clarified the mixing route of oxygen or fluorine by some experiments. Then, according to the experiment, oxygen or fluorine was intentionally mixed, and then heat treatment was performed to obtain n ^- A with good controllability.
The conditions for reducing the electron concentration of the lInAs layer have been found.

In the AlInAs / GaInAs HEMT epitaxially grown on the semiconductor substrate, an oxygen or fluorine introduction layer is formed in the electron supply layer only between the gate and drain, and heat treatment is performed. The heat treatment when introducing oxygen is 220 ° C. to 480 ° C., and the heat treatment temperature when introducing fluorine is 350 ° C. to 480 ° C.

By incorporating such a process of introducing oxygen or fluorine into the HEMT manufacturing process, n ^-- A
By reducing the electron concentration in the lInAs electron supply layer, the electron concentration in the channel layer is also reduced, and
A low gate-drain capacitance can be secured while maintaining the source-source resistance.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION First, a first embodiment for introducing oxygen will be described.

As shown in FIG. 1, semi-insulation by MBE method
On the crystalline InP substrate 1 with a thickness of 250 nm
A buffer layer 2 made of nAs is grown, and 20 is grown thereon.
Channel layer 3 made of undoped GaInAs having a thickness of nm
Is grown, and 5 nm thick Si with a thickness of 5 nm is further grown thereon.
¹⁸cm^-3Better than doped Si-doped AlInAs
Of the electron supply layer 4 having a thickness of 20 nm is grown on the electron supply layer 4.
A Schottky layer 5 made of doped AlInAs is grown.
On top of it, and add Si with a thickness of 20 nm to 5 × 10¹⁸cm ^-3Doe
Ping Si-doped GaInAs contacts
Grow layer 6.

Next, as shown in FIG. 2, in order to isolate the device, an unnecessary portion of the device is formed by etching a growth layer on the surface,
The InP substrate 1 is exposed.

Next, as shown in FIG. 3, a source electrode 7 and a drain electrode 8 made of AuGe / Ni / Au are formed through a normal photo process, a vapor deposition process and an alloy process in order to form an ohmic electrode. To do.

Next, as shown in FIG. 4, in order to form a Schottky electrode, a gate electrode forming pattern is formed by a photolithography process by a normal process, and the Si-doped GaInAs contact layer 6 on the surface of the growth layer is formed by the photoresist. Etching with a mask as a mask, through the vapor deposition process, Ti / Pt
Of the gate electrode 9 made of / Au with undoped AlInA
It is formed on the s-Schottky layer 5.

Next, as shown in FIG.
5, a pattern having an opening is formed at the drain end of the gate, and Si-doped AlInAs immediately below the drain end of the gate is formed.
In order to reduce the electron concentration in the electron supply layer 4, oxygen is introduced into the Si-doped AlInAs electron supply layer 4 by using an ozone ashing device generally used in the semiconductor process (substrate temperature 70 ° C., atmospheric pressure). , 15 minutes). Then, the photoresist 15 is peeled off, and heat treatment is performed at 400 ° C. for 5 minutes to form the oxygen-introduced layer 10 in the Si-doped AlInAs electron supply layer 4.
The electron concentration in the As electron supply layer 4 is reduced.

FIG. 6 is a schematic cross-sectional view of the HEMT after removing the photoresist layer. A HEMT without ozone ashing treatment was also produced in the same wafer at the same time. As a result, the resistance between the gate and the source is 0.2 Ω / mm, there is no difference between the presence and absence of the ozone ashing treatment, and the capacitance between the gate and the drain is 21 ohms / mm.
Although it was 1 fF / mm, it decreased to 156 fF / mm by the ozone ashing treatment. Further, the gate-drain breakdown voltage (Idg = 10 mA / mm) was 7 V without ozone ashing treatment, but was improved to 21 V by ozone ashing treatment, resulting in a low gate-drain capacitance C.
A HEMT having gd and a high gate-drain breakdown voltage was obtained.

In the step of introducing oxygen in FIG. 5, in addition to the method of exposing to ozone as described above, a method of exposing to oxygen plasma is possible, and a parallel plate oxygen ashing device and a barrel type oxygen which are generally used in a semiconductor process are available. An ashing device and a remote plasma type oxygen ashing device can be used.

The temperature required for the above heat treatment is 220 to 4
It is 80 ° C. If it is lower than 220 ° C., the effect of the introduced oxygen to lower the electron concentration is insufficient, and if it is 480 ° C. or higher, the interface of the heterojunction of the AlInAs / GaInAs layer deteriorates due to thermal diffusion, and the characteristics deteriorate.

More preferably, it is 300 to 450 ° C. If the temperature is lower than 300 ° C., the recovery of damage due to oxygen introduction is slow and the processing time is long, and if the temperature is 450 ° C. or higher, the diffusion of Si donors in the Si-doped AlInAs layer starts to deteriorate the device characteristics.

If the damage is not sufficiently recovered, the portion into which oxygen is introduced serves as a current path for the gate leak current, and the breakdown voltage between the gate and the drain deteriorates. From this, when the parallel plate oxygen ashing device which causes relatively large damage or the barrel type ashing device to be described later is used, the heat treatment is preferably 330 ° C. or higher.

The second embodiment described below is another example of introducing oxygen, and is different from the first embodiment in that
The growth method of the epitaxial layer is the MOCVD method, the barrel type oxygen ashing apparatus is used to introduce oxygen, the heat treatment conditions and the like.

First, semi-insulating InP is formed by MOCVD.
On the substrate, a buffer layer of undoped AlInAs having a thickness of 250 nm and undoped GaInAs having a thickness of 20 nm are formed.
Channel layer consisting of 5 nm thick Si of 5 × 10 ¹⁸ cm
^An electron supply layer made of ^-3 doped Si-doped AlInAs, a Schottky layer made of undoped AlInAs having a thickness of 20 nm, and a contact layer made of Si-doped GaInAs doped with Si of 5 nm 10 ¹⁸ cm ^-3 are grown. This is the same as in FIG. 1, so the illustration is omitted.

Then, the growth layer on the surface of the unnecessary portion of the element for element isolation is etched to expose the InP substrate. This is the same as that in FIG. 2, so the illustration is omitted.

Next, in order to form an ohmic electrode, AuGe / N is subjected to a usual photo process, vapor deposition and alloy process.
A source electrode and a drain electrode made of i / Au are formed. This is the same as that in FIG. 3, so the illustration is omitted.

Next, in order to form a Schottky electrode,
A gate electrode formation pattern is formed by a photo process by a normal process, the Si-doped GaInAs contact layer on the surface of the growth layer is etched by using the photoresist as a mask, and a gate electrode made of Ti / Pt / Au is undoped AlInAs through a vapor deposition process. It is formed on the Schottky layer. This is the same as in FIG. 4, so the illustration is omitted.

Next, as shown in FIG. 7, a pattern having an opening at the drain end of the gate is formed with a photoresist, and Si-doped AlInAs immediately below the drain end of the gate is formed.
In order to reduce the electron concentration in the electron supply layer 4, a barrel-type oxygen ashing device generally used in a semiconductor process is used, and Si-doped AlI is formed by oxygen plasma.
Oxygen is introduced into the nAs electron supply layer 4 (substrate temperature 10
0 ° C, oxygen pressure 0.7 Torr, RF power 100W, 5
Processing for minutes). After that, the photoresist is peeled off, and 350 ° C
By performing a heat treatment for 5 minutes, an oxygen introduction layer is formed,
The electron concentration in the Si-doped AlInAs electron supply layer 4 is reduced. This sectional view is similar to that of FIG.

A HEMT without the oxygen ashing process was also produced in the same wafer at the same time. As a result, the resistance between the gate and the source was 0.2 Ω / mm, and there was no difference between the presence and absence of the oxygen ashing treatment, and the capacitance between the gate and the drain was 211 fF / mm when the oxygen ashing treatment was not performed. It decreased to 113 fF / mm by the ashing process. In addition, the gate-drain breakdown voltage (Idg = 10
The current (mA / mm) was 7 V without the oxygen ashing treatment, but was improved to 23 V by the oxygen ashing treatment, and a HEMT having a low gate-drain capacitance Cgd and a high gate-drain breakdown voltage was obtained.

In FIG. 11, a barrel type oxygen ashing apparatus is used, the substrate temperature is 100 ° C., the oxygen pressure is 0.7 Torr, and the RF is used.
The oxygen profile analyzed by SIMS (secondary ion mass spectrometer) when heat-treated at a power of 100 W for 5 minutes and then at 330 ° C. for 1 minute is shown. As is clear from the figure, the presence of the N ^-- AlInAs layer 230-2
It can be seen that an oxygen introduction layer of about 1E18 cm ⁻³ is formed near 80 Å. Also, similarly treated n ^- Al
The electron concentration of the InAs electron supply layer was 7E from the hole measurement.
It was confirmed that was reduced from 18cm ^-3 to 5E18cm ^-3.

The third embodiment is one in which fluorine is introduced. Similar to the first and second embodiments, the buffer layer, the channel layer, the electron supply layer, the Schottky layer, and the contact layer having the same thickness as those in the above-described embodiments are formed on the semi-insulating InP substrate by the MBE method. Grow.

Next, as in the first and second embodiments, the growth layer on the surface of the unnecessary portion of the element is etched for element isolation to expose the InP substrate.

Then, similarly to the above-mentioned embodiment, the source electrode and the drain electrode made of AuGe / Ni / Au are formed through the usual photo process, vapor deposition process and alloy process for forming the ohmic electrode.

Next, in the same manner as in the above-described embodiment, in order to generate the Schottky electrode, a gate electrode forming pattern is formed by a photolithography process by a normal process, and the contact layer on the growth layer surface is etched by using the photoresist as a mask. Then, a gate electrode made of Ti / Pt / Au is formed on the Schottky layer through a vapor deposition process.

Next, as shown in FIG.
5, a pattern having an opening is formed at the drain end of the gate, and Si-doped AlInAs immediately below the drain end of the gate is formed.
In order to reduce the electron concentration in the electron supply layer 4, it is rinsed with hydrofluoric acid for 2 minutes. By sufficiently adsorbing fluorine on the surface of the epitaxial film, washing with water and drying, the photoresist 15 is peeled off, and heat treatment is performed at 400 ° C. for 15 minutes to form a fluorine introduction layer 11 in the Si-doped AlInAs electron supply layer 4, The electron concentration in the doped AlInAs electron supply layer 4 is reduced. FIG. 9 is a sectional view thereof. The oxygen introduction layer 10 of FIG. 6 becomes the fluorine introduction layer 11.

H without hydrofluoric acid rinsing in the same wafer
EMT was also produced at the same time. As a result, the resistance between the gate and the source was 0.2 Ω / mm, there was no difference between the presence and absence of the hydrofluoric acid rinse treatment, and the capacitance between the gate and the drain was 211 fF / mm without the hydrofluoric acid rinse treatment. , And decreased to 134 fF / mm by the hydrofluoric acid rinse treatment. In addition, the breakdown voltage between the gate and the drain (Idg = 10 mA / m
When m) was not subjected to the hydrofluoric acid rinse treatment, it was increased from 7 V to 18 V by the hydrofluoric acid rinse treatment, and a HEMT having a high gate-drain breakdown voltage was obtained.

In the case of introducing fluorine, the temperature required for the heat treatment is 350 to 480 ° C. If the temperature is lower than 350 ° C, the effect of the introduced fluorine to reduce the electron concentration is insufficient, and 4
AlInAs / GaInA due to thermal diffusion above 80 ° C
The boundary surface of the heterojunction of the s layer deteriorates, and the characteristics deteriorate. More preferably, it is 380-450 degreeC.

If the temperature is lower than 380 ° C., it takes a long time to introduce fluorine, and if the temperature is 450 ° C. or higher, Si-doped AlInAs is used.
Diffusion of Si donors in the layer starts, deteriorating device characteristics.

The amount of decrease in the electron concentration in the Si-doped AlInAs layer can be arbitrarily set by using the rinse time of hydrofluoric acid, the heat treatment temperature, and the treatment time as parameters.

The fourth embodiment is another embodiment of introducing fluorine. The difference from the third embodiment lies in the epitaxial layer growth method and the fluorine introduction method.

First, semi-insulating InP is formed by MOCVD.
A buffer layer, a channel layer, an electron supply layer, a Schottky layer, and a contact layer similar to those in the first and second embodiments are grown on the substrate.

Next, as in the first and second embodiments, the growth layer on the surface of the unnecessary portion of the element is etched for element isolation to expose the InP substrate.

Next, similarly to the first and second embodiments, a source electrode and a drain electrode made of AuGe / Ni / Au are formed through the usual photo process, vapor deposition process and alloy process in order to form an ohmic electrode. To do.

Next, as in the first and second embodiments,
In order to form a Schottky electrode, a gate electrode formation pattern is formed by a photo process in a normal process, a contact layer on the surface of the growth layer is etched by using the photoresist as a mask, and a gate made of Ti / Pt / Au is formed through a vapor deposition process. The electrode 9 is formed on the Schottky layer.

Next, as shown in FIG. 10, a pattern having an opening at the drain end of the gate is formed in the photoresist 15, and Si-doped AlIn immediately below the drain end of the gate is formed.
In order to reduce the electron concentration in the As electron supply layer 4, fluorine is introduced into the Si-doped AlInAs electron supply layer 4 by CF ₄ plasma treatment using a barrel-type plasma treatment apparatus generally used in semiconductor processes. (Substrate temperature 100 ° C, Fluorine pressure 0.4 Torr, RF power 100
W for 5 minutes) to form the fluorine-introduced layer 11, and then the same heat treatment as in the above-mentioned embodiment is performed. This reduces the electron concentration in the Si-doped AlInAs electron supply layer 4. Its sectional view is similar to that of FIG.

HEMTs without CF ₄ plasma treatment were also prepared in the same wafer at the same time. As a result, the resistance between the gate and the source was 0.2 Ω / mm, there was no difference between the presence and absence of the CF ₄ plasma treatment, and the capacitance between the gate and the drain was 211 fF / mm without the CF ₄ plasma treatment.
It was reduced to 173 fF / mm by CF ₄ plasma treatment. In addition, breakdown voltage between gate and drain (Idg = 10 mA
/ Mm) was 7 V without the CF ₄ plasma treatment, but was improved to 16 V by the CF ₄ plasma treatment, and a HEMT with a low gate-drain capacitance Cgd and a high gate-drain breakdown voltage was obtained.

For introducing fluorine, in addition to exposure to CF ₄ plasma, CHF ₃ , CH ₂ F ₂ , C ₃ F ₈ and SF
_The method of exposing to plasma in any of ₆ can be used, and a parallel plate plasma apparatus and a remote plasma apparatus generally used in the semiconductor process can be used.

The amount of decrease in the electron concentration in the Si-doped AlInAs layer can be arbitrarily set by using the fluorine compound gas species, the partial pressure of the gas, and the plasma processing time as parameters.

[0059]

As described above, according to the present invention, it is possible to provide a HEMT capable of operating at a high current density while ensuring a high gate-drain breakdown voltage, and a method for manufacturing the HEMT.
Contributing to the development of MMICs such as power amplifiers using

[Brief description of drawings]

FIG. 1 is a schematic sectional view of a step of the first embodiment of the present invention.

FIG. 2 is a schematic sectional view of a step of the first embodiment of the present invention.

FIG. 3 is a schematic sectional view of a step of the first embodiment of the present invention.

FIG. 4 is a schematic sectional view of a step of the first embodiment of the present invention.

FIG. 5 is a schematic sectional view of a step of the first embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view of the finished product of the first embodiment of the present invention.

FIG. 7 is a schematic sectional view of a step of the second embodiment of the present invention.

FIG. 8 is a schematic sectional view of a step of the third embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view of the finished product of the third embodiment of the present invention.

FIG. 10 is a schematic sectional view of a step of the fourth embodiment of the present invention.

FIG. 11 is an SIMS profile diagram of an example in which an oxygen introduction layer is provided.

FIG. 12 is a schematic cross-sectional view of one step of a conventional HEMT.

FIG. 13 is a schematic cross-sectional view of one step of manufacturing a conventional HEMT.

FIG. 14 is a schematic cross-sectional view of one step of manufacturing a conventional HEMT.

FIG. 15 is a schematic cross-sectional view of one step of manufacturing a conventional HEMT.

FIG. 16 is a schematic cross-sectional view of one step of manufacturing a conventional HEMT.

FIG. 17 is a schematic cross-sectional view of an example of a conventional HEMT.

[Explanation of symbols]

1 Semi-insulating InP substrate 2 buffer layers 3 channel layers 4 Electron supply layer 5,24 Schottky layer 6 Contact layer 7,26 Source electrode 8,27 drain electrode 9,29 Gate electrode 10 Oxygen introduction layer 11 Fluorine introduction layer 15 photoresist 21 Semi-insulating GaAs substrate 22 Undoped AlGaAs buffer layer 23 Undoped GaAs channel layer 24 n-type AlGaAs Schottky layer 25 n-type GaAs contact layer

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/338 H01L 29/778 H01L 29/812 H01L 21/265

Claims (15)

(57) [Claims] 1. An AlInAs / GaInAs high electron mobility transistor epitaxially grown on a semiconductor substrate, wherein an oxygen introduction layer is present only in the electron supply layer between the gate and drain of the high electron mobility transistor. Transistor. 2. An AlInAs / GaInAs high electron mobility transistor epitaxially grown on a semiconductor substrate, wherein a fluorine-introduced layer is present only in the electron supply layer between the gate and drain of the high electron mobility transistor. Transistor. 3. An undoped A formed on an InP substrate.
lInAs layer, formed directly on the undoped AlInAs layer
Undoped GaInAs layer, said undoped GaI
Si-doped AlInAs electrode formed on nAs layer
3. The method according to claim 1 or 2, characterized by having a feed layer.
High electron mobility transistor. 4. In an AlInAs / GaInAs high electron mobility transistor epitaxially grown on a semiconductor substrate , electrons are supplied only between its gate and drain.
A method of manufacturing a high electron mobility transistor, which comprises reducing the electron concentration of an electron supply layer only between the gate and drain by introducing oxygen into the layer and performing heat treatment. 5. An undoped A formed on an InP substrate.
lInAs layer, formed directly on the undoped AlInAs layer
Undoped GaInAs layer, said undoped GaI
Si-doped AlInAs electrode formed on nAs layer
AlInAs / GaInAs system high electron transfer having a supply layer
Degree transistor, only between its gate and drain
By introducing oxygen into the electron supply layer of
Electron concentration in the electron supply layer only between the gate and drain
High electron mobility transistor characterized by reducing
Manufacturing method. 6. The method according to claim 4, wherein oxygen is introduced by exposing the surface of the semiconductor substrate to ozone.
A method for manufacturing the high electron mobility transistor described. 7. The method according to claim 4, wherein oxygen is introduced by subjecting the surface of the semiconductor substrate to oxygen plasma treatment.
Or a method of manufacturing a high electron mobility transistor according to item 5 . 8. The heat treatment after the introduction of oxygen is performed at 220 ° C. to 4 ° C.
It is 80 degreeC , The manufacturing method of the high electron mobility transistor of Claim 4-6 or 7 characterized by the above-mentioned. 9. In an AlInAs / GaInAs high electron mobility transistor epitaxially grown on a semiconductor substrate , electrons are supplied only between its gate and drain.
A method for manufacturing a high electron mobility transistor, which comprises reducing the electron concentration of an electron supply layer only between the gate and the drain by introducing fluorine into the layer and performing heat treatment. 10. An undoped substrate formed on an InP substrate
AlInAs layer, formed directly on the undoped AlInAs layer
Formed undoped GaInAs layer, the undoped Ga layer
Si-doped AlInAs electrons formed on the InAs layer
AlInAs / GaInAs system high electron transfer with supply layer
In the mobility transistor, between its gate and drain
Introducing fluorine into the electron supply layer
The electrons in the electron supply layer only between the gate and drain
High electron mobility transformer characterized by decreasing concentration
Method of manufacturing the transistor. 11. The method of manufacturing a high electron mobility transistor according to claim 9, wherein fluorine is introduced by rinsing with hydrofluoric acid and heat treatment. 12. Fluorine is introduced by exposing it to plasma of a fluorine compound gas.
9. A method of manufacturing a high electron mobility transistor according to 9, 10, or 11 . 13. The method for manufacturing a high electron mobility transistor according to claim 12, wherein the fluorine compound is CF ₄ . 14. The fluorine compound is CHF ₃ , CH
13. The method for manufacturing a high electron mobility transistor according to claim 12, wherein the method is any one of ₂ F ₂ , C ₃ F ₈ and SF ₆ . 15. The heat treatment temperature after the introduction of fluorine is 350.
Claim, characterized in that ° C. is 480 ° C. from 9-13
15. The method for manufacturing a high electron mobility transistor according to item 14 .