TW202326824A - Method of manufacturing normally-off gallium nitride device - Google Patents
Method of manufacturing normally-off gallium nitride device Download PDFInfo
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 209
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 187
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 230000004888 barrier function Effects 0.000 claims abstract description 48
- 238000005468 ion implantation Methods 0.000 claims abstract description 42
- 239000000463 material Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 30
- 239000002019 doping agent Substances 0.000 claims description 21
- 238000002955 isolation Methods 0.000 claims description 14
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 12
- 239000011575 calcium Substances 0.000 claims description 12
- 239000011777 magnesium Substances 0.000 claims description 12
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- OYPRJOBELJOOCE-UHFFFAOYSA-N Calcium Chemical compound [Ca] OYPRJOBELJOOCE-UHFFFAOYSA-N 0.000 claims description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 6
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 6
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 claims description 6
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 claims description 6
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 claims description 6
- 229910052786 argon Inorganic materials 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 229910052790 beryllium Inorganic materials 0.000 claims description 6
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052791 calcium Inorganic materials 0.000 claims description 6
- 229910052799 carbon Inorganic materials 0.000 claims description 6
- 239000001307 helium Substances 0.000 claims description 6
- 229910052734 helium Inorganic materials 0.000 claims description 6
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 6
- 239000001257 hydrogen Substances 0.000 claims description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims description 6
- 229910052749 magnesium Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 229910052711 selenium Inorganic materials 0.000 claims description 6
- 239000011669 selenium Substances 0.000 claims description 6
- 229910052717 sulfur Inorganic materials 0.000 claims description 6
- 239000011593 sulfur Substances 0.000 claims description 6
- 229910052714 tellurium Inorganic materials 0.000 claims description 6
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 238000005530 etching Methods 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 238000000137 annealing Methods 0.000 description 8
- 230000005533 two-dimensional electron gas Effects 0.000 description 6
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000000407 epitaxy Methods 0.000 description 3
- 238000001451 molecular beam epitaxy Methods 0.000 description 3
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
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Abstract
Description
本發明是有關於一種常關型（或稱E-mode）氮化鎵元件技術，且特別是有關於一種常關型氮化鎵元件的製造方法。The present invention relates to a normally-off (or E-mode) gallium nitride device technology, and in particular to a manufacturing method for a normally-off gallium nitride device.
近年來，以III-V族化合物半導體為基礎的高電子移動率晶體電晶體（HEMT）元件因為其低阻值、高崩潰電壓以及快速開關切換頻率等特性，在高功率電子元件領域被廣泛地應用。一般來說，HEMT元件可分為常開型電晶體元件以及常關型電晶體元件。In recent years, high electron mobility crystal transistor (HEMT) elements based on III-V compound semiconductors have been widely used in the field of high-power electronic components because of their low resistance, high breakdown voltage, and fast switching frequency. application. In general, HEMT devices can be classified into normally-on transistor devices and normally-off transistor devices.
常開型電晶體元件要關斷元件必須加負偏壓，因此會增加閘極驅動設計的複雜性，而且容易發生誤導通，而衝擊電路穩定性和安全性。因此，常關型HEMT元件目前受到業界相當大的關注。The normally-on transistor element must be negatively biased to turn off the element, which will increase the complexity of the gate drive design, and it is prone to false conduction, which will affect the stability and safety of the circuit. Therefore, the normally-off HEMT device is currently attracting considerable attention from the industry.
近來，P-GaN常關型HEMT元件已成為各方研究的重點。這種氮化鎵元件的製造流程一般是在AlGaN障壁層上利用MOCVD磊晶成長P-GaN層，再利用蝕刻的方式移除閘極區域以外的P-GaN層。Recently, P-GaN normally-off HEMT components have become the focus of various researches. The manufacturing process of this gallium nitride device is generally to use MOCVD epitaxy to grow a P-GaN layer on the AlGaN barrier layer, and then use etching to remove the P-GaN layer outside the gate region.
然而，因為P-GaN層是一種不易蝕刻的材料，所以在利用蝕刻的方式移除P-GaN層的過程，很難控制蝕刻參數，且容易使AlGaN障壁層受到損害，導致2DEG受到影響。However, because the P-GaN layer is a material that is not easily etched, it is difficult to control the etching parameters during the process of removing the P-GaN layer by etching, and the AlGaN barrier layer is easily damaged, resulting in the 2DEG being affected.
本發明提供一種常關型氮化鎵元件的製造方法，不需要蝕刻移除部分P-GaN層的步驟，即可在預設區域內形成P-GaN層，並藉此防止障壁層表面受到損害。The invention provides a method for manufacturing a normally-off gallium nitride element, which can form a P-GaN layer in a predetermined area without etching and removing part of the P-GaN layer, thereby preventing the surface of the barrier layer from being damaged .
本發明的一種常關型氮化鎵元件的製造方法，包括於一基板上形成通道層，於所述通道層上形成障壁層，於所述障壁層上形成氮化鎵層，其中所述氮化鎵層的材料為P型氮化鎵（P-GaN）或未摻雜氮化鎵（undoped GaN，又稱u-GaN）。所述氮化鎵層具有一預設區域。然後，根據氮化鎵層的材料種類，利用選擇性離子植入，使所述預設區域內的氮化鎵層為P型氮化鎵，且所述預設區域以外的氮化鎵層為N型氮化鎵層、隔離區或未摻雜氮化鎵層。A method for manufacturing a normally-off gallium nitride element of the present invention includes forming a channel layer on a substrate, forming a barrier layer on the channel layer, and forming a gallium nitride layer on the barrier layer, wherein the nitrogen The gallium nitride layer is made of P-type gallium nitride (P-GaN) or undoped gallium nitride (undoped GaN, also known as u-GaN). The gallium nitride layer has a predetermined area. Then, according to the material type of the gallium nitride layer, using selective ion implantation, the gallium nitride layer in the predetermined area is made of p-type gallium nitride, and the gallium nitride layer outside the predetermined area is N-type GaN layer, isolation region or undoped GaN layer.
在本發明的一實施例中，上述氮化鎵層的材料為P型氮化鎵，則對預設區域以外的氮化鎵層進行選擇性離子植入，並且所述選擇性離子植入使用的摻質包括硫(S)、矽(Si)、硒(Ce)、碲(Te)或氧(O)，以使所述預設區域以外的氮化鎵層變成所述N型氮化鎵層。In an embodiment of the present invention, the material of the gallium nitride layer is P-type gallium nitride, then selective ion implantation is performed on the gallium nitride layer outside the preset region, and the selective ion implantation uses The dopant includes sulfur (S), silicon (Si), selenium (Ce), tellurium (Te) or oxygen (O), so that the gallium nitride layer outside the preset region becomes the N-type gallium nitride layer.
在本發明的一實施例中，上述氮化鎵層的材料為P型氮化鎵，則對預設區域以外的氮化鎵層進行選擇性離子植入，並且所述選擇性離子植入使用的摻質包括氫(H)、氦(He)、鐵(Fe)、氮(N 2)或氬(Ar)，以使所述預設區域以外的氮化鎵層變成所述隔離區。 In an embodiment of the present invention, the material of the gallium nitride layer is P-type gallium nitride, then selective ion implantation is performed on the gallium nitride layer outside the preset region, and the selective ion implantation uses The dopant includes hydrogen (H), helium (He), iron (Fe), nitrogen (N 2 ) or argon (Ar), so that the gallium nitride layer outside the preset region becomes the isolation region.
在本發明的一實施例中，上述氮化鎵層的材料為未摻雜氮化鎵，則對預設區域的氮化鎵層進行選擇性離子植入，並且所述選擇性離子植入使用的摻質包括鎂(Mg)、碳(C)、鈹(Be)或鈣(Ca)，以使所述預設區域內的氮化鎵層變成P型氮化鎵層。In an embodiment of the present invention, the material of the gallium nitride layer is undoped gallium nitride, then selective ion implantation is performed on the gallium nitride layer in the predetermined region, and the selective ion implantation uses The dopant includes magnesium (Mg), carbon (C), beryllium (Be) or calcium (Ca), so that the gallium nitride layer in the predetermined region becomes a p-type gallium nitride layer.
本發明的另一種常關型氮化鎵元件的製造方法，包括於一基板上形成通道層，於所述通道層上形成障壁層，於所述障壁層上形成P型氮化鎵層，所述P型氮化鎵層具有一預設區域。然後，對所述預設區域以外的P型氮化鎵層進行選擇性離子植入，使其轉變成N型氮化鎵層或隔離區。Another method for manufacturing a normally-off GaN device of the present invention includes forming a channel layer on a substrate, forming a barrier layer on the channel layer, and forming a P-type GaN layer on the barrier layer, so that The P-type GaN layer has a predetermined area. Then, selective ion implantation is performed on the P-type GaN layer outside the preset region to transform it into an N-type GaN layer or an isolation region.
在本發明的另一實施例中，上述選擇性離子植入所使用的摻質包括硫(S)、矽(Si)、硒(Ce)、碲(Te)或氧(O)，以使所述預設區域以外的所述P型氮化鎵層變成N型氮化鎵層。In another embodiment of the present invention, the dopant used in the selective ion implantation includes sulfur (S), silicon (Si), selenium (Ce), tellurium (Te) or oxygen (O), so that all The P-type GaN layer outside the predetermined area becomes an N-type GaN layer.
在本發明的另一實施例中，上述選擇性離子植入所使用的摻質包括氫(H)、氦(He)、鐵(Fe)、氮(N 2)或氬(Ar)，以使所述預設區域以外的所述P型氮化鎵層變成隔離區。 In another embodiment of the present invention, the dopant used in the selective ion implantation includes hydrogen (H), helium (He), iron (Fe), nitrogen (N 2 ) or argon (Ar), so that The P-type GaN layer outside the predetermined area becomes an isolation area.
本發明的再一種常關型氮化鎵元件的製造方法，包括於一基板上形成通道層，於所述通道層上形成障壁層，於所述障壁層上形成未摻雜氮化鎵層，所述未摻雜氮化鎵層具有一預設區域。然後，對預設區域內的未摻雜氮化鎵層進行選擇性離子植入，使所述預設區域內的所述未摻雜氮化鎵層變成P型氮化鎵層。Another method for manufacturing a normally-off gallium nitride device of the present invention includes forming a channel layer on a substrate, forming a barrier layer on the channel layer, and forming an undoped gallium nitride layer on the barrier layer, The undoped GaN layer has a predetermined area. Then, selective ion implantation is performed on the undoped GaN layer in the preset area, so that the undoped GaN layer in the preset area becomes a P-type GaN layer.
在本發明的再一實施例中，上述選擇性離子植入所使用的摻質包括鎂(Mg)、碳(C)、鈹(Be)或鈣(Ca)。In yet another embodiment of the present invention, the dopant used in the selective ion implantation includes magnesium (Mg), carbon (C), beryllium (Be) or calcium (Ca).
在本發明的再一實施例中，上述未摻雜氮化鎵層還包括一常開型氮化鎵元件區，且所述製造方法還包括；形成多個源極/汲極電極，穿過上述未摻雜氮化鎵層與上述障壁層並與上述通道層接觸，其中一個源極/汲極電極同時作為常關型氮化鎵元件與常開型氮化鎵元件的源極/汲極。然後，在上述P型氮化鎵層上形成第一閘極電極，並在所述常開型氮化鎵元件區形成第二閘極電極，所述第二閘極電極穿過上述未摻雜氮化鎵層並與上述障壁層接觸。In yet another embodiment of the present invention, the above-mentioned undoped gallium nitride layer further includes a normally-on gallium nitride element region, and the manufacturing method further includes: forming a plurality of source/drain electrodes, passing through The above-mentioned undoped GaN layer is in contact with the above-mentioned barrier layer and the above-mentioned channel layer, and one of the source/drain electrodes is used as the source/drain of the normally-off GaN element and the normally-on GaN element at the same time . Then, a first gate electrode is formed on the above-mentioned P-type gallium nitride layer, and a second gate electrode is formed on the normally-on gallium nitride element region, and the second gate electrode passes through the above-mentioned undoped The gallium nitride layer is in contact with the aforementioned barrier layer.
基於上述，根據本發明的製造方法，不需要對P型氮化鎵層進行蝕刻，而是改用選擇性離子植入，按照磊晶成長的氮化鎵層的材料的導電型態，選擇適合的摻質，使預設區域內的氮化鎵層維持在P型或者轉變為P型，而在預設區域以外的氮化鎵層維持在未摻雜的狀態或者轉變為N型，甚至是變成幾乎不導電的隔離區。因此，本發明的製造方法不含蝕刻移除P-GaN層的步驟，進而能避免障壁層表面受到損害。Based on the above, according to the manufacturing method of the present invention, it is not necessary to etch the p-type gallium nitride layer, but instead use selective ion implantation. According to the conductivity type of the material of the epitaxially grown gallium nitride layer, a suitable Doping, so that the gallium nitride layer in the predetermined area is maintained in the P-type or transformed into a P-type, while the gallium nitride layer outside the predetermined region is maintained in an undoped state or transformed into an N-type, or even becomes a nearly non-conductive isolation region. Therefore, the manufacturing method of the present invention does not include the step of removing the P-GaN layer by etching, thereby avoiding damage to the surface of the barrier layer.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.
以下實施例中所附的圖式是為了能更完整地描述本發明的實施例，然而本發明仍可使用許多不同的形式來實施，不限於所記載的實施例。此外，為了清楚起見，各個區域或膜層的相對厚度、距離及位置可能縮小或放大。另外，在圖式中使用相似或相同的元件符號表示相似或相同的部位或特徵的存在。The attached drawings in the following embodiments are for more complete description of the embodiments of the present invention, however, the present invention can still be implemented in many different forms, not limited to the described embodiments. In addition, the relative thicknesses, distances and positions of various regions or layers may be reduced or exaggerated for clarity. In addition, the use of similar or identical reference numerals in the drawings indicates the existence of similar or identical parts or features.
圖1是依照本發明的第一實施例的一種常關型氮化鎵元件的製造流程步驟圖。FIG. 1 is a flow chart of the manufacturing process of a normally-off GaN device according to the first embodiment of the present invention.
請參照圖1，在步驟S100中，於基板上形成通道層（channel layer），其中基板例如矽基板或其他可用於磊晶的基板。通道層例如未摻雜的氮化鎵（GaN）層。此外，基板與通道層之間還可視需求增設一層緩衝層，其中緩衝層可減緩後續形成於緩衝層上方的通道層的應變，並具有防止缺陷形成於通道層的效果，緩衝層的材料可列舉但不限於氮化鋁、氮化鎵、氮化鎵鋁或前述之組合。以上膜層可利用磊晶製程形成磊晶結構，其中磊晶製程例如金屬有機化學氣相沉積（MOCVD）、氫化物氣相磊晶法（HVPE）、分子束磊晶法（MBE）或前述方法之組合。Referring to FIG. 1 , in step S100 , a channel layer is formed on a substrate, such as a silicon substrate or other substrates that can be used for epitaxy. A channel layer such as an undoped gallium nitride (GaN) layer. In addition, a buffer layer can also be added between the substrate and the channel layer as required, wherein the buffer layer can relieve the strain of the channel layer subsequently formed above the buffer layer, and has the effect of preventing defects from forming in the channel layer. The material of the buffer layer can be listed But not limited to aluminum nitride, gallium nitride, aluminum gallium nitride or combinations thereof. The above film layer can form an epitaxial structure using an epitaxial process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE) or the aforementioned methods combination.
在步驟S102中，於通道層上形成障壁層（barrier layer），其中障壁層的材料是未摻雜的III-V族半導體材料，可列舉但不限於氮化鎵鋁（AlGaN）或者其他適當的III-V族材料。通道層與障壁層為異質材料，以於通道層與障壁層之間形成一異質界面，藉由異質材料的能隙差，可使二維電子氣（2DEG）形成於此異質界面上。障壁層可利用磊晶製程形成，如MOCVD、HVPE、MBE或前述方法之組合。In step S102, a barrier layer (barrier layer) is formed on the channel layer, wherein the material of the barrier layer is an undoped III-V semiconductor material, such as but not limited to aluminum gallium nitride (AlGaN) or other suitable III-V materials. The channel layer and the barrier layer are made of heterogeneous materials to form a heterogeneous interface between the channel layer and the barrier layer. With the energy gap difference of the heterogeneous materials, two-dimensional electron gas (2DEG) can be formed on the heterogeneous interface. The barrier layer can be formed by epitaxial process, such as MOCVD, HVPE, MBE or a combination of the aforementioned methods.
在步驟S104中，於障壁層上形成氮化鎵層。所述氮化鎵層的材料可為P型氮化鎵（P-GaN）或未摻雜氮化鎵（u-GaN）。所述氮化鎵層可利用磊晶製程形成，如MOCVD、HVPE、MBE或前述方法之組合。In step S104, a gallium nitride layer is formed on the barrier layer. The material of the gallium nitride layer may be P-type gallium nitride (P-GaN) or undoped gallium nitride (u-GaN). The GaN layer can be formed by epitaxial process, such as MOCVD, HVPE, MBE or a combination of the aforementioned methods.
在步驟S106中，確定氮化鎵層的材料是P-GaN或是u-GaN。如果氮化鎵層的材料是P-GaN，則進行步驟S108；如果氮化鎵層的材料是u-GaN，則進行步驟S110。In step S106, it is determined whether the material of the GaN layer is P-GaN or u-GaN. If the material of the gallium nitride layer is P-GaN, proceed to step S108; if the material of the gallium nitride layer is u-GaN, proceed to step S110.
在步驟S108中，對預設區域以外的氮化鎵層進行選擇性離子植入。在一實施例中，對預設區域以外的氮化鎵層進行選擇性離子植入，並且所述選擇性離子植入使用的摻質為施體（Donor），可列舉但不限於：包括硫(S)、矽(Si)、硒(Ce)、碲(Te)或氧(O)，以使所述預設區域以外的（P型）氮化鎵層變成N型氮化鎵（N-GaN）層。在另一實施例中，對預設區域以外的氮化鎵層進行選擇性離子植入，並且所述選擇性離子植入使用的摻質包括氫(H)、氦(He)、鐵(Fe)、氮(N 2)或氬(Ar)，以使所述預設區域以外的（P型）氮化鎵層變成隔離區（Isolated region）。 In step S108, selective ion implantation is performed on the gallium nitride layer outside the preset region. In one embodiment, selective ion implantation is performed on the gallium nitride layer outside the preset region, and the dopant used in the selective ion implantation is a donor, which can be listed but not limited to: including sulfur (S), silicon (Si), selenium (Ce), tellurium (Te) or oxygen (O), so that the (P-type) gallium nitride layer outside the predetermined region becomes N-type gallium nitride (N- GaN) layer. In another embodiment, selective ion implantation is performed on the gallium nitride layer outside the preset region, and the dopants used in the selective ion implantation include hydrogen (H), helium (He), iron (Fe ), nitrogen (N 2 ) or argon (Ar), so that the (P-type) gallium nitride layer outside the preset region becomes an isolated region (Isolated region).
在步驟S110中，對預設區域的氮化鎵層進行選擇性離子植入，並且所述選擇性離子植入使用的摻質包括鎂(Mg)、碳(C)、鈹(Be)或鈣(Ca)，以使所述預設區域內的（未摻雜）氮化鎵層變成P型氮化鎵層。In step S110, selective ion implantation is performed on the gallium nitride layer in the predetermined region, and the dopant used in the selective ion implantation includes magnesium (Mg), carbon (C), beryllium (Be) or calcium (Ca), so that the (undoped) gallium nitride layer in the predetermined region becomes a p-type gallium nitride layer.
在預設區域內完成P型氮化鎵層的形成後，可以分別形成連至通道層的源極與汲極電極和位於P型氮化鎵層上的閘極電極。詳細內容可參照以下說明。After the P-type GaN layer is formed in the predetermined area, the source and drain electrodes connected to the channel layer and the gate electrode on the P-type GaN layer can be formed respectively. For details, please refer to the following instructions.
圖2A至圖2E是依照本發明的第二實施例的一種常關型氮化鎵元件的製造流程剖面示意圖，其中使用與第一實施例相同的用語來表示相同的部分與構件，且相同的部分與構件的相關內容也可參照第一實施例的內容，不再贅述。2A to 2E are schematic cross-sectional views of the manufacturing process of a normally-off gallium nitride device according to the second embodiment of the present invention, wherein the same terms as those in the first embodiment are used to represent the same parts and components, and the same Part of the content related to the components can also refer to the content of the first embodiment, and will not be described again.
請先參照圖2A，於一基板200上形成通道層202，於所述通道層202上形成障壁層204，然後於所述障壁層204上形成P型氮化鎵層206，其中形成通道層202、障壁層204與P型氮化鎵層206的方法例如有機金屬化學氣相沉積（MOCVD）或其他適合的磊晶製程。所述P型氮化鎵層206具有一預設區域R1。然後，為了施行選擇性離子植入，可先在P型氮化鎵層206上沉積形成一層罩幕層208，其材料例如介電材料。然後再利用曝光顯影製程，在罩幕層208上形成圖案化的光阻層210，這層光阻層210對準預設區域R1。2A, a channel layer 202 is formed on a substrate 200, a barrier layer 204 is formed on the channel layer 202, and a P-type gallium nitride layer 206 is formed on the barrier layer 204, wherein the channel layer 202 is formed. , the method of the barrier layer 204 and the P-type GaN layer 206 such as metal organic chemical vapor deposition (MOCVD) or other suitable epitaxial process. The P-type GaN layer 206 has a predetermined region R1. Then, in order to perform selective ion implantation, a mask layer 208 may be deposited on the P-type GaN layer 206 first, and its material is, for example, a dielectric material. Then, an exposure and development process is used to form a patterned photoresist layer 210 on the mask layer 208 , and the photoresist layer 210 is aligned to the preset region R1 .
然後，請參照圖2B，先利用光阻層（圖2A的210）作為蝕刻罩幕，蝕刻去除露出的罩幕層，則剩下的罩幕層208a會遮蔽P型氮化鎵層206的預設區域R1。接著，移除光阻層，再進行離子植入製程212，即可在預設區域R1以外的P型氮化鎵層206植入摻質，使預設區域R1以外的P型氮化鎵層206的導電狀態發生變化。離子植入製程212一般包含注入離子以及退火步驟，且可通過控制離子的劑量、能量、掃描率等對於離子植入的濃度與深度進行調整。Then, referring to FIG. 2B , first use the photoresist layer ( 210 in FIG. 2A ) as an etching mask to etch and remove the exposed mask layer, and then the remaining mask layer 208a will shield the preliminary layer of the P-type gallium nitride layer 206. Let region R1 be set. Next, the photoresist layer is removed, and then the ion implantation process 212 is performed, so that dopants can be implanted in the P-type GaN layer 206 outside the predetermined region R1, so that the P-type GaN layer outside the predetermined region R1 The conduction state of 206 changes. The ion implantation process 212 generally includes ion implantation and annealing steps, and the concentration and depth of ion implantation can be adjusted by controlling the dose, energy, scan rate, etc. of the ions.
接著，請參照圖2C，進行退火步驟（如RTP退火）後，可去除植入區（預設區域R1以外的區域）的缺陷並使摻質分佈均勻，並於退火步驟後移除罩幕層（圖2B的208a）。上一步驟所用的摻質如為施體（Donor），可列舉但不限於：硫(S)、矽(Si)、硒(Ce)、碲(Te)或氧(O)，則預設區域R1以外的P型氮化鎵層會變成N型氮化鎵層214a。另一方面，上一步驟所用的摻質如為氫(H)、氦(He)、鐵(Fe)、氮(N)或氬(Ar)，則預設區域R1以外的P型氮化鎵層會變成隔離區214b，亦即在此區域內的導電率極低，接近於絕緣狀態。此時，二維電子氣2DEG會形成在P型氮化鎵層206以外的通道層202表面附近，且預設區域R1以外的障壁層204不受損害。也就是說，障壁層204與N型氮化鎵層214a（或隔離區214b）之間的界面仍維持磊晶結構之間晶格有小差異的接面。Next, please refer to FIG. 2C, after performing an annealing step (such as RTP annealing), the defects in the implanted region (regions other than the preset region R1) can be removed and the dopant distribution can be made uniform, and the mask layer can be removed after the annealing step (208a of Figure 2B). If the dopant used in the previous step is a donor (Donor), it can be listed but not limited to: sulfur (S), silicon (Si), selenium (Ce), tellurium (Te) or oxygen (O), then the preset area The P-type GaN layer other than R1 will become the N-type GaN layer 214a. On the other hand, if the dopant used in the previous step is hydrogen (H), helium (He), iron (Fe), nitrogen (N) or argon (Ar), the p-type gallium nitride outside the preset region R1 The layer becomes an isolation region 214b, that is, the conductivity in this region is extremely low, close to an insulating state. At this time, the two-dimensional electron gas 2DEG will be formed near the surface of the channel layer 202 other than the P-type GaN layer 206 , and the barrier layer 204 outside the predetermined region R1 will not be damaged. That is to say, the interface between the barrier layer 204 and the N-type GaN layer 214 a (or the isolation region 214 b ) still maintains a junction with a small difference in lattice between the epitaxial structures.
之後，請參照圖2D，可形成源極電極216與汲極電極218，穿過N型氮化鎵層214a（或隔離區214b）與障壁層204，且與通道層202接觸。形成源極電極216與汲極電極218的步驟例如先蝕穿N型氮化鎵層214a（或隔離區214b）與障壁層204，再沉積源極/汲極歐姆金屬，並進行RTP退火，以形成歐姆接觸。Afterwards, referring to FIG. 2D , a source electrode 216 and a drain electrode 218 may be formed, passing through the N-type GaN layer 214 a (or the isolation region 214 b ) and the barrier layer 204 , and contacting the channel layer 202 . The step of forming the source electrode 216 and the drain electrode 218 is, for example, etching through the N-type GaN layer 214a (or the isolation region 214b) and the barrier layer 204 first, then depositing the source/drain ohmic metal, and performing RTP annealing to form an ohmic contact.
接著，請參照圖2E，在P型氮化鎵層206上形成一閘極電極220。Next, referring to FIG. 2E , a gate electrode 220 is formed on the P-type GaN layer 206 .
圖3A至圖3E是依照本發明的第三實施例的一種常關型氮化鎵元件的製造流程剖面示意圖，其中使用與第二實施例相同的元件符號來表示相同或近似的部分與構件，且相同或近似的部分與構件的相關內容也可參照第二實施例的內容，不再贅述。3A to 3E are schematic cross-sectional views of the manufacturing process of a normally-off GaN device according to the third embodiment of the present invention, wherein the same or similar parts and components are represented by the same element symbols as those in the second embodiment, And the related content of the same or similar parts and components can also refer to the content of the second embodiment, and will not be described again.
請參照圖3A，於基板200上依序形成通道層202和障壁層204後，二維電子氣2DEG會形成在通道層202表面接近障壁層204。然後，於所述障壁層204上形成未摻雜氮化鎵層300，其中形成通道層202、障壁層204與未摻雜氮化鎵層300的方法例如有機金屬化學氣相沉積（MOCVD）或其他適合的磊晶製程。所述未摻雜氮化鎵層300具有一預設區域R1。然後，為了施行選擇性離子植入，可先在未摻雜氮化鎵層300上沉積形成一層罩幕層302，其材料例如介電材料。然後再利用曝光顯影製程，在罩幕層302上形成圖案化的光阻層304，這層光阻層304對準預設區域R1以外的區域。Referring to FIG. 3A , after the channel layer 202 and the barrier layer 204 are sequentially formed on the substrate 200 , the two-dimensional electron gas 2DEG will be formed on the surface of the channel layer 202 close to the barrier layer 204 . Then, an undoped gallium nitride layer 300 is formed on the barrier layer 204, wherein the channel layer 202, the barrier layer 204 and the undoped gallium nitride layer 300 are formed by methods such as metal organic chemical vapor deposition (MOCVD) or Other suitable epitaxy processes. The undoped GaN layer 300 has a predetermined region R1. Then, in order to perform selective ion implantation, a mask layer 302 may be deposited on the undoped GaN layer 300 first, and its material is, for example, a dielectric material. Then, an exposure and development process is used to form a patterned photoresist layer 304 on the mask layer 302 , and the photoresist layer 304 is aligned to the area outside the preset region R1 .
然後，請參照圖3B，先利用光阻層（圖3A的304）作為蝕刻罩幕，蝕刻去除露出的罩幕層，則剩下的罩幕層302a會遮蔽預設區域R1以外的未摻雜氮化鎵層300。接著，移除光阻層，再進行離子植入製程306，其中使用的摻質可列舉但不限於鎂(Mg)、碳(C)、鈹(Be)或鈣(Ca)，因此預設區域R1內的未摻雜氮化鎵層300會轉變為P型。Then, referring to FIG. 3B , first use the photoresist layer (304 in FIG. 3A ) as an etching mask to etch and remove the exposed mask layer, and the remaining mask layer 302a will shield the undoped GaN layer 300 . Next, the photoresist layer is removed, and then the ion implantation process 306 is performed, in which the dopants used can be listed but not limited to magnesium (Mg), carbon (C), beryllium (Be) or calcium (Ca), so the predetermined area The undoped GaN layer 300 in R1 will be transformed into P-type.
隨後，請參照圖3C，進行退火步驟（如RTP退火）後，可去除植入區（預設區域R1）的缺陷並使摻質分佈均勻，而在預設區域R1內形成P型氮化鎵層308，並於退火步驟後移除罩幕層（圖3B的302a）。此時，二維電子氣2DEG會形成在P型氮化鎵層308以外的通道層202表面附近，且預設區域R1以外的障壁層204不受損害。也就是說，障壁層204與未摻雜氮化鎵層300之間的界面仍維持磊晶結構之間晶格有小差異的接面。Subsequently, please refer to FIG. 3C, after performing an annealing step (such as RTP annealing), the defects in the implanted region (predetermined region R1) can be removed and the distribution of dopants can be made uniform, so that P-type gallium nitride can be formed in the predetermined region R1 layer 308, and remove the mask layer (302a of FIG. 3B) after the annealing step. At this time, the two-dimensional electron gas 2DEG will be formed near the surface of the channel layer 202 other than the P-type GaN layer 308 , and the barrier layer 204 outside the predetermined region R1 will not be damaged. That is, the interface between the barrier layer 204 and the undoped GaN layer 300 still maintains a junction with a small difference in crystal lattice between the epitaxial structures.
然後，請參照圖3D，可採用第二實施例所述的方式形成源極電極216與汲極電極218，穿過未摻雜氮化鎵層300與障壁層204，且與通道層202接觸。Then, referring to FIG. 3D , the source electrode 216 and the drain electrode 218 can be formed in the manner described in the second embodiment, passing through the undoped GaN layer 300 and the barrier layer 204 , and contacting the channel layer 202 .
接著，請參照圖3E，在P型氮化鎵層308上形成一閘極電極220。Next, referring to FIG. 3E , a gate electrode 220 is formed on the P-type GaN layer 308 .
圖4是第三實施例的一種常關型氮化鎵元件結合常開型（或稱D-mode）氮化鎵元件的剖面示意圖，其中沿用圖3E的元件符號來表示相同的部分與構件。FIG. 4 is a schematic cross-sectional view of a normally-off GaN device combined with a normally-on (or called D-mode) GaN device according to the third embodiment, wherein the same parts and components are represented by the reference numerals in FIG. 3E .
請參照圖4，第三實施例的製造方法也可應用於疊接電路（Cascode circuit）的製作，例如未摻雜氮化鎵層300還包括一常開型氮化鎵元件區R2，與預設區域R1相隔一段距離。並且，在形成源極電極216與汲極電極218的同時，也在常開型氮化鎵元件區R2中形成源極/汲極電極；也就是說，汲極電極218作為常開型氮化鎵元件的汲極，而其中一個源極/汲極電極S/D同時作為常關型氮化鎵元件的汲極與常開型氮化鎵元件的源極。而在P型氮化鎵層上形成第一閘極電極G1（即閘極電極220）時，也在常開型氮化鎵元件區R2形成第二閘極電極G2，所述第二閘極電極G2穿過未摻雜氮化鎵層300並與障壁層204接觸，因此二維電子氣2DEG會形成在障壁層204與通道層202之間的界面附近。在一實施例中，第一閘極電極G1與第二閘極電極G2的步驟例如，先蝕穿常開型氮化鎵元件區R2中的未摻雜氮化鎵層300，並露出穿常開型氮化鎵元件區R2中的障壁層204，再在P型氮化鎵層308上以及露出的障壁層204上同時沉積形成第一閘極電極G1與第二閘極電極G2。然而，本發明並不限於此，第一閘極電極G1與第二閘極電極G2也可分開沉積形成。常關型氮化鎵元件的源極電極216可經由內連線與常開型氮化鎵元件的閘極（即第二閘極電極）G2連通，形成疊接電路，並因此可大幅降低寄生電感（parasitic inductance）。Please refer to FIG. 4, the manufacturing method of the third embodiment can also be applied to the manufacture of cascode circuits. Let the regions R1 be separated by a certain distance. Moreover, while forming the source electrode 216 and the drain electrode 218, the source/drain electrodes are also formed in the normally-on GaN device region R2; The drain of the gallium device, and one of the source/drain electrodes S/D serves as the drain of the normally-off GaN device and the source of the normally-on GaN device. When the first gate electrode G1 (that is, the gate electrode 220 ) is formed on the P-type gallium nitride layer, the second gate electrode G2 is also formed in the normally-on gallium nitride element region R2, and the second gate electrode The electrode G2 passes through the undoped GaN layer 300 and contacts the barrier layer 204 , so the two-dimensional electron gas 2DEG is formed near the interface between the barrier layer 204 and the channel layer 202 . In one embodiment, the steps of the first gate electrode G1 and the second gate electrode G2 are, for example, first etching through the undoped GaN layer 300 in the normally-on GaN device region R2, and exposing the normally-on GaN layer 300. The barrier layer 204 in the open-type GaN device region R2 is deposited on the P-type GaN layer 308 and the exposed barrier layer 204 simultaneously to form the first gate electrode G1 and the second gate electrode G2 . However, the present invention is not limited thereto, and the first gate electrode G1 and the second gate electrode G2 can also be deposited and formed separately. The source electrode 216 of the normally-off GaN device can be connected to the gate (ie, the second gate electrode) G2 of the normally-on GaN device through an interconnection line to form a stacked circuit, thereby greatly reducing parasitic Inductance (parasitic inductance).
綜上所述，本發明通過選擇性離子植入的方式，不需要對P型氮化鎵層進行蝕刻，即可在預設區域內形成P型氮化鎵層，而在預設區域以外維持未摻雜氮化鎵或者將原為P型的氮化鎵層轉變為N型，或是變成幾乎不導電的隔離區。根據本發明的製造方法，能避免障壁層表面因為蝕刻P型氮化鎵層受到損害，進而避面2DEG的濃度受到影響。To sum up, the present invention can form a P-type GaN layer in a preset region without etching the P-type GaN layer by means of selective ion implantation, and maintain the P-type GaN layer outside the preset region. Undoped GaN either transforms the p-type GaN layer into N-type, or becomes a nearly non-conductive isolation region. According to the manufacturing method of the present invention, the surface of the barrier layer can be prevented from being damaged by etching the P-type gallium nitride layer, thereby preventing the concentration of 2DEG from being affected.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.
200:基板 202:通道層 204:障壁層 206、308:P型氮化鎵層 208、208a、302、302a:罩幕層 210、304:光阻層 212、306:離子植入 214a:N型氮化鎵層 214b:隔離區 216:源極電極 218:汲極電極 220:閘極電極 300:未摻雜氮化鎵層 2DEG:二維電子氣 G1:第一閘極電極 G2:第二閘極電極 R1:預設區域 R2:常開型氮化鎵元件區 S100、S102、S104、S106、S108、S110:步驟 S/D:源極/汲極電極 200: Substrate 202: channel layer 204: barrier layer 206, 308: P-type gallium nitride layer 208, 208a, 302, 302a: mask layer 210, 304: photoresist layer 212, 306: Ion implantation 214a: N-type gallium nitride layer 214b: Quarantine 216: source electrode 218: Drain electrode 220: gate electrode 300: undoped gallium nitride layer 2DEG: two-dimensional electron gas G1: the first gate electrode G2: The second gate electrode R1: preset area R2: normally-on gallium nitride device area S100, S102, S104, S106, S108, S110: steps S/D: source/drain electrode
圖1是依照本發明的第一實施例的一種常關型氮化鎵元件的製造流程步驟圖。 圖2A至圖2E是依照本發明的第二實施例的一種常關型氮化鎵元件的製造流程剖面示意圖。 圖3A至圖3E是依照本發明的第三實施例的一種常關型氮化鎵元件的製造流程剖面示意圖。 圖4是第三實施例的一種常關型氮化鎵元件結合常開型氮化鎵元件的剖面示意圖。 FIG. 1 is a flow chart of the manufacturing process of a normally-off GaN device according to the first embodiment of the present invention. 2A to 2E are schematic cross-sectional views of a manufacturing process of a normally-off GaN device according to a second embodiment of the present invention. 3A to 3E are schematic cross-sectional views of a manufacturing process of a normally-off GaN device according to a third embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of a normally-off GaN device combined with a normally-on GaN device according to the third embodiment.
S100、S102、S104、S106、S108、S110:步驟 S100, S102, S104, S106, S108, S110: steps
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