JP2006120784A - Semiconductor joint superconduction three-terminal element and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture more easily semiconductor superconduction three-terminal element which controls a supercurrent by use of a gate electrode by bringing a source drain electrode made of superconduction metal into an ohmic contact with a channel layer consisting of InGaAs of a high electron mobility transistor. <P>SOLUTION: A gate contact layer 108 is formed so as to expose the upper surface of an etching stop layer 106 by removing selectively an InAlAs layer 128, and by setting a resist pattern 122 as a mask. In this etching, the etching method to be used is capable of etching removal of the InAlAs selectively to InP. Next, by setting a resist pattern 122 as a mask, the etching removal of the exposed etching stop layer 106 is carried out so as to expose the channel layer 105 at both the sides. It changes into the condition that was exposed to both this side. In this etching, the etching method to be used is capable of etching removal of the InGaAs selectively to InP. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor-coupled superconducting three-terminal device having a high electron mobility transistor composed of a channel layer made of InGaAs at a junction and a method for manufacturing the same.

  Many studies have been made on superconducting three-terminal devices corresponding to bipolar transistors and field effect transistors (FETs) in semiconductors beginning with tunnel-type Josephson junction devices. Of these, many attempts have been made for semiconductor-coupled superconducting devices because of the possibility of three-terminal operation by electrical control of semiconductors, and the use of superconducting materials for the source and drain electrodes of high electron mobility transistors has been proposed. (See Patent Document 1). This is because the channel layer is made of InGaAs and enables ohmic contact with the superconducting electrode so that high carrier concentration, high mobility, and high transconductance gm can be obtained. .

  The semiconductor coupled superconducting transistor described above will be described. As shown in FIG. 2, a buffer layer 202 made of non-doped InAlAs and a carrier supply layer 203 made of n-type InAlAs are formed on a substrate 201 made of semi-insulating InP. , A spacer layer 204 made of non-doped InAlAs, a channel layer 205 made of InGaAs, a gate contact layer 208 made of InAlAs, and a source electrode 209 and a drain electrode 210 on the channel layer 205 so as to sandwich the gate contact layer 208. The gate electrode 211 is provided on the gate contact layer 208. The source electrode 209 and the drain electrode 210 are made of Nb, which is a superconducting material, and are in ohmic contact with the channel layer 205.

  Next, a method for manufacturing the element shown in FIG. 2 will be briefly described with reference to FIG. First, as shown in FIG. 3A, on the substrate 201, non-doped InAlAs, n-type InAlAs, non-doped InAlAs, InGaAs, and InAlAs are crystal-grown by, for example, metal organic vapor phase epitaxy to form a buffer layer. 202, a carrier supply layer 203, a spacer layer 204, a channel layer 205, and an InAlAs layer 228 are formed. Next, a photosensitive resin layer 221 for electron beam exposure is formed on the InAlAs layer 228.

  Next, the photosensitive resin layer 221 is patterned by electron beam exposure and development so that a resist pattern 222 is formed as shown in FIG. Next, the InAlAs layer 228 is removed by etching using the resist pattern 222 as a mask to form a gate contact layer 208 as shown in FIG. 3C, with the upper surface of the channel layer 205 exposed on both sides. . Next, Nb is deposited on these by electron beam evaporation to form a superconducting metal layer 223 as shown in FIG.

  Next, the resist pattern 222 is dissolved and removed using a resist stripping solution, and a source electrode 209 and a drain electrode 210 are formed on the channel layer 205 so as to sandwich the gate contact layer 208 as shown in FIG. It is assumed that Next, a photosensitive resin for electron beam exposure is applied onto these so that a photosensitive resin layer 224 is formed as shown in FIG. Next, as shown in FIG. 3G, an opening 224a is formed in the photosensitive resin layer 224 by electron beam exposure and development.

  Next, a metal material to be a gate electrode is deposited to form a metal layer, and thereafter, the photosensitive resin layer 224 is removed so as to leave a deposited portion in the opening 224a of the metal layer. Thus, the gate electrode 211 is formed on the gate contact layer 208 as shown in FIG.

The applicant has not yet found prior art documents related to the present invention by the time of filing other than the prior art documents specified by the prior art document information described in this specification.
Japanese Patent No. 3131291

  However, the conventional manufacturing method described with reference to FIG. 3 has a problem that good ohmic contact between the source electrode 209 and the drain electrode 210 and the channel layer 205 cannot be easily formed. This is because in the etching of the InAlAs layer 228, it is difficult to obtain selectivity with the channel layer 205 made of InGaAs below.

  As described above, in order to obtain good ohmic contact, in the etching of the InAlAs layer 228 using the resist pattern 222 as a mask, the InAlAs layer 228 is completely removed from a predetermined region, and the upper surface of the channel layer 205 is exposed. There is a need. For example, when the InAlAs layer 228 remains on the upper surface of the channel layer 205 on which the source / drain electrodes are formed, this becomes an insulating barrier, and good ohmic contact of the source / drain electrodes made of a superconducting metal cannot be obtained (defective). State 1). Further, if the over-etching is performed so that the InAlAs layer 228 does not remain, the channel layer 205 in the etching region may be lost. In this state, the source / drain electrode comes into contact with the side portion of the channel layer 205, and the contact area becomes extremely small (defective state 2).

  Here, if InAlAs can be selectively etched with respect to InGaAs, it is easy to perform an etching process between the defective state 1 and the defective state 2. However, there is an etching method for selectively etching InAlAs with respect to InGaAs, but this method has a problem that it is difficult to obtain the resistance of the resist pattern 222 made of resin. In order to obtain a gate breakdown voltage, the gate contact layer 208 needs to have a certain thickness of 20 nm or more. Therefore, if this thickness is etched by the above-described etching method, the resist pattern 222 cannot be endured, and high-precision patterning is performed. I can't.

  Therefore, in order to perform patterning with high accuracy, InAlAs is etched in a state where a selection ratio cannot be obtained with respect to InGaAs. As described above, since etching selectivity cannot be obtained between the InAlAs layer 228 and the channel layer 205, the etching of the InAlAs layer 228 is mainly controlled by the processing time. For this reason, it is not easy to perform the etching process between the defective state 1 and the defective state 2 described above, and the conventional manufacturing method forms a source / drain electrode made of a superconducting metal with good ohmic contact. Was not easy.

  The present invention has been made to solve the above-described problems. A source / drain electrode made of a superconductive metal is ohmically connected to a channel layer made of InGaAs of a high electron mobility transistor, and a gate electrode is connected. An object of the present invention is to make it possible to more easily manufacture a semiconductor superconducting three-terminal element that uses and controls a superconducting current.

  The method for manufacturing a semiconductor-coupled superconducting three-terminal device according to the present invention includes a first step in which a carrier supply layer made of n-type InAlAs is formed on a substrate, and an InGaAs layer on the carrier supply layer. A second step in which the channel layer is formed, a third step in which an etching stop layer made of InP is formed on the channel layer, and a semiconductor layer made of InAlAs are formed on the etching stop layer. A fourth step for forming the mask pattern, a fifth step for forming a mask pattern having a predetermined shape on the semiconductor layer, and a first etching for selectively etching InAlAs with respect to InP. The semiconductor layer is selectively etched using the mask pattern as a mask, and made of InAlAs with an etching stop layer in a predetermined region exposed. The etching stop layer is selectively etched using the mask pattern as a mask by the sixth step in which the gate contact layer is formed and the second etching in which InP is selectively etched with respect to InGaAs. The layer is exposed to the seventh step, and a superconducting metal is selectively deposited on the exposed channel layer to form ohmic contact on the channel layer on both sides of the gate contact layer. At least an eighth step in which a source electrode and a drain electrode made of a superconducting metal are formed and a ninth step in which a gate electrode is formed on the gate contact layer are provided. . According to this manufacturing method, the surface of the channel layer on which the source electrode and the drain electrode are formed is exposed without reducing the thickness of the channel layer in the etching process of the gate contact layer, and these good ohmic contacts can be obtained. Be able to.

  In the above manufacturing method, before forming the etching stop layer, an additional etching stop layer made of InAlAs thinner than the channel layer is formed on the channel layer, and in the seventh step, the etching stop layer is selectively etched. After that, the additional etching stop layer may be etched by sputter etching using the mask pattern as a mask so that the channel layer in a predetermined region is exposed.

  Further, a semiconductor coupled superconducting three-terminal element according to the present invention includes an n-type InAlAs carrier supply layer formed on a substrate, an InGaAs channel layer formed on the carrier supply layer, An etching stop layer made of InP formed on the channel layer, a gate contact layer made of InAlAs formed on the etching stop layer, a gate electrode formed on the gate contact layer, a gate At least a source electrode and a drain electrode made of a superconducting metal formed in ohmic contact with each other on the channel layer on both sides of the contact layer, and a two-dimensional electron gas is generated in the channel layer by carriers supplied from the carrier supply layer. It is designed to be formed. In this element, the channel layer can be protected by the etching stop layer in forming the gate contact layer. In this semiconductor coupled superconducting three-terminal element, an additional etching stop layer made of InAlAs thinner than the channel layer may be provided between the channel layer and the etching stop layer.

  As described above, according to the present invention, since the etching stop layer made of indium phosphide is provided between the channel layer and the gate contact layer, the thickness of the channel layer is reduced in the etching process of the gate contact layer. Without decreasing, the surface of the channel layer on which the source electrode and the drain electrode are formed is exposed, and these good ohmic contacts can be obtained. As a result, a semiconductor superconducting three-terminal device in which a source / drain electrode made of a superconducting metal is ohmically connected to a channel layer made of InGaAs of a high electron mobility transistor and a superconducting current is controlled by using a gate electrode is easier. The excellent effect of being able to be manufactured easily is obtained.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1A to FIG. 1I are process diagrams for explaining an example of a manufacturing method of a semiconductor coupled superconducting three-terminal element in an embodiment of the present invention. First, as shown in FIG. 1A, non-doped InAlAs, n-type InAlAs, non-doped InAlAs, and InGaAs are crystallized on a substrate 101 made of semi-insulating InP, for example, by metal organic chemical vapor deposition. The buffer layer 102, the carrier supply layer 103, the spacer layer 104, and the channel layer 105 are formed by growth. Subsequently, InP and InAlAs are crystal-grown by, for example, metal organic vapor phase epitaxy, and an etching stop layer 106 made of InP and an InAlAs layer (semiconductor layer) 128 are formed. Next, the photosensitive resin layer 121 for electron beam exposure is formed on the InAlAs layer 128.

  Next, the photosensitive resin layer 121 is patterned by electron beam exposure and development so that a resist pattern 122 is formed as shown in FIG. Next, the InAlAs layer 128 is selectively removed by etching using the resist pattern 122 as a mask to form a gate contact layer 108 as shown in FIG. 1C, and the upper surface of the etching stop layer 106 is exposed on both sides thereof. State. In this etching, for example, wet etching using an etchant composed of citric acid and hydrogen peroxide may be performed. In this manner, by using an etching method that can selectively remove InAlAs with respect to InP, only the InAlAs layer 128 can be selectively processed in the patterning process of the InAlAs layer 128.

  Next, using the resist pattern 122 as a mask, the exposed etching stop layer 106 is removed by etching, and the channel layer 105 is exposed on both sides. This etching may be performed by wet etching using an etching solution such as hydrochloric acid, phosphoric acid, acetic acid, and water. Further, wet etching using hydrogen chloride water as an etchant may be used. As described above, the etching stop layer 106 can be selectively removed by using an etching method that can selectively remove InP with respect to InGaAs. Therefore, even if overetching is performed to completely remove the etching stop layer 106, the channel layer 105 is prevented from being etched and the film thickness is reduced.

Next, a superconducting metal such as Nb is deposited on these by an electron beam evaporation method, and a superconducting metal layer 123 is formed as shown in FIG. Needless to say, not only Nb but also other superconducting materials such as YBa ₂ Cu ₃ O _7-x may be used. Next, the resist pattern 122 is dissolved and removed using a resist stripping solution, and the source electrode 109 and the drain electrode 110 are formed on the channel layer 105 so as to sandwich the region of the gate contact layer 108 as shown in FIG. Is formed. After that, the element region is processed into a mesa shape in order to separate the elements, and thereafter, the gate electrode 111 shown below is formed.

  Next, a photosensitive resin for electron beam exposure is applied, and the photosensitive resin layer 124 is formed as shown in FIG. Next, as shown in FIG. 1H, an opening 124a is formed in the photosensitive resin layer 124 by electron beam exposure and development. The opening 124a is, for example, a groove extending in a direction perpendicular to the paper surface of FIG. Next, a metal material that becomes a gate electrode such as gold (Au) is deposited to form a metal layer, and thereafter, a photosensitive resin is left so as to leave a deposited portion in the opening 124a of the metal layer. By removing the layer 124, the gate electrode 111 is formed on the gate contact layer 108 as shown in FIG. Note that the formed gate electrode 111 is disposed over the channel layer 105 in a necessary region, and is electrically separated from the two-dimensional electron gas formed in the channel layer 105 in other regions. .

  By the above, the state in which the semiconductor coupled superconducting three-terminal element in the present embodiment is formed is obtained. According to the manufacturing method described above, the surface of the channel layer 105 can be exposed without substantially etching the channel layer 105. Therefore, according to this manufacturing method, it is possible to easily obtain good ohmic contact between the source electrode 109 and the drain electrode 110 and the channel layer 105.

  Incidentally, the selective etching of the etching stop layer 106 made of InP is a wet process, and the formation of the superconducting metal layer 123 is a deposition process in a vacuum vessel. Therefore, after the selective etching of the etching stop layer 106, the exposed region of the channel layer 105 is exposed to air until the superconducting metal layer 123 is formed. As a result, in the manufacturing method described above, an oxide film formed by natural oxidation is formed in a region where the channel layer 105 is exposed, in other words, a region where an ohmic contact with the source electrode 109 and the drain electrode 110 is to be formed. There is a case. When the oxide film is formed in this way, good ohmic contact cannot be obtained.

  In order to solve such a problem, for example, a thin InAlAs layer (additional etching stop layer) having a thickness of about 5 nm may be provided between the channel layer 105 and the etching stop layer 106. InAlAs, like InGaAs, functions as an etching stop layer having high selectivity to the InP layer. In addition, after the selective etching of the etch stop layer 106, the presence of the thin InAlAs layer causes the above-described oxidation of the region in which the ohmic contact with the source electrode 109 and the drain electrode 110 of the channel layer 105 is to be formed. Formation of the film is suppressed.

  If the thin InAlAs layer has a thickness of about 5 nm, the thin InAlAs layer is completely removed without affecting the channel layer 105 even if an etching method having no selectivity such as sputter etching is used. Thus, it is easy to expose the surface of the channel layer 105. Note that the thin InAlAs layer may be thinner than the channel layer 105. Therefore, after the selective etching of the etching stop layer 106, the thin InAlAs layer is removed by a dry process, and the superconducting metal layer 123 can be deposited while the vacuum state is maintained. Thus, by providing a thin InAlAs layer having a film thickness of about 5 nm between the channel layer 105 and the etching stop layer 106, the exposed surface of the channel layer 105 can be removed from the air before the formation of the superconducting metal layer 123. It will be possible to prevent exposure.

It is process drawing for demonstrating the example of the manufacturing method of the semiconductor coupling superconducting transistor in embodiment of this invention. It is typical sectional drawing which shows the structure of the conventional semiconductor coupling superconducting transistor. It is process drawing for demonstrating the manufacturing method of the conventional semiconductor coupling superconducting transistor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 ... Substrate, 102 ... Buffer layer, 103 ... Carrier supply layer, 104 ... Spacer layer, 105 ... Channel layer, 106 ... Etching stop layer, 108 ... Gate contact layer, 109 ... Source electrode, 110 ... Drain electrode, 111 ... Gate Electrode 121 ... photosensitive resin layer 122 ... resist pattern 123 ... superconducting metal layer 124 ... photopolymer film 124a ... opening part 128 ... InAlAs layer

Claims (4)

A first step in which a carrier supply layer made of n-type InAlAs is formed on a substrate;
A second step in which a channel layer made of InGaAs is formed on the carrier supply layer;
A third step in which an etching stop layer made of InP is formed on the channel layer;
A fourth step in which a semiconductor layer made of InAlAs is formed on the etching stop layer;
A fifth step in which a mask pattern having a predetermined shape is formed on the semiconductor layer;
In the first etching in which InAlAs is selectively etched with respect to InP, the semiconductor layer is selectively etched using the mask pattern as a mask, and the gate contact made of InAlAs with the etching stop layer in a predetermined region exposed. A sixth step in which a layer is formed;
A second step in which InP is selectively etched with respect to InGaAs, a seventh step of selectively etching the etching stop layer using the mask pattern as a mask and exposing the channel layer in a predetermined region; ,
A source electrode and a drain made of a superconducting metal formed in ohmic contact with the channel layer on both sides of the gate contact layer by selectively depositing a superconducting metal on the exposed channel layer. An eighth step in which an electrode is formed;
And a ninth step of forming a gate electrode on the gate contact layer. 9. A method of manufacturing a semiconductor coupled superconducting three-terminal element, comprising: In the manufacturing method of the semiconductor coupling superconducting three terminal element according to claim 1,
Before forming the etching stop layer, an additional etching stop layer made of InAlAs thinner than the channel layer is formed on the channel layer,
In the seventh step, after the etching stop layer is selectively etched, the additional etching stop layer is etched using the mask pattern as a mask by sputter etching to expose the channel layer in a predetermined region. A method for producing a semiconductor-coupled superconducting three-terminal element, characterized in that: A carrier supply layer made of n-type InAlAs formed on the substrate;
A channel layer made of InGaAs formed on the carrier supply layer;
An etching stop layer made of InP formed on the channel layer;
A gate contact layer made of InAlAs formed on the etching stop layer;
A gate electrode formed on the gate contact layer;
At least a source electrode and a drain electrode made of a superconducting metal formed in ohmic contact on the channel layer on both sides of the gate contact layer, and the channel layer by carriers supplied from the carrier supply layer A semiconductor-coupled superconducting three-terminal device characterized in that a two-dimensional electron gas is formed. The semiconductor-coupled superconducting three-terminal element according to claim 3,
A semiconductor coupled superconducting three-terminal device comprising an additional etching stop layer made of InAlAs thinner than the channel layer between the channel layer and the etching stop layer.

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