JPS63187666A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To form an ultramicro gate electrode by shaping a gate electrode through photolithography and etching treatment. CONSTITUTION:A P-type GaAs layer 2 and an N-type GaAs layer 3 are grown onto a GaAs substrate 1 in an epitaxial manner, and an N<+> type Ge layer 10 is formed onto said operating layer 3 through epitaxial growth. The Ge layer 10 is etched by using a mask to shape a source region 5 and a drain region 6. A conductive layer 13 forming a Schottky junction between the operating layer 3 and the layer 13 and shaping an ohmic junction between the regions 5, 6 is laminated. A source electrode 7, a drain electrode 8 and a gate electrode 9 are formed from the conductive layer 13 through etching treatment employing a mask. Accordingly, the gate electrode is fined while a FET having large mutual conductance gm can be acquired.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a field effect transistor, and more specifically to a method for manufacturing a field effect transistor, which is a semiconductor integrated circuit element.

[Conventional technology]

Transconductance fm is one of the important parameters that determines the characteristics of field effect transistors, but is it important to increase the speed of integrated circuits? 1 is essential. In order to increase the mutual conductance, it is necessary to increase the impurity concentration of the source semiconductor layer and the drain semiconductor layer, and to decrease the ohmic resistance and sheet resistance.

In this case, the use of Ge as the source semiconductor layer and the drain semiconductor layer, rather than GaAs, allows for a higher impurity concentration (up to about 10"am-') and an increase of 2 m.

The conventional field effect transistor using this Ge
As shown in the figure. This field effect transistor is the fourth field effect transistor described below.
It is manufactured by the manufacturing process shown in Figures (a) to (d). That is, (1) a semiconductor substrate 4 is prepared in which a P-type GaAs semiconductor 2 + an n-type GaAs semiconductor operating layer 3 are formed in this order on a semi-insulating GaAs semiconductor substrate body 1;
A Ge layer 10 with a high n-type impurity concentration is formed (Fig. 4(a)
) o (2) Form the source electrode 7 and the drain electrode 8 on the Ge layer 10 (see FIG. 4(b)). (3) The Ge layer 10 is etched using masks 11 and 12 made of photoresist, and the masks 11, 12 and 9 from the Ge layer 10 also have a slightly smaller pattern, and the source electrode 7 is etched. .

A source semiconductor layer 5 and a drain semiconductor layer 6 having a pattern larger than the drain electrode 8 are formed (see FIG. 4C). (4) A gate electrode 9 is formed on the semiconductor active layer 3 and in a region other than under the photoresists 11 and 12 by self-line using a conductive material different from that of the source electrode 7 and drain electrode 8 ( (See Figure 4(d)).

The above are the structures of conventionally proposed field effect transistors and their manufacturing methods. According to the field effect transistor having such a structure, (i) since the source semiconductor layer and the drain semiconductor layer are made of Ge, the n-type impurity concentration can be made higher than that of GaAs (n~10 ”
am-"). Therefore, the sheet resistance of the source semiconductor layer and the drain semiconductor layer can be significantly reduced. (ii) The source semiconductor layer and the drain semiconductor layer are located above the semiconductor active layer. Because of this, short channel effects are less likely to occur.Furthermore, it has characteristics such as less variation in threshold values.

[Problem that the invention seeks to solve]

In this conventional method for manufacturing a field effect transistor, as shown in FIG. 12 and deposited on the semiconductor operating layer 3 to form a gate electrode.

However, for the purpose of creating ultra-fine gates, photoresist 1
If the space between 1 and 12 is narrowed, only a small amount of particles will be deposited on the semiconductor active layer and the space between photoresist 11 and 12 will be closed, making it difficult to form a gate electrode, as shown in FIG. 5(b). For this reason, conventional methods for manufacturing field effect transistors have the disadvantage that there is a limit to the reduction in gate length.

[Means for Solving the Problems of the Invention] Object of the Invention The present invention has the characteristics of a conventional field effect transistor, but has a new electric field suitable for forming an extremely fine gate electrode compared to the conventional field effect transistor. A method for manufacturing an effect transistor is provided.

[Structure of the invention]

In the prior art, a lift-off method was used in the process of forming the gate electrode. However, with this method, it is difficult to form extremely short gate electrodes, as described above. Therefore, in the present invention, the process of forming the gate electrode is performed by photolithography and etching.

〔Example〕

FIG. 1 shows the structure of the field effect transistor of the present invention,
The manufacturing steps are shown in FIGS. 2(a) to 2(i).

(1) A P-type GaAs semiconductor 2. is placed on a semi-insulating GaAs semiconductor substrate 1. N-type GaAs semiconductor 3 (n-type impurity concentration 5 x 10 cm, 5
A semiconductor substrate 4 is prepared which is formed by laminating layers by epitaxial growth in the order of thickness of 00 to 100 OA (thickness of 00 to 100 OA).
(See figure (a)).

(2) Next, on the semiconductor operating layer 3, Ge or InGaAs (Q<X<1) 10 having a high n-type impurity concentration (about 5X10"cm-') is epitaxially grown 1-X (see FIG. 2(b)).

(3) Next, the semiconductor 410 is etched by RIE (CF4 etching gas) using photoresist masks 11 and 12 to remove the semiconductor layer 10 from the source semiconductor layer 5 and the drain semiconductor layer 6.
(see FIG. 2(c), (d, >)). Thereafter, the masks 11 and 12 are removed by dissolving them (see FIG. 2(e)).

(4) Next, on the semiconductor active layer 3, on the source semiconductor layer 5, and on the drain semiconductor layer 6,
A Schottky junction is formed with the semiconductor active layer, and between the source semiconductor layer and the drain semiconductor layer,
Conductive layers (Mo, WSi) forming ohmic junctions
, WSiN, WTi, etc.) 13 are stacked.

If there are irregularities near the surface of the conductive layer on the gate electrode side, (i) Laminate the layers at a substrate temperature of about 300°C.

(ii) Lamination by bias sputtering, ECR nozzle, and snow vine. It is preferable to form the conductive layer using the above method or the like so that the surface of the conductive layer is flat. In order to lower the resistance, it is also possible to stack Au or the like on the upper layer (see Figure 2(f)) (5)
Next, a photoresist mask 1 is applied to the conductive layer.
4, 15, and 16 are used to perform etching treatment with a fluoride such as CF4 (dry etching is preferable. For wet etching, hydrofluoric acid or the like may be used) to remove the conductive layer 13 from the source electrode 7, the drain electrode 8, and the like. A gate electrode 9 is formed (see FIGS. 2(g) and 2(h)). In this fluoride etching process, the etching process is also performed on the gate electrode sides of the source semiconductor layer 5 and the drain semiconductor layer 6 using masks 14 and 15 at the same time. In the case of Ge, it is etched by fluoride, but In
In the case of 1-zGaxAa, it is not etched, so it is not necessarily necessary to etch them at the same time. In other words, there is no problem even if n+4 appears on the side surface as shown in FIG. 2(i) instead of as shown in FIG. 2(h). When layering Au, etc., use another etching method (ion milling, etc.) to remove A.
After etching u, etc., use the same method.

(6) Finally, the masks 14, 15, and 16 are removed to obtain the intended field effect transistor. This packing is
As shown in FIG.

A field effect transistor manufactured by such a manufacturing process has the following features: (i) Since the semiconductor active layer is formed by epitaxial growth, it is possible to form a significantly thinner and highly doped active layer, and a large mutual conductance 2rn can be obtained. 0 +i> Since the source semiconductor layer and the drain semiconductor layer exist on the semiconductor active layer, the short channel effect is less likely to occur.0 (ii) The n-type impurity concentration of the source semiconductor layer and the drain semiconductor layer is set to GaAs. The sheet resistance can be made relatively high and the sheet resistance can be made small.

At the same time, it has the advantages of conventional field effect transistors, such as (iv) it can form a finer gate electrode than conventional field effect transistors, so it has a significantly higher electron velocity and is less susceptible to problems such as the parisistic effect. There is a possibility that a phenomenon may occur.

〔Effect of the invention〕

As explained above, according to the field effect transistor of the present invention, an extremely large mutual conductance of 2□ can be obtained, and at the same time, an extremely large electron mobility can be obtained. Furthermore, an extremely fine structure can be obtained through an extremely simple process. Therefore, it is also applicable to high-density integrated circuits.

[Brief explanation of the drawing]

FIG. 1 shows a cross-sectional view illustrating the structure of a field effect transistor of the present invention. FIGS. 2(a) to 2(i) are cross-sectional views showing the manufacturing process of the field effect transistor of the present invention. FIG. 3 shows a cross-sectional view of a conventional field effect transistor. FIGS. 4(a) to 4(d) are cross-sectional views showing the manufacturing process of a conventional field effect transistor. A mock diagram of gate electrode formation during the process is shown. 1 and 2 (a) to (i), 1 is a semi-insulating GaAs semiconductor substrate 2 is a P-type GaAs semiconductor conductor 3 is an n-type GaAs semiconductor active layer 4 is a semiconductor containing the above-mentioned 1 to 3. The substrate 5 is a source semiconductor layer 6 is a drain semiconductor layer 10 is a Ge layer 11, 12 is a mask 13 is a conductive layer 14, 15, 16 is a mask 7 is a source electrode 8 is a drain electrode Patent applicant Agent of Nippon Telegraph and Telephone Corporation Private Patent Attorney Hisashi Tamamushi Gobe (2 others) 1st
Figure 3 Drawing 1” I revision (no change in content) 2 Figure “OCv” ,ノ ＼ノ
()'' No. 4 Figure 111NNN! tlllllllltl! Figure 5 Procedural Amendment (Zuroku) May 7, 1988 Patent Application No. 19936 2, Name of the invention Method of manufacturing electric effect transistor 3, Relationship with the case of the person making the amendment Residence of the patent applicant Address: 1-1-6 Uchisaiwai-cho, Chiyoda-ku, Tokyo Name (422) Kuchimoto Telegraph and Telephone Co., Ltd. Representative: Tsune Shinfuji 4, Agent address: 2-5-2-6 Minami-Nagasaki, Toshima-ku, Tokyo, as amended. Target drawing (Figure 2)

Claims (5)

[Claims] (1) A step of manufacturing a semiconductor substrate by forming a semiconductor active layer on a semi-insulating GaAs semiconductor substrate, Ge or In_1_-_xGa_xAs having an impurity of a conductivity type opposite to that of the semiconductor active layer on the semiconductor active layer.
(where 0 < forming a conductive layer on the entire surface of the semiconductor active layer and the source/drain semiconductor layer exposed in the step, forming a Schottky junction with the semiconductor active layer, and forming a conductive layer on the source/drain semiconductor layer; forming an ohmic contact with the conductive layer, etching the conductive layer using a photoresist mask to form a pattern of source and drain electrodes, and exposing the semiconductor operating layer at the same time; A method for manufacturing a field effect transistor, comprising the step of removing a mask. (2) The field effect transistor according to claim 1, wherein the semiconductor substrate on which the semiconductor active layer is formed is an n-type GaAs semiconductor active layer formed on a semi-insulating GaAs semiconductor substrate. Manufacturing method. (3) The semiconductor substrate on which the semiconductor active layer is formed is a semi-insulating GaAs semiconductor substrate, a P-type GaAs semiconductor, an n
A method for manufacturing a field effect transistor according to claim 1, characterized in that GaAs type semiconductor active layers are successively formed. (4) The semiconductor substrate on which the semiconductor active layer is formed has a P-type GaAs semiconductor active layer formed on a semi-insulating GaAs semiconductor substrate.
A method for manufacturing a field effect transistor as described in Section 1. (5) The semiconductor substrate on which the semiconductor active layer is formed is characterized in that an n-type GaAs semiconductor and a P-type GaAs semiconductor active layer are sequentially formed on a semi-insulating GaAs semiconductor substrate. Method of manufacturing the field effect transistor described.