JPS59130481A - Schottky gate field effect transistor - Google Patents

Abstract

PURPOSE:To form the structure of an FET of a small occupation area without increasing the unevenness due to an electrode on the surface of a substrate, improve the operating speed, and prevent the deterioration of element characteristics by a method wherein an ohmic junction part required for the operation of a transistor is formed as a thick electrode in the direction of depth. CONSTITUTION:A mesa mark used for positioning is etched on a Cr doped semi- insulating GaAs substrate 31. Thereafter, ion implantation is performed with e.g. resist as a mask, and accordingly an operating layer 32 of a uniform thickness is formed at a desired position. Grooves 36 are formed by performing etching at desired positions of both ends of the operating layer wherein a source electrode and a drain electrode are to be formed, with resist as a mask. Next, ion implantation is performed from an oblique direction with the resist used for the etching as a mask, thus forming a conductive layer 37 in continuity to the operating layer on the side surface of the grooves. Successively the ohmic metal is lifted off. An extra deposited film is removed, and annealing is performed in N2 atmosphere, resulting in the formation of ohmic contacts 33 and 34. Afterwards, the upper metal 38 is evaporated to a desired thickness in order to decrease the electrode resistance of source-drain down to a value required in the operating characteristic of the device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a Schottky gate field effect transistor. The present invention can be applied to a wide range of general semiconductor materials such as single-element semiconductors such as 7Z (Si) or compound semiconductors, without any restrictions regarding the materials. Explanation will be given by taking GaAs among compound semiconductors as an example.

[Background technology]

The general structure of a conventional Schottky gate field effect transistor is made of GaAs, as illustrated in the cross-sectional view of FIG.
After forming an n-type active layer 12 with a uniform thickness on the surface of a semi-insulating semiconductor substrate 11 such as by epitaxial growth or ion implantation, a source electrode 1 is formed on the surface of this active layer.
3. A drain electrode 14 and a gate electrode 15 are formed.

Source electrode 13, drain electrode 14, gate electrode 15
Of these, the lengths of the source electrode and drain electrode are LS and L.
D is generally 5 μm or more, and the area occupied by the source electrode 18 and the drain electrode 14 on the substrate in the FET is larger than that of the goo electrode "14."

However, the size of the region that effectively functions as an electrode in those onic junctions is less than a fraction of the ohmic junction lengths Ls and LD, and therefore, the ohmic junctions of the above-mentioned size are generally A Schottky gate field effect transistor with electrodes includes an ohmic junction that is unnecessary for the device's functionality.

Therefore, by creating a source electrode and a drain electrode having the minimum necessary ohmic junction, the dimensions of the MESFET can be reduced to less than half without impairing the function of the MESFET.

However, simply reducing L8 or LD or both will reduce the source electrode cross-sectional area s8 and the drain electrode cross-sectional area SD, increasing the internal resistance of the source and
The potential gradient in the drain increases and the characteristics of the device deteriorate.

As one of the methods for solving these drawbacks as devices become smaller, it has been realized to increase the thicknesses dS and dd of the source and drain electrodes. However, in the above-described structure, the reduction of LS and LD is not necessarily effectively realized.

For example, if the thickness of the electrode is increased, the unevenness on the substrate surface will be enlarged, making it difficult to perform precise microfabrication in the manufacturing process. In other words, according to the conventional method, the thickness of the source and drain electrodes, ds'
Due to the limitation of dd, the source electrode length L8. The drain electrode length Ld satisfies Ss/ds≦Ls, Sa under the condition that the source electrode internal resistance drain electrode internal resistance b'C does not increase.
/da≦Ld, so generally L8
．． Ld has a drawback of being about 5 μm.

[Disclosure of the invention]

The present invention provides a new ME that solves the drawbacks of the above-mentioned conventional structure.
The S FET groove structure is proposed.

The present invention will be explained below based on the drawings.

An example of the MESFET of the present invention is shown in FIG. FIG. 2 shows an active layer 22 formed on a semiconductor substrate 21.
This is a MESFET in which another active layer is formed in contact with both ends of the active layer 27, at least one of a source electrode 23 and a drain electrode 24 is provided at a position deeper than the substrate surface, and an ohmic contact region is formed in the depth direction of the active layer 27. Here, 25 is a gate electrode.

The present invention forms an ohmic junction necessary for the operation of a Schottky gate field effect transistor as a thick electrode in the depth direction, thereby realizing a FET with a small occupied area without increasing the irregularities caused by the electrode on the surface of the substrate. The essential element is a structure that can be formed.

The present invention will be explained in more detail below based on the drawings.

An example of a procedure for manufacturing a Schottky gate field effect transistor having the above-described ohmic electrode structure is shown in FIG.

For example, as a substrate material, Cr-doped semi-insulating GaA
An s-substrate 31 is used. First, mesa marks used for alignment are etched onto the substrate using a resist pattern as a mask. (Figure (a)) After forming the mesa mark,
For example, ion implantation is performed using a resist as a mask to form the active layer 32 with a uniform thickness at a desired position. (Same figure (
b)) The carrier concentration of this active layer and the active layer thickness are selected to achieve the desired pinch-off voltage.

For example, in order to achieve a pitch-off voltage of 0.2V, an active layer with a carrier concentration of 10"an" and a thickness of about 0.1 μm is required, so Si+ ions are implanted with an energy of 1i0
Ion implantation is performed by selecting a KeV implantation amount of 2XlO"'dose/cm" (assuming the activation rate to be 100%).

After forming the active layer by ion implantation, etching is performed at desired positions on both ends of the active layer where source and drain electrodes are to be formed using a resist as a mask to form grooves 36.
form. ((C) in the same figure) Although both a wet method and a soft method can be used as the etching method, it was decided here that the wet method using a simple HF-based etchant was used. The depth of the etching is determined based on the desired dimension of the active layer in the depth direction, and in order to sufficiently reduce the electrical resistance of the electrode portion, for example, a conductive layer 37 connected to the active layer with a depth of 1 μm or more is formed. Assuming that the dimensions of the source and drain electrodes 9 are 1.5 .mu.m long and 3 .mu.m thick, a groove 3 .mu.m deep and 1.5 .mu.m long is formed by etching.

Next, using the resist used for etching as a mask, ions are implanted from an oblique direction (FIG. 2(d)), thereby forming a conductive layer 37 on the side surface of the groove formed by etching, continuous with the above-mentioned active layer. be able to.

After forming the conductive layer, the ohmic metal is subsequently lifted off. For example, after depositing an AaGe Ni alloy using a resist as a mask, excess deposited film is removed. Then, annealing is performed at 4.00°C for 5 minutes in an N2 atmosphere, and ohmic contacts 33, 34. form. ((e) in the same figure) Once the ohmic contact is formed, the upper metal 38 is deposited to a desired thickness in order to lower the source/drain electrode resistance to a value required for the operating characteristics of the device. ((f) in the same figure) In this case, for example, At is deposited to a thickness of 3 μm so that the electrode has the same electrical resistance as a generally used electrode with a source length of 5 μm and a thickness of 1 μm.

After forming the ohmic metal as described above, the gate electrode 35 is deposited. After wiring, a Schottky gate field effect transistor is manufactured. ((f) in the same figure) An example of a Schottky gate field effect transistor having an ohmic junction in the direction perpendicular to the substrate and its manufacturing procedure have been shown above. However, the present invention is characterized in that the active layer and a portion of the ohmic contact are formed in the depth direction of the substrate, and is not limited to the structure shown in the above embodiment. do not have.

-1 Perform etching in the vertical direction. Although an embodiment has been shown in which both the source electrode and the drain electrode form an ohmic contact in the vertical direction to the substrate, in other cases, the ohmic contact of either the source electrode or the drain electrode is formed in the depth direction of the substrate. In particular, it is more practical to consider the case where only the ohmic contact portion of the source electrode is formed with a conductive layer and an ohmink contact deep above the substrate surface to connect to the active layer. Furthermore, it should be noted that using the etched surface as the side surface of the groove for the ohmic contact increases the area occupied by the electrode, but is advantageous in processes such as oblique ion implantation and vapor deposition on the side surface.

The structure in this case is shown in Figure 4. 4.1 in the figure
4 is a GaAs substrate, 42 is an active layer, 4.3 is a source electrode 44 is a drain electrode, and 45 is a gate electrode.

[Industrial applicability]

As described above, according to the present invention, by forming the ohmic junction necessary for the operation of the Shozotoki gate field effect l/landisk as a thick electrode in the depth direction, it is possible to avoid increasing the unevenness caused by the electrode on the substrate surface. A FET structure with a small footprint can be formed, and the operating speed is fast.
A MESFET with no deterioration in element characteristics can be created.

In the above embodiments, GaAs is used as the semiconductor crystal, but if necessary, InP or other crystals may be used.
Any semiconductor such as a group compound semiconductor or Si can be used.

In the example, the present invention can be applied to integrated circuits using this type of device, as well as LSI and VLSI. It is clear that the effects of the present invention function more effectively as the technology progresses.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing a MESFET with a conventional structure;
FIG. 2 shows an example, and FIG. 3 shows the MESFET of the present invention.
The processing process diagram and FIG.

Claims (1)

[Claims] In a Schottky gate field effect transistor having a semiconductor active layer formed on a semiconductor substrate, at least one of the source electrode and the drain electrode is formed at a position deeper than the surface of the substrate. Schottky gate field effect transistor characterized in that a portion is formed in the depth direction of the active layer