JPS62204578A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To prevent the lateral diffusion of an impurity due to an ion-implanted layer and the generation of leak from a substrate by a method wherein a temporary gate pattern is formed on a channel layer, sidewalls are formed on the side surfaces of the temporary gate pattern, high-concentration conductive layers are grown and the temporary gate pattern only is selectively removed. CONSTITUTION:An oxide film is formed on the surface of a channel layer 5, the oxide film is processed by dry etching and a temporary gate pattern 6 is formed. Then, its whole surface is covered with a sputtered Si nitride film and dry etching is performed to leave sidewalls 8 on the side surfaces of the temporary gate pattern 6. High-concentration conductive layers 9a and 9b are grown on the channel layer 5. After that, a gate opening 13 is provided inverting the pattern and a gate electrode 1 consisting of aluminum Al is provided. Then, by dry etching is removed a nitride film 10 which is used as an inversion film on the high-concentration conductive layers 9a and 9b, and a source electrode 2 and a drain electrode 3, which consist of ohmic metals, Au, Ge and Ni, are provided 2mum away from the gate electrode 1.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a field effect I transistor.
In particular, the present invention relates to a method of manufacturing a junction gate field effect transistor having a high concentration growth layer adjacent to a gate portion.

[Conventional technology]

Compound semiconductors, represented by GaAs, are characterized by higher electron mobility than Si, and research and development are being actively conducted to apply them to ultra-high-speed integrated circuits. Here, a GaAs Schottky barrier gate field effect transistor (hereinafter referred to as MESFET) will be explained as an example.4 A method for manufacturing this MESFET is proposed in Japanese Patent Laid-Open No. 15978/1983. 6Figure 3(a)
-(h) are cross-sectional views of the element in main steps shown in the order of steps to explain this manufacturing method.

First, as shown in FIG. 3 (a), Si+ is applied to a semi-insulating GaAs substrate 4 at an acceleration voltage of 30 keV and a dose of 2X 1.
At 012 am-2, ions were implanted to completely form the 'r't' channel layer 5, and then, as shown in FIG. 3(b),
A silicon oxide film of 0.8 μm is vapor-phase grown on this substrate 4, and e) the oxide film is etched by parallel plate dry etching using the resist film as a mask, and the gate length is 1.0.
Temporary game patterns I to 6 of μm are formed. Next, as shown in FIG. 3(C), using the temporary gate pattern 6 as a mask, St+ was applied at an acceleration voltage of 100 keV and a dose of 3 x 10
"cm-2 ion implantation to form highly concentrated conductive layers 7a and 7b.
form. Next, as shown in FIG. 3(d), invert
As 110, the entire surface is covered with a silicon nitride film having a thickness of 0.3 μm, and the crystallinity of the channel layer 5 and high concentration conductive layers 7a and 7b is restored by heat treatment at 800° C. for 20 minutes in hydrogen. Next, as shown in FIG. 3(e), when the photoresist film 11 is applied to a thickness of 1.0 μm, the surface of the photoresist [11] becomes smooth, and the photoresist film 6 on the temporary gate pattern 6 is formed as shown in the figure. Become thin. Next, as shown in FIG. 3(f), the entire surface is etched by parallel plate dry etching using CF4 gas to expose the temporary gate I to pattern 6 of the oxide film. Next, as shown in FIG. 3 (g>), the remaining photoresist film 11 is removed using a stripping solution, and then the oxide film 6 of the temporary gate pattern is removed using a buffered hydrofluoric acid solution.
is removed to form a gate opening 13. Next, see Figure 3 (
As shown in h), a gate electrode 1 made of aluminum is provided in the gate opening 12, and a source electrode 2 made of ohmic metal Au-Ge:Ni is provided on the high concentration conductive layers 7a and 7b. drain electrode 3
is formed to complete the MESFET.

A feature of this conventional manufacturing method is that since the gate electrode 1 can be formed after high-temperature heat treatment, there is a large degree of freedom in selecting the gate electrode.

[Problem that the invention seeks to solve]

To increase the mutual conductance (gm) of a FET, shorten the gate length and increase the resistance (gm) between the source and gate electrodes.
(source resistance) needs to be reduced. However, it is difficult to activate the highly doped conductive layer formed by ion implantation to 8×1017C111 or more under normal annealing conditions such as in this conventional example, and in order to lower the source resistance, the highly doped conductive layer is As the thickness becomes deeper and thicker, lateral diffusion of implanted impurities under the gate and substrate leakage current increase, resulting in poor drain current saturation and reduced mutual conductance.

An object of the present invention is to provide a field effect transistor that has good drain current saturation and mutual conductance even when the gate length is shortened.

[Means for solving problems]

The field effect transistor of the present invention includes a step of forming a channel layer serving as a field effect transistor portion on a semiconductor substrate, a step of forming a temporary gate pattern for determining a gate shape on the channel layer, and a step of forming the temporary gate pattern on the channel layer. forming a sidewall on the side surface of the temporary gate pattern; growing a highly concentrated conductive layer on the channel layer using the temporary gate pattern and the sidewall as a mask; and covering the surface of the semiconductor substrate with a coating film above the temporary gate pattern. and selectively removing only the temporary gate pattern to form a gate opening in the covering film, and forming a gate electrode in the gate opening.

[Effect]

The manufacturing method of the present invention eliminates lateral diffusion and substrate leakage caused by the ion implantation layer by stacking a high concentration layer on the channel layer by vapor phase growth.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. FIGS. 1(a) to 1(f) are cross-sectional views of a device in main manufacturing steps shown in the order of steps for explaining the first embodiment of the present invention.

First, as shown in FIG. 1(a), a channel layer 5 with a carrier density of 2 x 1012 cm-' and a thickness of about 50 nm is formed on a semi-insulating GaAs substrate 4 by ion implantation or molecular beam crystal growth. . Then, an oxide film is formed on the surface, and the oxide film is processed by parallel plate dry etching using the HoleRegister I-film as a mask to a height of 0.87 tm.
, a temporary gate pattern 6 having a gate length of 0.3 μm is formed.

Next, as shown in FIG. 1(b), the entire surface has a thickness of 0 and an IJ
IM is covered with a sputtered silicon nitride film, and parallel plate dry etching is performed using CF4 scraps, leaving a uniform wall 8 of 0.1 μm thick on the side surface of the temporary gate pattern 6.

Next, as shown in FIG. 1(C), GaA
After cleaning the surface, a highly concentrated conductive layer 9 with a carrier density of 1.2 x 1018 cm-3 is formed by metal organic vapor phase epitaxy.
Thickness rl, 3 no.
m grow.

The growth conditions at this time were: arsine (^5H3): trimedel potassium (TMG): hydrogen sulfide (H2S) = 7:
With a gas ratio of 120.04, the growth temperature is 620°C. Here, 112s is a carrier dopant gas.Next, as shown in FIG. 1(d), a sputtered silicon nitride film with a thickness of 0.3 μm is provided on the entire surface as an inversion film 10.

Thereafter, as shown in FIG. 1(e), the pattern is reversed and a gate opening 13 is provided as in the prior art example.

Next, as shown in FIG. 1(f), a gate electrode 1 made of aluminum is provided in the gate opening 13. Then, the nitride film 10 as an inversion film on the high concentration conductive layers 9a and 9b is removed by parallel plate dry etching, and the high concentration conductive layer 9a is removed by parallel plate dry etching.
, 9b, a source electrode 2 and a drain electrode 3 of ohmic metal ^u -Ge:Ni are placed 2 μm apart from the gate electrode 1.
The MESFET of the first embodiment is completed.

The FET characteristics obtained by this first example are as follows:
Game 1 - L threshold voltage Vt - 0.9V (standard deviation 60
mV>, the transconductance at day 1 to voltage OV g m = 340 m S , / am ,
Source resistance R5 = 0.5Ω・Dragon, gate reverse breakdown voltage - BVG
=6V. Further, the train feedback rate γ=-QVT/FVo, which indicates the saturation property of the drain current, was 0.04.

In the conventional method, when a high concentration layer is formed by ion implantation and the gate length is 0.3 μm, at VT = -1, 0, standard deviation is 130 mv, gm = 230 m S/mm,
Rs = 0.7Ω-IIl, -BVG: 4V.

γ-0.12.

Thus, it can be seen that in this method, the standard deviation of the gate threshold voltage, the source resistance Rs, and the drain feedback factor γ are reduced, and the mutual conductance gm and the gate reverse breakdown voltage -BV are improved.

Another effect of forming a highly concentrated conductive layer using vapor phase growth is that it can provide a higher carrier density than when using ion implantation. The peak carrier density of the high concentration layer formed by conventional ion implantation is 7 x 1017c11-.

However, the high concentration layer formed by the metal organic vapor phase epitaxy method in the example is as high as 1.2 x 1018 cm-2, and can have a uniform concentration distribution in the growth direction, and the source resistance R5
will go down.

As the vapor phase growth method for the high concentration layer, although the organic metal vapor phase growth method has been explained, a halide transport method or the like may be used.

Next, an embodiment of the pond of the present invention will be described.

The embodiments so far have mainly used MESFETs, but are not limited to this. Next, an example in which the present invention is applied to a two-dimensional electron gas type field effect transistor will be described. FIGS. 2(a) to 2(c) are cross-sectional views of a device shown in order of process for explaining a second embodiment of the present invention.

First, as shown in FIG. 2 (a), an undoped GaAs layer (
Channel layer) 21 was grown to a thickness of 1.0 μm, and continued]
'i x 1018cs-3 Si-doped Ga
An IAs electron supply layer 22 is grown to a thickness of 40 nm.

Next, as shown in FIG. 2 (1)), a temporary gate pattern 6 with a height of 0.8 μm and a gate length of 0.3 μm was formed in the same manner as in the first embodiment, and a parallel plate using CF4 gas was formed. A side wall 8 of a nitride film having a thickness of 0.1 μm is provided by dry etching the mold. Thereafter, the GaAJ?As layer 22 and the undoped GaAs layer 21 are etched to a thickness of 20 nm by parallel plate dry etching using CC(!4 gas).

Next, as shown in FIG. 2(c), after cleaning the semiconductor surface by organic cleaning, a 300 nm thick layer is grown on the undoped GaAs layer 21 with the high concentration conductive layers 9a and 9b exposed by organometallic vapor phase epitaxy. After this, the aluminum gate electrode 1 and ^u-Ge-N
i source electrode 2. A field effect transistor can be formed by providing a drain electrode 3.

Then, carriers are generated inside the undoped GaAs layer 21 by the GaAj'As electron supply layer 22 and a channel is formed, so the undoped GaAs layer 21 becomes a channel layer in the two-dimensional electron gas field effect transistor. .

The F E 'I' characteristic obtained by this second example is as follows at gate threshold voltage VT = 0.5 V:
Maximum transconductance g m = 480 m S
/ +u.

The source resistance R5 was a good value of 0.6Ω.

〔Effect of the invention〕

As explained above, according to the present invention, by stacking a highly concentrated conductive layer on a channel layer by vapor phase growth, lateral diffusion and substrate leakage are reduced, and saturation of drain current and variations in gate threshold voltage are reduced. Furthermore, since vapor phase growth allows higher carrier density than ion implantation, source resistance can be lowered and mutual conductance increased.

Furthermore, in the present invention, since the gate electrode is formed later, the gate resistance can be lowered by using a thick material with low resistivity for the gate electrode.

[Brief explanation of drawings]

1(a) to 1(f) are cross-sectional views of the element in main steps shown in the order of steps for explaining the first embodiment of the present invention, and FIG.
Figures (a) to (c) are cross-sectional views of the element in the main steps shown in order of process to explain the second embodiment of the present invention, and Figure 3 (
a) to (h) are cross-sectional views of elements in main steps shown in the order of steps to explain a conventional MESFET manufacturing method; 61...gate electrode, 2...source electrode, 3...
Drain electrode, 4... Semiconductor substrate, 5... Channel layer, 6... Temporary gate pattern, 7a, 7b, 9a, 9
b- High concentration conductive layer, 8... Side wall, 10... Inversion film (coating film) 11... Resist film, 12... Inversion pattern, 13... Gate opening. 76 Reversal job $ / 2nd fig. 3 fig.

Claims (1)

[Claims] A step of forming a channel layer that will become a field effect transistor section on a semiconductor substrate, a step of forming a temporary gate pattern for determining a gate shape on the channel layer, and a step of forming sidewalls on the sides of the temporary gate pattern. a step of growing a highly doped conductive layer on the channel layer using the temporary gate pattern and sidewalls as a mask; and a step of covering the surface of the semiconductor substrate with a coating film and removing the coating film above the temporary gate pattern. A method for manufacturing a field effect transistor, comprising the steps of: selectively removing only the temporary gate pattern to provide a gate opening in the coating film; and forming a gate electrode in the gate opening.