JPS6184869A - Semiconductor device - Google Patents

Abstract

PURPOSE:To form excellent gate electrodes of which threshold voltage can be controlled by the external electrodes, by a method wherein the first semiconductor layer is doped n type, second one very weak p type or n type, and third one p type; then, the third, second, and first semiconductor layers are formed and immediately coated continuously with metals to be exposed to the air. CONSTITUTION:A p type GaAs layer 20 is formed by burial in a semi-insulation GaAs substrate 10 at the part immediately under the gate electrode of an element to serve as the E-FET in the future; successively, an undoped GaAs layer 11 is formed, and an n type AlxGa1-xAs layer is grown by growing undoped AlxGa1-xAs. At this time, the buried p-layer 20 is kept floating or is provided with a control electrode so as to impress voltage thereon from outside. In such a construction of E-FET, many FETs having the buried p-layer under the gate by connecting only the necessary part of the p type buried layer in the substrate 10 with a p type GaAs layer can be controlled in threshold value by impressing external potentials.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method of manufacturing a field effect transistor using a heterojunction, and particularly to a method of manufacturing a transistor suitable for threshold control technology and gate electrode formation.

[Background of the invention]

A cross-sectional structural diagram of a conventional selectively doped heterojunction FET is shown in FIG.
No. 86. The basic structure is semi-insulating GaAs
On the substrate 10, undoped GaAs 11 is deposited to a thickness of about 1 um.
Undoped AQ, Ga1-. As(x = 0, 3
) layer 12 with 60 people, n-type AQ, Ga, , As (x-0
, 3) layer 13 by 400 people, n-type GaAs layer 14 by about 200 people, MBE (Molaeulas Beam)
Epitaxy) or OM-VPE method (Organi
c 1Letal Vapor Pose Dep
After crystal growth, a gate electrode 15 and source/drain electrodes 16 and 16' are formed. Enhancement type FET (E-FET) and depletion type FE
The T (D-FET) is made with n-type Ga in the top layer.
A method has been used in which the As layer 14 is selectively etched by dry etching and the gate metal 15' is deposited on the AQ, Ga□-, and As layers.

However, this method of manufacturing E/D FETs causes deterioration of the AID, GaL-, and As layers due to dry damage.
A problem has arisen in that a good gate electrode cannot be formed.

In addition, GaAs+AuwGa□- and As have very active surfaces and are immediately contaminated with impurities, oxidation, etc. when exposed to the atmosphere, causing defects in gate electrode formation.

On the other hand, the threshold voltage V th of this FET is the undoped G
If we ignore the term generated from the a A s layer, we get (however, E-FET) φ1. is the Schottky barrier height at the gate electrode.

dE is the amount of energy discontinuity in the conduction band of the heterojunction, q: unit charge, t: dielectric constant, N: concentration of Ni donor toping, d: thickness of n-type AQGaAs layer.

By the way, when this FET is used in an integrated circuit (IC), threshold control of the E-FET becomes the biggest problem. When applying the MBE or OM-VPE method, variations in film thickness occur between lots, resulting in a significant reduction in integrated circuit yield.

In other words, when applied to an IC, the thickness d is calculated from equation (1).
requires controllability of ±5 people within the plane.

To summarize the above, the biggest problems with this FET are (1) the value of vfk is determined at the time of crystal growth;

(2) Since the gate electrode is formed after exposure to crystal growth techniques, gate electrode defects are likely to occur.

[Purpose of the invention]

An object of the present invention is to provide a method for manufacturing a selectively doped heterojunction FET in which the threshold voltage V Th can be controlled by an external electrode and a gate electrode can be formed favorably.

[Summary of the invention]

Having a structure that allows the voltage V y b to be adjusted externally after crystal growth eliminates the strong limitation on crystal growth technology, that is, the need to control the film thickness with an accuracy of 1% from lot to lot. I can do it. MBE method The M-VPE method has extremely excellent in-plane uniformity due to the principle of crystal growth.

On the other hand, the gate electrode is formed using GaAs, in which Ga, As, and AQ are removed during crystal growth using the MBE method.

Apart from the AQ, Ga, -mAs growth chamber, another ultra-high vacuum chamber is provided in which the wafer can be transferred in an ultra-high vacuum, and gate electrode metals such as Ti, Mo, AQ, etc.
, WS i, etc. are deposited in an ultra-high vacuum of about 10 −1 torr.

On the other hand, in the OM-VPE method, after crystal growth, metal carbonyl forceps, such as W(Go)6, Mo(Go), etc., and organic metals such as their derivatives are thermally decomposed without being exposed to the atmosphere. Gate 1! Extreme metals can be grown all over the wafer.

By the way, Gate 1 without exposing it to the atmosphere! In the above method of forming poles, E -F E T and D-
The problem is how to make different FETs.

The feature of the present invention is that E-FET and D-FET are
An object of the present invention is to provide a method for controlling a semiconductor device in which gate electrode metal can be formed separately, and gate electrode metal can be formed without exposing it to the atmosphere.

The method for manufacturing a semiconductor device according to the present invention will be explained below with reference to FIG.

A p-type GaAs substrate is placed directly below the gate electrode of an element that will become an E-FET in the future in the semi-octagonal GaAs substrate 10.
The layer 20 is buried, and then MBE or O
Undoped GaAs layer 11 using M-VPE method
and around 60 undoped AQ, Ga,,As
, (x~0.3~0.37) to grow n-type AQ, G
Let a,−,As (x~0.3~0.37) grow in the range of 100 to 700 people.

At this time, the buried type 2 layer 20 is left floating, or a control electrode is formed so that a potential can be applied from the outside.

Normally, the p-layer is reverse biased, and the related FET
can be an E-FET. In this way E-F
When configuring an ET, by connecting only the necessary parts of the buried p-type layer in the semi-insulating GaAs substrate 10 with the p-type buried GaAs layer, a large number of FETs having two buried layers under the gate can be converted into an E-FET. The threshold value can be controlled by applying an external potential. FETs that are desired to have the same threshold value V a within a wafer can be adjusted by connecting p-type buried layers with each other through p layers and applying an external potential to the p layer to -V y b.

In this way, the controllability of the film thickness applied to the n-type AQGaAs layer 13 can be made considerably looser.

That is, in this case, the threshold value control is only for the D-FET.

In the present invention, gate gold g15 is grown without exposing n-type A Q Ga As Ml 13 to the atmosphere immediately after growth.
form. A feature of the process of the present invention is that when the MBE method is used, the sample is usually moved to another chamber in an ultra-high vacuum after the epitaxial growth layer is formed, and a gate metal is deposited in an ultra-high vacuum. On the other hand, when the epitaxial layer is grown using the ○M-VPE method, metal carpol, that is, w(
The gate metal is formed using an organic or thermal decomposition method of co)s or Mo('Go)s.

The method for forming the gate electrode is to form the gate region using normal photolithography (FIG. 2b).

Next, source/drain electrodes 16 are formed, and electrodes connected to the buried p-type Mho are formed.

The buried p-type layer can also be used to adjust the threshold voltage of the D-FET, VTk.

The p-layer of the present invention takes full advantage of the properties of the semi-insulating GaAs substrate. That is, by embedding the p-layer in a semi-insulating substrate, the associated buried pFfiF
can all be at the same potential. In this way, the p-layer can be used as a buried wiring in a semi-insulating substrate.

In the process of depositing gate metal without exposure to the atmosphere, metal can be deposited not only on AQ, Ga and As, but also on n-type GaAs.

When a reverse bias is applied to the p-type layer, a small amount of leakage current occurs, creating a potential difference in the p-type layer within the wafer.
In this case, external III control terminals may be provided at multiple locations within the wafer to maintain the same potential.

[Embodiments of the invention]

The present invention will be explained in more detail below through Examples.

Example I An example using the MBE method is shown in FIG.
3,000 people arrive at the 17th. Next, a 1.5 μm photoresist was applied, and the portion corresponding to the bottom of the gate region of the E-type FET was removed as shown in FIG. 3(a).
was ion-implanted at a dose of IX 10"d at an acceleration voltage of 200h. After removing the photoresist, 5in2 was implanted at a dose of 20"
00 people and annealing was performed at 900° C. for 20 minutes in an H2 atmosphere.

At this time, the p-type GaAs layer 20 had a doping concentration of 10''cn-'.Next, Sin was removed using a mixed solution of hydrofluoric acid and ammonium fluoride.

Next, an undoped GaAs layer (
GaAs layer (which does not intentionally contain impurities) 11 is 1μ
It grew to about m. Next, undoped A Q-G
A 1-A s layer 12' (x-Q, 3) was grown by about 60 people, and an n layer doped with 2X IQ"cm-' of Si was grown.
300 people of the type AQwGa,,As(x~0.3) were grown. Normally, the thickness of the n-type A Qw Ga 1-A s layer is selected in the range of 100 to 500 layers, and the thickness is 7
It is used in the doping amount range of X 1017an-3 to 2
The AQ mixed crystal ratio X is selected in the range of 0.2 to 0.37. Subsequently, 10-”t of material was deposited from the epitaxial growth chamber.
The tube was transferred to a separate room at 10" torr using a transfer manipulator while maintaining an ultra-high vacuum of 10" torr.

Next, Mo was deposited on the entire surface of 1,500 people. As this gate metal, in addition to Mo, Ti, WSi, (tungsten silicide), WAQ (tungsten aluminum), etc. can also be deposited.

Next, gate electrodes 15' and 15' were formed by dry etching as masks for photoresistors 19 and 19'.

At this time, NF and N
Reactive ion etching was performed using a mixed gas of 2.

Next, use CVO@ to coat Sin as a protective film.

21 was formed, and 5 in 2 on the gate electrode portion and Sio 2 on the source/drain electrode region were removed by photolithography and etching.

Next, using photoresist, the source is
A drain electrode 16 was formed. FIG. 3(d) A u G e /N i /A u was used as the metal.

Here, the FET with the p-type buried layer 20 becomes an E-FET, and the FET without it becomes a D-FET.

Next, after forming the FET, a control hole 24 for forming an external electrode connected to the p-type region 20 is formed.

21, A<1. Gat-, As 13,12, Ga
This was done by etching A, S11 (Figure 3(e)). Note that FIGS. 3(a) to 3(d) are cross-sectional views, and FIG. 3(e) is a plan view of a portion centered on the gate portion. P type Ga As layer 2 through control hole 24
Electrodes 26 and 12 in ohmic contact with 0 were used. Third
In the figure (e), 25 is a mesa etching region for element isolation.

In order to change the threshold value by applying a reverse bias to the buried p-type layer in this manner, the breakdown voltage between the 9th layer 20 and the undoped layer 11 must be sufficiently large.

For this purpose, it is desirable that the carrier concentration in the p-type layer be as low as possible.

That is, it is preferable to use a p-type dopant concentration of about IQ"am-" (However, when controlling V Th with an external voltage, there is no strong restriction on the concentration).

If the impurity concentration in the p-type head region is too high, the impurity may diffuse during epitaxial growth and contaminate the undoped GaAs layer. Other p-type dopants include Be and Z.
n, Ge, etc.

Example 2 When using the 0M-VPE method, fill the shrimp in Figure 2.
, 12.13 are different in the method of forming the gate metal 15 except that they are formed by OM-VPE. That is, OM-V
As in Example 1, the undoped Ga As was 1 μm thick and the undoped A Q w was formed using the PE method at a substrate temperature of 650°C, as in Example 1.
G a 1- m A s layer (x = 0.3) at 60
Human-1n type AR, Ga, -, As (x=0.3.n-1
After growing 300 people each
The inside of the reaction tube is purged in an atmosphere of H, +AsH□ for about 2 minutes. Next, Mo(C○)G was introduced into the reaction tube with N2 as a carrier, and the temperature was 65°C, which was the same as the epitaxial growth temperature.
A pyrolysis reaction is carried out at 0°C, and about 1500 Mo thin films are deposited on the Ga + As growth layer at n-A°C.

As this gate metal, in addition to Mo, W, WS i, , W
AI2 etc. can also be deposited in a similar manner.

Next, the steps for forming the gate electrode and source/drain electrodes are the same as in the first embodiment.

By connecting a plurality of necessary transistors using a p-type buried layer and connecting them to an external control terminal through a contact hole, it has become possible to set the necessary threshold voltage v5 of the FET to almost the same value. For this reason, conventionally, NBE, ○M-
The lot-to-lot variation in V T II (mainly caused by lot-to-lot variation in film thickness and doping level), which had been a problem with the VPE method, could be extremely reduced. In this example, v7 between lots. The variation is σv,,=1
It was 0 mv.

The semiconductor device and its manufacturing method of the present invention can be applied to other compound semiconductors, InP-InGaAsP, InP-InGaAs,
InAs-InAsSb, GaAs-A Q GaA
sP, A El, Ga, -, As-A Q, Ga1-,
Of course, it is effective even when FETs are made using As or the like.

〔Effect of the invention〕

According to the present invention, after forming a p-type buried layer, a selective doper heterojunction structure is formed and a gate metal is deposited without exposing it to the atmosphere. (1) The threshold voltage can be determined by applying an external voltage after crystal growth. Can be adjusted. This made it possible to significantly increase the controllability of the threshold voltage.

(2) Since the gate electrode can now be formed without being exposed to the atmosphere, the stability of the gate electrode with respect to the threshold value has been greatly improved.

(3) By connecting the necessary FETs of an integrated circuit using a p-type buried layer, the characteristics of the extremely excellent in-plane film thickness uniformity of MBE and ○M-VPE methods can be maximized. became. That is, the threshold voltage VTk of the enhancement type FET can be externally controlled to a desired value, and the variance between lots can be reduced. =10mV.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view of a conventional selectively doped heterojunction FET, Fig. 2 is a process diagram showing the manufacturing process of the selectively doped heterojunction FET of the present invention, and Fig. 3 is a process diagram showing an embodiment of the present invention. be. DESCRIPTION OF SYMBOLS 10... Semi-insulating GaAs substrate, 11... Undoped GaAs layer, 12-... Undoped A
Q, Ga1-, As layer, 13-n type A Q, Ga,
-, As layer, 14- n-type Ga As layer, 16.
16'... Source/drain electrode, 15... Gate metal, 15'... Gate electrode of FET without P-type buried layer, 15'... Gate electrode of FET with P-type buried layer, 20 ... p-type buried layer, 21 ... insulator,
26... External control electrode ohmically connected to the P-type buried layer, 24... Contact hole, 25... Inter-element isolation region 6'fI 1 'A 2 mouth by mesa etching

Claims (1)

[Claims] 1. A first semiconductor layer and a second semiconductor layer are arranged to form a heterojunction; a second semiconductor layer and a third semiconductor layer are arranged to form a heterojunction; The electron affinity of the semiconductor layer is smaller than that of the second semiconductor layer, and at least one pair of electrodes electronically connected to the first semiconductor layer and means for controlling carriers generated near the heterojunction In at least one semiconductor device, the first semiconductor layer is N-type doped, and the second semiconductor layer is very weak P-type or very weak N-type (intentionally not doped with impurities or slightly doped). ) The third semiconductor layer is p-doped and is continuously coated with a metal for controlling carriers at the heterojunction interface without exposing it to the atmosphere immediately after forming the third, second, and first semiconductor layers. 1. A semiconductor device characterized in that the semiconductor device is made of 2. In the semiconductor device according to claim 1,
A semiconductor device characterized by having an external electrode connected to a third semiconductor layer and capable of controlling carriers near a hetero interface. 3. In the semiconductor device according to claim 1,
A region (buried layer) of the third semiconductor layer selectively doped in the substrate is formed, and a field effect transistor without a buried layer and a field effect transistor with a buried layer are formed on the same substrate under the gate electrode. A semiconductor device characterized by: 4. In the semiconductor device according to claim 1,
A semiconductor device characterized in that a plurality of semiconductor devices using a p-type buried layer (third layer) are interconnected within a substrate.