JPH0322526A - Manufacture of silicon carbide semiconductor device - Google Patents

Abstract

PURPOSE:To manufacture the title silicon carbide semiconductor device having excellent element characteristics by a method wherein a silicon carbide single crystal layer deposited on a semiconductor substrate is implanted with III group element ion; a p type layer is formed by thermoannealing process; the silicon carbide single crystal layer is implanted with V group element ion and thermoannealing processed again to form an n type layer. CONSTITUTION:A B ion implanted layer 3 and a P type ion implanted layer 4 are formed on the surface region of a undoped SiC single crystal layer 2 deposited on an Si single crystal substrate 1 by respectively implanting boron ion and successively P ion. Next, the B ion implanted layer 3 and the P ion implanted layer 4 are activated by thermoannealing process at specific temperature to form a p type layer 5 and an n type layer 6. successively, after vacuum-evaporating aluminum on the n type layer 6, an Al evaporated film 7 is formed on a specific region by photolithography. Next, the surface parts of the n type layer 6 and the p type layer 5 are etched away to form a mesa structure by reactive ion-etching process using the Al evaporated film 7 as a mask and then the Al evaporated film 7 is etched away. Finally, the p type layer 5 and the n type layer 6 with aluminum respectively vacuum-evaporated thereon are patterned using photolithography to form a p side electrode 8 and an n side electrode 9.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for manufacturing a silicon carbide semiconductor device. In particular, the present invention relates to a method of manufacturing a silicon carbide semiconductor device having a pn junction formed by ion implantation.

(Prior art) In addition to silicon (Si), gallium arsenide (GaAs)
) and gallium phosphide (GaP) (e.g., diodes, transistors, integrated circuits, large-scale integrated circuits, light-emitting diodes, semiconductor lasers, and charge-coupled devices) are widely used in various fields of electronics. It has been put into practical use.

Silicon carbide (SiC) has a wide forbidden band width (2.2~3.3e
V), and has the excellent characteristics of being extremely stable thermally, chemically, and mechanically, and resistant to radiation damage. Semiconductor devices using conventional semiconductor materials such as silicon are difficult to use, especially under harsh conditions such as high temperatures, high-power driving, and radiation exposure. Therefore, semiconductor devices using silicon carbide. Applications in a wide range of fields are expected as semiconductor devices that can be used even under such harsh conditions.

However, it has a large area. Moreover, no crystal cutting technology has been established that can stably supply high-quality silicon carbide single crystals on an industrial scale with productivity in mind. therefore. Although silicon carbide is a semiconductor material that has many advantages and possibilities as described above, its practical application has been hindered.

Traditionally, on a laboratory scale, silicon carbide single crystals have been grown using, for example, the sublimation recrystallization method (Rayleigh method), and the silicon carbide single crystals obtained by this method have been used as a substrate and then grown using the vapor phase crystallization method (Raley method).
By elongating a silicon carbide single crystal layer epitaxially using a CVD method (CVD method) or a liquid phase epitaxial growth method (LPE method), a silicon carbide single crystal of a size that allows trial production of semiconductor devices is obtained.

however. With these methods, the area of the single crystal obtained is small. It is difficult to control its size and shape with high precision. Furthermore, it is not easy to control the crystal polymorphism and impurity concentration of silicon carbide.

In order to solve these problems, the present inventors proposed a method of growing a high-quality silicon carbide single crystal with a large area in the vapor phase on an inexpensive and easily available silicon single crystal substrate ( JP-A-59-203799).

In this method, impurities are added when silicon carbide is grown in the gas phase. It is possible to control the impurity concentration and conductivity type in the obtained silicon carbide single crystal. and. This method utilizes a silicon carbide single crystal layer formed on a silicon substrate. Methods for manufacturing various semiconductor devices (for example, diodes and transistors) have been developed (Japanese Patent Application Nos. 58-246511, 1982-249981, and 1982-252157).

Conventionally, in these various silicon carbide semiconductor devices, a +pn junction has been used as a method of electrically isolating the element shape region from the semiconductor substrate. As a method to form a pn junction. For example, in the above-mentioned gas phase precept method. A method of forming a p-type layer and an n-type layer by adding appropriate impurities when lengthening a silicon carbide single crystal layer. There is a method of forming an n-type layer (or a P-type layer) in a predetermined region by implanting impurity ions into a p-type layer (or an n-type layer) obtained by a vapor phase method.

however. In such a method, many crystal defects occur in the p-type layer and n-type layer that make up the pn junction. Furthermore, it is difficult to define the p-type layer and the n-type layer in a stepped manner. therefore. In a semiconductor device having a pn junction formed by these methods, leakage current occurs when a reverse bias voltage is applied to the pn junction. Therefore, it is difficult to completely electrically isolate the device shape region from the semiconductor substrate, and good device characteristics cannot be obtained.

The present invention solves the above-mentioned conventional problems, and its purpose is to provide a silicon carbide semiconductor having a pn junction with sufficient rectification characteristics to electrically isolate an element formation region from a semiconductor substrate. An object of the present invention is to provide a method for manufacturing a device.

(Means for Solving the Problems) The present invention is a method for manufacturing a silicon carbide semiconductor device having at least one pn junction composed of a p-type layer and an n-type layer made of silicon carbide, the method comprising: a step of elongating a silicon carbide single crystal layer above; a step of implanting group Ⅰ element ions into the silicon carbide single crystal layer and performing a thermal annealing treatment to form the p-type layer; By implanting group III element ions into the single crystal layer and performing thermal annealing. and forming the n-type layer, thereby achieving the above object.

In the manufacturing method of the present invention, a p-n junction is formed.
Both the type layer and the n-type layer are formed by ion implantation. First, a silicon carbide single crystal layer is grown above a semiconductor substrate, and then predetermined impurity ions are implanted into the silicon carbide single crystal layer to form an ion implantation layer.

In this case, by appropriately adjusting the implantation conditions, an ion implantation layer having a predetermined impurity concentration and layer thickness can be obtained. The ions to be implanted to form a p-type layer are: Boron (B) ion. Group II element ions such as argonium (AI) ions and gallium (Ga) ions are used. n
Nitrogen (N) is used as the implanted ion to shape the mold layer.
ion. Group III element ions such as phosphorus (P) ions and arsenic (As) ions are used.

The resulting ion-implanted layer is. A thermal annealing treatment is then performed. Thermal annealing treatment. It is carried out at a temperature of about 1,000 to 1,400°C under an inert gas atmosphere (eg, 8R gas). By this thermal annealing treatment, the ion implantation layer is activated and becomes a p-type layer or an n-type layer.

The order in which the p-type layer and n-type layer forming the pn junction are formed is not particularly important. for example. Group II element ions (or Group V element ions) are implanted into a silicon carbide single crystal layer formed above a semiconductor substrate, without subsequent thermal annealing treatment. Inject group V element ions (or group ■ element ions). By applying thermal annealing treatment to both of the resulting ion-implanted layers. A p-type layer and an n-type layer can be formed at the same time. Alternatively, by implanting group I element ions (or group V element ions) into a silicon carbide single crystal layer formed above the semiconductor substrate and performing thermal annealing treatment, the p-type layer (or n-type layer) is first formed. Then, this P-type layer (
By implanting group V element ions (or group II element ions) into the layer (or n-type layer) and performing thermal annealing treatment again,
The n-type layer (or p-type layer) can be formed in stages.

(Function) By implanting predetermined impurity ions into the silicon carbide single crystal layer in this way, a p-type layer and an n-type layer can be formed in a stepwise manner. Moreover. Crystal defects do not occur at the joints, unlike when using the vapor phase method. A pn junction composed of such a p-type layer and an n-type layer has good rectification characteristics. The element formation region can be electrically isolated sufficiently from the semiconductor substrate. Therefore, various silicon carbide semiconductor devices obtained by the manufacturing method of the present invention have good device characteristics.

(Example) Examples of the present invention will be described below.

Figure 1(a) shows a pn junction diode which is an embodiment of the silicon carbide semiconductor device of the present invention. This pn junction diode was manufactured as follows.

First, as shown in Figure 1(b), vapor phase growth (CVO)
A non-doped SiC single crystal layer 2 was grown at 1,350° C. on a Si single crystal substrate 1 using the method. Next, use an ion implanter. By implanting boron ions (Ilu-) into the surface region of the non-doped SiC single crystal layer 2, and then implanting phosphorus ions (:llp"), a B ion-implanted layer 3 and a A P ion implantation layer 4 was formed.The implantation conditions were that the acceleration voltage was 200 keV and 100 keV, respectively, and the implantation amount of B ions and P ions was IXIO"c.
m-2 and 3 XIO"c"2.

and. By performing thermal annealing at approximately 1,000 to 1,300°C, the B ion-implanted layer 3 and P
Activate the ion implantation layer 4. A p-type layer 5 and an n-type layer 6 as shown in FIG. 1(d) were formed.

Subsequently, aluminum (AL) is vacuum-deposited on the n-type layer 6. Using photolithography, apply it to a specified area ^l
The vapor deposited film 7 was formed. Using this AI vapor deposited film 7 as a mask, the n-type layer 6 and the surface portion of the p-type layer 5 are etched by reactive ion etching (RIIE) to form a meza structure as shown in FIG. 1(e). did. And, A
The I vapor deposited film 7 was removed by etching. Note that a phosphoric acid (H3PO4) solution was used for the etching step 6. lastly. After vacuum-depositing aluminum (AI) on the p-type layer 5 and the n-type layer 6, respectively, pakuning is performed using photolithography to form the p-side electrode 8 and the n-side electrode 9. p as shown in figure (a)
An n-junction diode was obtained.

For comparison, B ion-implanted layer 3 and P ion-implanted N
4, the conventional pn junction was formed in the same manner as in the above embodiment except that a pn junction was formed by using a silicon carbide single crystal layer which was grown in the vapor phase while adding boron impurities and phosphorous impurities, respectively. A junction diode was fabricated.

The pn junction diode of this example obtained in this way and the conventional pn junction diode are as follows. The current-voltage characteristics were investigated. The results are shown in FIGS. 2 and 3, respectively. Note that the solid line indicates the current-voltage characteristic at room temperature, and the dotted line indicates the current-voltage characteristic at 300°C.

As is clear from these figures. The pn junction diode of this example has a p-type layer implanted with Bq l0 ions and a p-type layer implanted with Bq l0 ions. Since a pn junction is formed from the n-type layer into which P ions are implanted, leakage current is significantly reduced compared to conventional pn junction diodes, and stable rectification characteristics are obtained, especially up to the high a region.

Figure 4(a) shows an insulated gate field effect transistor (MOS) which is another embodiment of the silicon carbide semiconductor device of the present invention.
FET). This MOSFET was manufactured as follows.

first. As shown in Figure 4(b), vapor phase growth (CVD)
A non-doped SiC single crystal layer 12 was grown at 1,350°C on a Si single crystal substrate 11 by a method. Next, aluminum ions (Z7AI-) are implanted into the surface region of the non-doped SiC single crystal layer 12 using an ion implantation device. An AI ion-implanted layer l3 as shown in FIG. 4(C) was formed. The injection conditions are as follows. The accelerating voltage was 200 keV, and the amount of AI ions implanted was IXIOI5cnr2, respectively.

Then, thermal annealing treatment is performed at 1,300°C. By. The old ion-implanted layer 13 is activated, and as shown in FIG.
A p-type layer 14 as shown in d) was formed.

continue. A SiOz film was formed on the p-type layer 14 by a CvD method or a plasma CVD method. Next, using photolithography, a predetermined region of the SiO film was opened by etching to form a field insulating film 15 (a fourth film).
Figure (e)). Note that hydrogen fluoride (HF) is used for etching.
A solution was used. and. Nitrogen ions ("N") were implanted into the open region of the p-type layer 14 using an ion implantation device and using the field insulating film 15 as a mask. The implantation conditions were an acceleration voltage of 50 keV and an implantation amount of N ions of 3×10
”cm~2. Then, about 1,000~1
, by thermal annealing at 200°C.
The N ion implantation region was activated to form a source region 16 and a drain region 17 made of an n-type layer as shown in FIG. 4(e).

Furthermore, after removing the field insulating film l5 in the portion corresponding to the gate region by etching, under an oxygen atmosphere,
By performing thermal oxidation at 1,100°C for 4 hours. The gate insulating film l8 was formed. lastly. After vacuum-depositing aluminum (AI) on the opening portions corresponding to the source region 16 and drain region 17 and on the gate insulating film 18 on the portion corresponding to the gate region. A MOSFET as shown in FIG. 4(a) was obtained by forming a source electrode 19, a drain electrode 20, and a gate electrode 2l using photolithography.

For comparison, a conventional MOSFET was fabricated in the same manner as in the above example except that a silicon carbide single crystal layer grown in a vapor phase while adding an aluminum impurity was used in place of the AI ion-implanted layer l3. Created.

The transistor characteristics (drain current vs. drain voltage characteristics) of the thus obtained MOSFET of this example and the conventional MOSFET were investigated. The results are shown in FIGS. 5 and 6, respectively. As is clear from these figures, in the MOSFET of this example, a p-n junction is formed from the p-type layer implanted with AI ions and the n-type layer implanted with N ions, so it is different from the conventional MOSPET.
The leakage current was significantly reduced compared to the previous model, and transistor characteristics showing good saturation of the drain current were obtained. Also,
Such good transistor characteristics were stable even in the high temperature range.

(Effects of the Invention) According to the present invention, the p-type layer and n
To shape the mold layer using ion implantation. A silicon carbide semiconductor device in which the element formation region is sufficiently electrically isolated from the semiconductor substrate and has good element characteristics can be obtained. Such silicon carbide semiconductor devices can be used for various purposes. Since the device characteristics are stable up to a high temperature range, it is particularly useful as a semiconductor device for high temperature operation. Furthermore, since the present invention utilizes ordinary ion implantation technology, it is possible to produce various silicon carbide semiconductor devices (for example, pn junction diodes, gate insulated field effect transistors, etc.) on an industrial scale. Become.

4. Figures 1 (a) to (e) are cross-sectional views for explaining the manufacturing process of a pn junction diode, which is an embodiment of the silicon carbide semiconductor device of the present invention, and Figure 2 is a cross-sectional view of the pn junction diode, which is an embodiment of the silicon carbide semiconductor device of the present invention. A diagram showing the rectification characteristics of a junction diode. FIG. 3 shows the rectifying characteristics of a pn junction diode manufactured by a conventional method. FIGS. A cross-sectional view for explaining the manufacturing process, FIG. 5 is a diagram showing the device characteristics of the insulated gate field effect transistor, and FIG. 6 is a diagram showing the device characteristics of the insulated gate field effect transistor manufactured by the conventional method. It is a diagram.

1.11... Si single crystal substrate, 2.12... Non-doped SiC single crystal layer, 3... B ion implantation layer, 4...
・P ion implantation layer, 5.14...p type layer, 6...n
Mold layer, 7... AI vapor deposited film, 8... p-side electrode, 9...
・N-side electrode, 13...AI ion implantation layer. 15...
Field insulating film, 16...source region (n-type layer)
, 17... drain region (n-type layer). 18... Gate insulating film, 19... Source electrode, 20... Drain electrode, 21... Gate electrode.

that's all

Claims (1)

[Claims] 1. A method for manufacturing a silicon carbide semiconductor device having at least one pn junction composed of a p-type layer and an n-type layer made of silicon carbide, the method comprising: placing a silicon carbide single crystal above a semiconductor substrate; a step of growing a layer, a step of forming the p-type layer by implanting group III element ions into the silicon carbide single crystal layer and performing a thermal annealing treatment; A method for manufacturing a silicon carbide semiconductor device, comprising: forming the n-type layer by implanting ions and performing thermal annealing.