JPS63148616A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63148616A JPS63148616A JP29469886A JP29469886A JPS63148616A JP S63148616 A JPS63148616 A JP S63148616A JP 29469886 A JP29469886 A JP 29469886A JP 29469886 A JP29469886 A JP 29469886A JP S63148616 A JPS63148616 A JP S63148616A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor layer
- semiconductor
- gallium arsenide
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 98
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims abstract description 33
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 31
- 239000010409 thin film Substances 0.000 claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 17
- 239000010703 silicon Substances 0.000 claims abstract description 17
- 239000013078 crystal Substances 0.000 claims abstract description 14
- 229910000673 Indium arsenide Inorganic materials 0.000 claims abstract description 7
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims abstract description 7
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 claims description 9
- 229910052732 germanium Inorganic materials 0.000 claims description 8
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 8
- 238000001704 evaporation Methods 0.000 claims description 7
- MDPILPRLPQYEEN-UHFFFAOYSA-N aluminium arsenide Chemical compound [As]#[Al] MDPILPRLPQYEEN-UHFFFAOYSA-N 0.000 claims description 6
- 230000008020 evaporation Effects 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 239000010408 film Substances 0.000 abstract description 21
- 239000000758 substrate Substances 0.000 abstract description 12
- 238000001451 molecular beam epitaxy Methods 0.000 abstract description 11
- 238000005530 etching Methods 0.000 abstract description 6
- 229910052785 arsenic Inorganic materials 0.000 abstract description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052760 oxygen Inorganic materials 0.000 abstract description 5
- 239000001301 oxygen Substances 0.000 abstract description 5
- 239000003463 adsorbent Substances 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 235000012239 silicon dioxide Nutrition 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 5
- 239000007789 gas Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 1
- RAWGYCTZEBNSTP-UHFFFAOYSA-N aluminum potassium Chemical compound [Al].[K] RAWGYCTZEBNSTP-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000002109 crystal growth method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000005755 formation reaction Methods 0.000 description 1
- 150000004678 hydrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体層上に他の半導体層を形成し、所定の
工程を経た後さらに別の半導体層を形成する半導体装置
の製造方法に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, in which another semiconductor layer is formed on a semiconductor layer, and after a predetermined process, another semiconductor layer is formed. It is something.
高集積回路、半導体レーザ超高周波デバイス等の微細構
造を有する半導体装置を作成するにあたり、薄膜成長は
極めて重要な工程の一つである。Thin film growth is one of the extremely important steps in producing semiconductor devices with fine structures such as highly integrated circuits and semiconductor laser ultra-high frequency devices.
通常の半導体装置ではドーピングレベルや■−Ｖ族半導
体ではそれらの組成の異なる半導体層を少なくとも２層
以上積層した構造よりなり、それらの制御性は高いもの
でなけれならない。A normal semiconductor device has a structure in which at least two or more semiconductor layers having different doping levels and compositions for (1-V group semiconductors) are laminated, and these must be highly controllable.
ところで半導体層を形成後たとえば大気や超高真空中に
おいて一定時間の間装置した場合、大気や超高真空中に
おいても残留ガスにより半導体結晶の表面に酸素や炭素
等が吸着する。そして再び半導体層をその表面に形成し
た場合、吸着したガスは半導体中に取り込まれ不純物と
なる。その結果、たとえばｎ型半導体では半導体層界面
においてドナの個喝がおこり、したがって制御された半
導体層が得られない。By the way, if the device is left in the atmosphere or ultra-high vacuum for a certain period of time after forming the semiconductor layer, oxygen, carbon, etc. will be adsorbed onto the surface of the semiconductor crystal due to residual gas even in the atmosphere or ultra-high vacuum. When a semiconductor layer is formed on the surface again, the adsorbed gas is incorporated into the semiconductor and becomes an impurity. As a result, for example, in an n-type semiconductor, individual donors occur at the semiconductor layer interface, and therefore a controlled semiconductor layer cannot be obtained.
このような半導体層界面の清浄化の方法として、可能な
かぎり複数の半導体層を連続的に形成する方法がある。As a method for cleaning such semiconductor layer interfaces, there is a method of forming a plurality of semiconductor layers continuously as much as possible.
しかし半導体レーザや電界効果トランジスター等では、
大気中に取り出し半導体層の一部を加工し、再び半導体
層を形成しなければならない。ｍ−ｖ族化合物半導体結
晶形成法であるハイドライド（Ｈｙｄｒｉｄｅ）及びク
ロライド（Ｃ１ｏｒｉｄｅ）気相成長法では、ガスによ
るエツチングにより大気等により汚染された半導体表面
を除去し、その上に半導体層を形成する。しかし、これ
らの成長方法では除去する膜厚の制御性はよ（ない。ま
た、これらの結晶成長法ではアルミニウムを含むｍ−ｖ
族半導体を形成するには、アルミニウムと石英の反応を
抑えねばならずいまだ一般的でない。However, in semiconductor lasers, field effect transistors, etc.
It is necessary to take it out into the atmosphere, process a part of the semiconductor layer, and then form the semiconductor layer again. In the hydride and chloride vapor phase growth method, which is a method for forming m-v group compound semiconductor crystals, a semiconductor surface contaminated by the atmosphere is removed by gas etching, and a semiconductor layer is formed on it. . However, these growth methods do not provide good control over the thickness of the removed film.
In order to form group semiconductors, the reaction between aluminum and quartz must be suppressed, which is still not common.
ｍ−ｖ族化合物半導体の分子線エピタキシー（ＭＢＥ）
法では、結晶表面に砒素膜を形成することによりガリウ
ム砒素等のｍ−ｖ族半導体表面を保護する方法がとられ
る。しかしこの方法においても砒素膜により結晶表面を
保護するには基板温度を１００℃以下に下げねばならず
、結晶成長後基板温度が下がる間は基板表面は残留ガス
にさらされる可能性がある。さらに砒素は大気中の水分
と反応する可能性があり、大量に用いるには人体に害を
及ぼすおそれがある。Molecular beam epitaxy (MBE) of m-v group compound semiconductors
In this method, the surface of an m-v group semiconductor such as gallium arsenide is protected by forming an arsenic film on the crystal surface. However, even in this method, the substrate temperature must be lowered to 100° C. or less in order to protect the crystal surface with an arsenic film, and the substrate surface may be exposed to residual gas while the substrate temperature is lowered after crystal growth. Furthermore, arsenic can react with moisture in the atmosphere, and if used in large quantities, it may be harmful to the human body.
シリコンの分子線エピタキシー（ＭＢＥ）法ではシリコ
ンを大気中にさらした場合、二酸化硅素（Ｓ ｉ Ｏ，
）が形成され、再成長ではこの酸化膜を除去するため８
５０℃以上の高温にしなければならない。In silicon molecular beam epitaxy (MBE), silicon dioxide (S i O,
) is formed, and in order to remove this oxide film during regrowth, 8
The temperature must be 50°C or higher.
本発明の目的は、結晶のエツチング、砒素膜形成、さら
にシリコンの場合の酸化膜除去等の繁雑な方法を用いる
ことなく、清浄な界面を保ったまま半導体層を再形成す
る半導体装置の製造方法を提供することにある。The purpose of the present invention is to form a semiconductor device manufacturing method that re-forms a semiconductor layer while maintaining a clean interface without using complicated methods such as crystal etching, arsenic film formation, and oxide film removal in the case of silicon. Our goal is to provide the following.
本発明は、加熱昇温した第１の半導体層上に第２の半導
体層を設け、所定時間経過後に第３の半導体層を設ける
半導体装置の製造方法において、前記第２の半導体層を
形成した後連続して前記第２の半導体層よりも蒸発温度
の低い第４の半導体層である薄膜層を設け、所定の時間
経過後に前記第４の半導体層を加熱蒸発させた後に前記
第３の半導体層を設けることを特徴としている。The present invention provides a method for manufacturing a semiconductor device in which a second semiconductor layer is provided on a first semiconductor layer heated to an elevated temperature, and a third semiconductor layer is provided after a predetermined period of time has elapsed, in which the second semiconductor layer is formed. Subsequently, a thin film layer that is a fourth semiconductor layer having an evaporation temperature lower than that of the second semiconductor layer is provided, and after a predetermined time has elapsed, the fourth semiconductor layer is heated and evaporated, and then the third semiconductor layer is heated and evaporated. It is characterized by providing layers.
本発明によれば第２の半導体層はガリウム砒素あるいは
アルミニウム砒素あるいはこれらの混晶、薄膜層はイン
ジウム砒素とするのが好適である。According to the present invention, the second semiconductor layer is preferably made of gallium arsenide, aluminum arsenide, or a mixed crystal thereof, and the thin film layer is preferably made of indium arsenide.
また、第２の半導体層はアルミニウム砒素あるいはアル
ミニウム組成の大きいアルミニウムガリウム砒素、薄膜
層はガリウム砒素とするのが好適である。Further, it is preferable that the second semiconductor layer is made of aluminum arsenide or aluminum gallium arsenide with a large aluminum composition, and the thin film layer is made of gallium arsenide.
また、第２の半導体層はシリコン、薄膜層はゲルマニウ
ムとするのが好適である。Further, it is preferable that the second semiconductor layer is made of silicon and the thin film layer is made of germanium.
第２の半導体層上にこれより蒸発温度の低い第４の半導
体層である薄膜層を形成する。したがって半導体をたと
えば大気中に取り出して、たとえばある半導体加工工程
を施しても第２の半導体層は決して直接に大気には触れ
ない。そして再び第３の半導体層を形成する前にたとえ
ばＭＢＥ法では超高真空中で加熱して薄膜層を蒸発させ
る。このときの加熱温度は第２の半導体層の蒸発温度よ
りも低く、したがって薄膜層のみ除去される。このとき
大気中において薄膜層に吸着したものは同時に除去され
第２の半導体表面は大気の汚染の影響を受けない。そし
て薄膜層が除去された直後に第３の半導体層を形成する
。したがって第２及び第３の半導体層界面は清浄に保た
れる。A thin film layer as a fourth semiconductor layer having a lower evaporation temperature than the second semiconductor layer is formed on the second semiconductor layer. Therefore, even if the semiconductor is taken out into the atmosphere and subjected to, for example, a certain semiconductor processing step, the second semiconductor layer never comes into direct contact with the atmosphere. Then, before forming the third semiconductor layer again, for example, in the MBE method, the thin film layer is evaporated by heating in an ultra-high vacuum. The heating temperature at this time is lower than the evaporation temperature of the second semiconductor layer, so only the thin film layer is removed. At this time, substances adsorbed to the thin film layer in the atmosphere are simultaneously removed, and the second semiconductor surface is not affected by atmospheric pollution. A third semiconductor layer is then formed immediately after the thin film layer is removed. Therefore, the interface between the second and third semiconductor layers is kept clean.
尖旌脳上
第１図は第１の半導体層としてガリウム砒素基板１、第
２の半導体層としてシリコンの濃度が２×１０”ｃｎ＋
−ｆｆのｎ型がガリウム砒素Ｍ２、第３の半導体層とし
て同じくシリコンの濃度が２ Ｘ１０１６ｃｍ−’のｎ
型ガリウム砒素Ｈ３を形成する場合の実施例を示す各工
程の素子断面図である。Figure 1 shows a gallium arsenide substrate 1 as the first semiconductor layer, and a silicon concentration of 2 x 10''cn+ as the second semiconductor layer.
The n-type of -ff is gallium arsenide M2, and the third semiconductor layer also has a silicon concentration of 2 x 1016 cm-'.
FIG. 4 is a cross-sectional view of an element in each step showing an example of forming type gallium arsenide H3.
まず、ガリウム砒素基板１上にｎ型ガリウム砒素層２を
ＭＢＥ法により形成する（第１図（ａ））。First, an n-type gallium arsenide layer 2 is formed on a gallium arsenide substrate 1 by the MBE method (FIG. 1(a)).
このときの成長温度は５５０℃とした。次に、ただちに
表面保護膜（薄膜Ｎ）としてインジウム砒素Ｎ４を５０
０ Ａエピタキシャル成長する（第１図（ｂ））。その
後大気中に放置したところ、表面に酸素等の吸着分子５
が吸着しまた一部反応している（第１図（Ｃ））。そし
て再びＭＢＥ装置に導入して、６５０℃に加熱しインジ
ウム砒素層４を除去する（第１図（ｄ））。そして除去
後ただちにｎ型ガリウム砒素層３を形成する。The growth temperature at this time was 550°C. Next, immediately apply 50% of indium arsenide N4 as a surface protective film (thin film N).
0A epitaxial growth (Fig. 1(b)). After that, when left in the atmosphere, 5 adsorbed molecules such as oxygen appeared on the surface.
is adsorbed and also partially reacted (Fig. 1(C)). Then, it is introduced into the MBE apparatus again and heated to 650° C. to remove the indium arsenide layer 4 (FIG. 1(d)). Immediately after the removal, an n-type gallium arsenide layer 3 is formed.
第２図は実施例により作製した試料（ａ）と従来方法に
より結晶再成長を行った試料（ｂ）のドナ濃度の膜厚方
向の分布を示す。縦軸はドナ濃度を、横軸は膜厚方向の
距離を示す。破線は試料（ａ）のドナ濃度を、実線は試
料（ｂ）のドナ濃度をそれぞれ示している。試料（ａ）
では、ｎ型ガリウム砒素層２とｎ型ガリウム砒素層３と
の界面におけるドナの個喝はみられなかった。FIG. 2 shows the distribution of the donor concentration in the film thickness direction of the sample (a) prepared according to the example and the sample (b) subjected to crystal regrowth by the conventional method. The vertical axis shows the donor concentration, and the horizontal axis shows the distance in the film thickness direction. The broken line indicates the donor concentration of sample (a), and the solid line indicates the donor concentration of sample (b). Sample (a)
In this case, no individual donor chips were observed at the interface between the n-type gallium arsenide layer 2 and the n-type gallium arsenide layer 3.
以上の実施例では、第２の半導体層としてガリウム砒素
を用いたが、第２の半導体層はガリウム砒素あるいはア
ルミニウム砒素あるいはこれらの混晶であってもよい。In the above embodiments, gallium arsenide is used as the second semiconductor layer, but the second semiconductor layer may be gallium arsenide, aluminum arsenide, or a mixed crystal thereof.
大施炎１
第３図は第１の半導体層としてガリウム砒素基板１１及
びｎ型ガリウム砒素コレクタ層１２及びｐ型ガリウム砒
素ベース層１３、第２の半導体層としてアルミニウム組
成０．６のアルミニウムガリウム砒素層２０、第３の半
導体層としてアルミニウム組成が徐々に小さくなるアル
ミニウムガリウム砒素グレーデツト層３０を用いてヘテ
ロバイポーラトランジスタ（ＨＢＴ）を製造する場合の
実施例を示す各工程の素子断面図である。Large Flame 1 Figure 3 shows a gallium arsenide substrate 11, an n-type gallium arsenide collector layer 12, and a p-type gallium arsenide base layer 13 as a first semiconductor layer, and an aluminum gallium arsenide layer with an aluminum composition of 0.6 as a second semiconductor layer. 3A and 3B are device cross-sectional views showing each step of manufacturing a hetero-bipolar transistor (HBT) using an aluminum gallium arsenide graded layer 30 whose aluminum composition gradually decreases as a layer 20 and a third semiconductor layer.
まず、ガリウム砒素基＋ｔｆｆｊ １１、ｎ型ガリウム
砒素コレクタ層１２、ｐ型ガリウム砒素ベース層１３、
アルミニウムガリウム砒素層２０までの層を形成し、さ
らに表面保護膜（薄膜層）としてガリウム砒素層４０を
形成する（第３図（ａ））。次に、ベース層１３及びコ
レクタ層１２までメサエッチングを施し、二酸化硅素膜
９０を被覆する（第３図（ｂ））。次に、ガリウム砒素
層４０をＭＢＥ装置内で７５０℃で蒸発させ、アルミニ
ウムガリウム砒素グレーデツト層３０を形成する（第３
図（Ｃ））。そして、二酸化硅素膜９０のリフトオフ後
、エミッタ電極６０゜ベース電極７０．コレクタ電極８
０を形成しＨＢＴが完成する。First, gallium arsenide base +tffj 11, n-type gallium arsenide collector layer 12, p-type gallium arsenide base layer 13,
Layers up to the aluminum gallium arsenide layer 20 are formed, and a gallium arsenide layer 40 is further formed as a surface protective film (thin film layer) (FIG. 3(a)). Next, mesa etching is performed up to the base layer 13 and the collector layer 12 to cover the silicon dioxide film 90 (FIG. 3(b)). Next, the gallium arsenide layer 40 is evaporated at 750°C in an MBE apparatus to form an aluminum gallium arsenide graded layer 30 (third
Figure (C)). After lift-off of the silicon dioxide film 90, the emitter electrode 60° and the base electrode 70. Collector electrode 8
0 is formed and the HBT is completed.
本実施例によれば、グレーデソトエミソタ層形成後メサ
エッチングする従来の製造方法に比較して、ベース層及
びコレクタ層電極形成のためのメサエッチングの深さの
制御性が向上し、したがってＨＢＴの歩止まりが改善さ
れた。According to this example, compared to the conventional manufacturing method in which mesa etching is performed after forming a graded layer and a graded layer, the controllability of the mesa etching depth for forming the base layer and collector layer electrodes is improved, and therefore the HBT The yield rate has been improved.
以上の実施例では、第２の半導体層としてＡＩ！組成の
大きいアルミニウムガリウム砒素を用いたが、アルミニ
ウム砒素であってもよい。In the above embodiments, AI! is used as the second semiconductor layer. Although aluminum gallium arsenide having a large composition is used, aluminum arsenide may also be used.
ス４１江１
第１の半導体層としてシリコン基板、第２の半導体層と
してシリコンエピタキシャル層、第３の半導体層として
同じくシリコンエピタキシャル層、薄膜層としてゲルマ
ニウムを用いた場合の実施例を説明する。An example will be described in which a silicon substrate is used as the first semiconductor layer, a silicon epitaxial layer is used as the second semiconductor layer, a silicon epitaxial layer is used as the third semiconductor layer, and germanium is used as the thin film layer.
まず、ＭＢＥ法によりシリコン基板上にシリコン層を形
成した後、ただちに表面保護膜（薄膜層）としてゲルマ
ニウム層を形成する。その後大気中に取り出したところ
、大気中の酸素等がゲルマニウム層の表面に吸着される
。そして再びＭＢＥ装置に導入して、８００℃に加熱し
、ゲルマニウム層を除去する。除去後ただちにシリコン
層等を形成する。First, a silicon layer is formed on a silicon substrate by the MBE method, and then a germanium layer is immediately formed as a surface protection film (thin film layer). When it is then taken out into the atmosphere, oxygen and other substances in the atmosphere are adsorbed onto the surface of the germanium layer. Then, it is introduced into the MBE apparatus again and heated to 800° C. to remove the germanium layer. Immediately after removal, a silicon layer or the like is formed.
従来の製造方法では、ＭＢＥ法によりシリコン基板上に
シリコン層を形成した後に大気中に取り出した場合、大
気中の酸素がシリコン層に吸着し徐々に表面が酸化され
てゆく。したがって再びシリコン等を再成長する場合、
酸化膜を除去するため結晶を８５０℃程度に加熱しなけ
ればならない。In conventional manufacturing methods, when a silicon layer is formed on a silicon substrate by the MBE method and then taken out into the atmosphere, oxygen in the atmosphere is adsorbed to the silicon layer and the surface is gradually oxidized. Therefore, when regrowing silicon etc.,
In order to remove the oxide film, the crystal must be heated to about 850°C.
しかし本実施例ではゲルマニウムを表面保護膜として用
いることにより表面の酸化を保護し、したがって結晶を
８５０℃に加熱する必要がなくなり、ゲルマニウム層を
除去するために８００℃程度でよい。したがって従来の
方法に比較して不純物の拡散を抑えることが可能となる
。However, in this embodiment, germanium is used as a surface protective film to protect the surface from oxidation, so there is no need to heat the crystal to 850°C, and it is sufficient to heat the crystal to about 800°C to remove the germanium layer. Therefore, it is possible to suppress diffusion of impurities compared to conventional methods.
本実施例では結晶成長法としてＭＢ２法を用いて説明し
たが、たとえば気相成長法でも可能であり、また適切な
成長条件を用いて自由に変更することが可能である。Although this embodiment has been described using the MB2 method as the crystal growth method, it is also possible to use, for example, a vapor phase growth method, and it is possible to freely change the method using appropriate growth conditions.
以上の説明から明らかなように、本発明は半導体形成後
蒸発温度の低い半導体層を設け、再度半導体層を形成す
る前に蒸発温度の低い半導体層を加熱蒸発することによ
り清浄な表面を保持しつつ所望の半導体層を形成するこ
とが可能となるという利点があり、従来の製造方法と比
較して半導体素子の性能向上を図ることができる効果は
著しい。As is clear from the above description, the present invention maintains a clean surface by providing a semiconductor layer with a low evaporation temperature after semiconductor formation and heating and evaporating the semiconductor layer with a low evaporation temperature before forming the semiconductor layer again. However, this method has the advantage that it is possible to form a desired semiconductor layer, and has a remarkable effect of improving the performance of semiconductor elements compared to conventional manufacturing methods.
第１図は本発明の第１の実施例における半導体装置の各
製造工程での断面図、
第２図は第１の実施例により製造された半導体装置と従
来の製造方法により製造された半導体装置のドナ濃度の
膜厚方向の分布を示す図、第３図は第２の実施例におけ
る半導体装置の各製造工程での断面図である。
１．１１・・・ガリウム砒素基板
２．３・・・ｎ型ガリウム砒素層
４・・・・・インジウム砒素層
５・・・・・吸着分子
１２・・・・・ｎ型ガリウム砒素コレクタ層１３・・・
・・ｐ型ガリウム砒素ベース層２０・・・・・アルミニ
ウムガリウム砒素層３０・・・・・アルミニウムガリウ
ム砒素グレーデツト層
４０・・・・・ガリウム砒素層
６０・・・・・エミッタ電極
７０・・・・・ベース電極
８０・・・・・コレクタ電極
９０・・・・・二酸化硅素膜
（ａ）
（ｂ）
（Ｃ）
（ｄ）
（ｅ）
第１図
界面
月賛犀方向の７巨禽を
第２図
（ｄ）
第３図
ガリウム砒素層
アルミニウム
カリウム砒素層
ガリウム砒素基板
二酸化硅素膜
電場
スミ楊
コレクタ＠格FIG. 1 is a cross-sectional view of a semiconductor device in each manufacturing process according to a first embodiment of the present invention, and FIG. 2 is a diagram showing a semiconductor device manufactured according to the first embodiment and a semiconductor device manufactured by a conventional manufacturing method. FIG. 3 is a diagram showing the distribution of donor concentration in the film thickness direction, and FIG. 3 is a cross-sectional view at each manufacturing process of the semiconductor device in the second embodiment. 1.11... Gallium arsenide substrate 2.3... N-type gallium arsenide layer 4... Indium arsenide layer 5... Adsorbed molecules 12... N-type gallium arsenide collector layer 13 ...
...p-type gallium arsenide base layer 20 ... aluminum gallium arsenide layer 30 ... aluminum gallium arsenide graded layer 40 ... gallium arsenide layer 60 ... emitter electrode 70 ... ... Base electrode 80 ... Collector electrode 90 ... Silicon dioxide film (a) (b) (C) (d) (e) Figure 2 (d) Figure 3 Gallium arsenide layer Aluminum potassium arsenide layer Gallium arsenide substrate Silicon dioxide film Electric field Sumiyang collector @Gate
Claims (4)
を設け、所定時間経過後に第３の半導体層を設ける半導
体装置の製造方法において、前記第２の半導体層を形成
した後連続して前記第２の半導体層よりも蒸発温度の低
い第４の半導体層である薄膜層を設け、所定の時間経過
後に前記第４の半導体層を加熱蒸発させた後に前記第３
の半導体層を設けることを特徴とする半導体装置の製造
方法。(1) In a method for manufacturing a semiconductor device in which a second semiconductor layer is provided on a first semiconductor layer heated to an elevated temperature, and a third semiconductor layer is provided after a predetermined period of time, after forming the second semiconductor layer. A thin film layer that is a fourth semiconductor layer having an evaporation temperature lower than that of the second semiconductor layer is successively provided, and after a predetermined time has elapsed, the fourth semiconductor layer is heated and evaporated, and then the third semiconductor layer is heated and evaporated.
1. A method of manufacturing a semiconductor device, comprising: providing a semiconductor layer.
ミニウム砒素あるいはこれらの混晶であり、前記薄膜層
はインジウム砒素であることを特徴とする特許請求の範
囲第１項記載の半導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the second semiconductor layer is gallium arsenide, aluminum arsenide, or a mixed crystal thereof, and the thin film layer is indium arsenide. .
アルミニウム組成の大きいアルミニウムガリウム砒素で
あり、前記薄膜層はガリウム砒素であることを特徴とす
る特許請求の範囲第１項記載の半導体装置の製造方法。(3) The method for manufacturing a semiconductor device according to claim 1, wherein the second semiconductor layer is aluminum arsenide or aluminum gallium arsenide with a high aluminum composition, and the thin film layer is gallium arsenide. .
層はゲルマニウムであることを特徴とする特許請求の範
囲第１項記載の半導体装置の製造方法。(4) The method of manufacturing a semiconductor device according to claim 1, wherein the second semiconductor layer is silicon and the thin film layer is germanium.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29469886A JPS63148616A (en) | 1986-12-12 | 1986-12-12 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29469886A JPS63148616A (en) | 1986-12-12 | 1986-12-12 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63148616A true JPS63148616A (en) | 1988-06-21 |
Family
ID=17811144
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29469886A Pending JPS63148616A (en) | 1986-12-12 | 1986-12-12 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63148616A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5288657A (en) * | 1990-11-01 | 1994-02-22 | At&T Bell Laboratories | Device fabrication |
| FR2766614A1 (en) * | 1997-07-22 | 1999-01-29 | Commissariat Energie Atomique | METHOD FOR PRODUCING A GROWING STRUCTURE OF A MATERIAL ON AN AIR VENT SUPPORT |
-
1986
- 1986-12-12 JP JP29469886A patent/JPS63148616A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5288657A (en) * | 1990-11-01 | 1994-02-22 | At&T Bell Laboratories | Device fabrication |
| FR2766614A1 (en) * | 1997-07-22 | 1999-01-29 | Commissariat Energie Atomique | METHOD FOR PRODUCING A GROWING STRUCTURE OF A MATERIAL ON AN AIR VENT SUPPORT |
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