JPS63158836A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To provide a novel active layer effective for substantially decreasing the number of processes, by heat treating a wafer on which AlN is deposited by the CVD process at different depositing temperature according to various regions on the surface of III-V compound semiconductor crystals doped with amphoteric dopant ions. CONSTITUTION:Si ions are implanted into the surface of an insulating GaAs substrate 21 to form an ion implanted layer 211. In order to provided a protection film on the layer 211 for preventing GaAs from being thermally decomposed by a heat treatment, 900 Angstrom AlN layer 22 is deposited all over the surface of the substrate at 400 deg.C for example and then a resist mask is provided on a region where the AlN layer 22 is to be left unetched. The unrequired part of the AlN layer 22 is removed by etching and then the mask is also removed. After that, an AlN layer 23 having a thickness of 900 Angstrom is formed by the MOCVD process at 600 deg.C for example. When the wafer is heat treated at 950 deg.C for 20 minutes, it can be observed at an electron concentration of 3.6X10<12>cm<-2> that the part of the ion implanted layer 211 covered with the AlN layer 22 has been converted into an N-type conducting layer 212 while the part of the layer 211 covered with the AlN layer 23 has been converted into a P-type layer 213. In this manner, types of conductivity and concentrations of active carriers of the ion implanted layer can be controlled as required.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for controlling conduction type of a semiconductor.

(Prior art) Conventional methods for forming an active layer include the so-called ion implantation method, in which an impurity is implanted into a semiconductor crystal, and the active layer is formed by heat-treating the hindlimb crystal; There is a diffusion method in which the active layer is introduced into the semiconductor crystal by diffusion, and a selective growth method in which the region where the active layer is to be formed is selectively etched and an active layer is grown with impurities added to the rear region.These methods are widely used in the manufacturing of semiconductor devices. It is used for. By the way, when active layers with different conductivity types and carrier concentrations are formed on the same wafer using conventional techniques such as ion implantation and diffusion, processes are required for each type of active layer.

(Interset point to be solved by the invention) In other words, according to the conventional method, a mask is not provided on the wafer portion where the active layer is to be formed, and after a mask is provided on the portion that is not to be used as the active layer, impurities are introduced into the crystal. A series of processes for enlarging and directly forming the active layer were required only for each type of active layer. For this reason, the actual manufacturing process of semiconductor devices becomes complicated.
Even small circuit changes required enormous effort. An object of the present invention is to provide a novel method for forming an active layer that is effective in significantly reducing the number of man-hours.

(Means for Solving the Problems) The present invention provides III + V ions in which amphoteric impurities are ion-implanted.
A method for manufacturing a semiconductor device characterized by heat-treating a wafer on which AIN has been formed by CVD at different deposition temperatures depending on the region of the compound semiconductor crystal surface; A semiconductor device manufacturing method characterized by ion implanting an amphoteric impurity from above a wafer on which AIN has been formed at different deposition temperatures, followed by heat treatment, and a CVD method according to the surface area of an IILV compound semiconductor crystal added with an amphoteric impurity. This method of manufacturing a semiconductor device is characterized in that a wafer on which AIN is formed at different deposition temperatures is heat-treated.

(Function) In the 111-V compound semiconductor crystal, the group III element behaves as an amphoteric impurity, and when it occupies the group III site,
When it becomes an n-type impurity and occupies the V group,
It is known to become a p-type impurity.

Therefore, if the sites occupied by the group Ⅰ elements can be controlled, the conductivity type and carrier concentration can be controlled. Taking Si, which is an amphoteric impurity in GaAs, as an example, the reason why the conductivity type of the ion implantation layer can be controlled by using CVD AIN with different film formation temperatures as a heat treatment protective film will be explained below.

Figure 2 shows that 5X1012 cm-2 of Si is ion-implanted at 100 KeV into an insulating GaAs substrate, and a MOC is placed on top of it.
A at 400, 500, 600, 700°C by VD method
Wafers with 900 IN films were heated at 800°C for 20 minutes.
9 is a diagram showing the relationship between the concentration of activated electrons and the heat treatment temperature when heat treatment is performed between 900°C and 900°C. 400,5
The AIN film formed at 00°C shows high donor activation at heat treatment temperatures between 800°C and 950°C, a feature not seen in heat-treated protective films formed by conventional methods. Conventionally, 5i02 and SiO-Ny have been generally used as a heat treatment protective film after ion implantation, but because these and GaAs have a large coefficient of thermal expansion, large stress was generated at the interface during heat treatment. The stress increases as the temperature rises higher than the film formation temperature of the heat-treated protective film, which affects the site substitution of amphoteric impurities, resulting in a decrease in the carrier activation rate and a decrease in the GaA
s surface damage. In order to solve the above-mentioned drawbacks, an example has been proposed in which AIN, which has a coefficient of thermal expansion almost equal to that of GaAs, is used as a heat treatment protective film.

(Applied Physics
, Lett.

40 (1982) 689)) However, the AIN in this report was formed by a reactive sputtering method, and the GaAs surface was damaged during film formation.

Not only did the crystal quality deteriorate on the damaged GaAs surface, resulting in lower mobility, but stress also occurred at the disordered interface with AIN. Therefore, as a heat treatment protective film, 5i02
The disadvantages of using 5iO1Ny and 5iO1Ny were not resolved. The AIN of the present invention is based on the MOCVD method in which growth gas is thermally decomposed and deposited, and it is believed that damage to the GaAs surface during film formation, which could not be avoided with conventional sputtering methods, can be prevented. In addition 400.500°C
It is thought that the AIN film formed in the above method was formed at a temperature lower than the decomposition temperature of GaAs, resulting in an interface with extremely little damage. On the other hand, 600,700°C
Although the AIN film was formed using the MOCVD method, which does not damage the GaAs surface, the film was formed at temperatures above the decomposition temperature of GaAs, resulting in evaporation of As, which has a higher vapor pressure than the GaAs surface. It is thought that it has deteriorated due to heat. It is thought that thermal deterioration of GaAs progresses closer to the surface.

Therefore, deterioration of crystallinity near the GaAs surface, etc.
It is thought that heat treatment at a temperature of .degree. C. or higher causes a decrease in carrier activation. For the above reasons, by heat-treating a semiconductor crystal having a portion in which AIN is deposited at at least two different temperatures by MOCVD on a GaAs crystal into which amphoteric impurities have been ion-implanted, the conduction shape of the ion-implanted layer can be improved. Concentration can be controlled.

(Example) Hereinafter, an example of the present invention will be described in detail using the drawings.

A first embodiment of the invention set forth in claim 1 will be described below. In FIG. 1, (a) shows an insulating GaAs substrate 2.
An ion-implanted layer 211 in which Si is implanted is formed on the surface of the ion-implanted layer 211, and an AIN layer 22 formed at 400°C by MOCVD and an AIN layer 22 formed at 600°C as a heat treatment protective film to prevent thermal decomposition of GaAs due to heat treatment. FIG. 2 is a cross-sectional view of a deposited AIN layer 23. When the wafer is subjected to heat treatment at 950°C for 20 minutes, the portion where the AIN layer 22 is applied has an electron concentration of 3.6 x 101 per treatment, as shown in Fig.
An n-type conductive layer 212 with a thickness of 2 cm −2 was obtained, and inversion to p-type was observed in the portion where the AIN layer 23 was applied, and a p-type layer 213 was obtained. This is because Si occupies group III sites in the portion where the AIN layer 22 with a good interface is formed, and therefore the ion implantation layer becomes the n-type conductive layer 212 for the reason shown in the "effect" column. AIN layer 23 having a thermally degraded GaAs surface at the interface with AIN
It is considered that in the portion where Si was subjected to the ion implantation, Si exhibited properties as an amphoteric impurity, and the ion implantation layer was inverted to p-type.

A second embodiment of the invention set forth in claim 1 will be described below. FIG. 3 is an example of active layer formation according to the present invention. In FIG. 3, (a) is an external view of the wafer before heat treatment, and FIG. 3(b) is a cross-sectional view taken along line A-A'.
Ru. The wafer is an insulating GaAs substrate 31 with 100% Si.
5 x 1012 cm-2 ions were implanted at KeV to form an ion-implanted layer 311, and on top of that, an AIN layer 32 at 500'C and an AIN layer 33 at 700°C were formed by 900 people by MOCVD. . 20 of those wafers
By heat-treating at 950°C for
), an n-type conductive layer 312 and a high-resistance layer 313 having an electron concentration of about 3.5×10 12 cm −” were obtained.

The n-type conductive layer 312 is insulated from the insulating GMS substrate 31 by the layer 313 exhibiting high resistance, and it is clear that the present invention is effective for electrically isolating elements.

Examples of the invention set forth in claim 2 are shown below. FIG. 4 is an example of active layer formation according to the present invention.

In FIG. 4, (a) is an external view of the wafer before heat treatment,
FIG. 4(b) is a sectional view taken along line AA'. The wafer is formed on an insulating GaAs substrate 41 using the MOCVD method.
500 layers of AIN layer 42 were formed at 0°C and AIN layer 43 was formed at 600°C, and then 150 layers of Si were formed from above the wafer.
An ion implantation layer 411 is formed by implanting 5×10 12 cm −2 ions at KeV. 20 of those wafers
Figure 4 (C
), an n-type conductive layer 412 and a high-resistance layer 413 having an electron concentration of about 3×10 12 cm −2 were obtained. The n-type conductive layer 412 could be insulated from the insulating GaAs substrate 41 by the layer 413 exhibiting high resistance.

Examples of the invention set forth in claim 3 are shown below. FIG. 5 is an example of active layer formation according to the present invention.

In FIG. 5, (a) is an external view of the wafer before heat treatment,
FIG. 5(b) is a sectional view taken along line AA'. The wafer is made of Si on an insulating GaAs substrate 51 by MOCVD.
The growth layer 511 doped with I×1018 cm−3 is about 1
000 people were formed and 40
0°C AIN layer 52 and 600°C AIN layer 53
The film was formed by 900 people. The wafer was heat treated at 950°C for 20 minutes. In this example, the active layer is formed first, and therefore, as a result of the present invention, the carrier concentration in the portion used as the active layer must remain at its initial value or be at a value that can be used as the active layer. Therefore, the carrier concentration in the portion not used as an active layer must be low. FIG. 5(C) shows a cross-sectional view of the wafer after heat treatment. Approximately 9X1017 in the 2nd part above the AIN layer 5
An n-type conductive layer 512 with an electron concentration of cm-3 was obtained. On the other hand, the high resistance layer 5 is formed on the AIN layer 5.
I got 13. The reason why a high resistance layer 513 was obtained in the portion where three AIN layers were formed is as shown in the operation.

That is, it is considered that stress existing between the three dynamic layers 511 above the five AIN layers acted on 8i, causing about half of the Si atoms to undergo site substitution from group III sites to group V sites. Further, in this embodiment, an example was shown in which the Si-doped growth layer 511 was formed on the insulating GaAs substrate 51 by the MOCVD method.
It is not limited to the 11 manufacturing methods. Layer 511 can also be formed by uniform thermal diffusion of Si into insulating GaAs substrate 51.

In the above embodiments, the amphoteric impurity Si in GaAs was given as an example, but the method for manufacturing a semiconductor device according to the present invention can also be applied to other amphoteric impurities in GaAs, such as Ge.
It is obvious that the present invention can be applied not only to the above, but also to other 1-2 compound semiconductor materials, such as InP-based materials.

(Effects of the Invention) As described above, according to the present invention, not only is there no need for a complicated process unlike the conventional technology, but there is also no need for a huge amount of labor even when changing the circuit, and the ion-implanted layer The conduction shape and active carrier concentration can be controlled.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are cross-sectional views showing the first embodiment of the invention set forth in claim 1, and FIG. 2 is an AI
FIG. 3 is a diagram showing the relationship between the activated electron concentration and the heat treatment temperature when the N layer is used as a heat treatment protective film for a GaAs substrate. FIG. 4 is an example of the present invention based on the results shown in the embodiment of the invention set forth in claim 2, and FIG. 5 is a diagram showing an example. 3 is a diagram showing an embodiment of the invention shown in Section 3. FIG. 21: Insulating GaAs substrate, 211: Ion implantation layer, 212: N-type conductive layer, 213: P-type layer, 22: A
IN film, 23--AIN film, 31--insulating GaA
s substrate, 311--ion implantation layer, 312-n-type conduction layer, 313--high resistance layer, 32--AIN film, 33
-AIN layer, 41... insulating GaAs substrate, 411-
...Ion implantation layer, 412...n-type conduction layer, 413.
...High resistance layer, 42, -AIN film, 43-AIN film, 5
1... Insulating GaAs substrate, 511... Growth layer, 5
12... n-type conductive layer, 513.・High resistance layer, Figure 1 Figure 2 Heat treatment temperature ('C) 1000/Heat treatment temperature (1/K) Figure 3 Figure 4 Figure 5 Figure 5 Procedural amendment (voluntary)

Claims (3)

[Claims] (1) A method for manufacturing a semiconductor device, which comprises heat-treating a wafer on which AIN has been formed by CVD at different deposition temperatures depending on the region of the III-V compound semiconductor crystal surface into which amphoteric impurities have been ion-implanted. (2) Depending on the surface area of the III-V compound semiconductor crystal, C
A method for manufacturing a semiconductor device, comprising ion-implanting an amphoteric impurity from above a wafer on which AIN has been formed at different deposition temperatures by a VD method, and then heat-treating the wafer. (3) III-V compound semiconductor crystals doped with amphoteric impurities At different deposition temperatures depending on the region of the crystal surface
A method for manufacturing a semiconductor device, comprising heat-treating a wafer on which an IN has been formed.