JPH05175536A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing a semiconductor device, in which a lateral p-n junction, in any shape according to the mask used, is formed in a Si1-xGex film (x=0.2+ or -0.1). CONSTITUTION:A substrate 1 having an Si0.8Ge0.2/Si/sapphire structure is used. Boron ions are implanted to the Si0.8Ge0.2 layer 1c, and the substrate is annealed to form a p-type region 4. In addition, phosphorus ions are implanted to the Si0.8Ge0.2 layer 1c, and the substrate is annealed to form an n-type region 6. Aluminum 9 is deposited on contact holes 8 to form ohmic contact. In this manner, a lateral pin diode is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in a Si _1-x Ge _x / Si structure, and more particularly to a method for manufacturing a semiconductor device for forming a PN junction in a Si _1-x Ge _x film. It is a thing.

[0002]

2. Description of the Related Art A Si _1-x Ge _x (x = 0.2 ± 0.1) film is a material exhibiting electrical and optical properties which has not been obtained by the Si film alone by forming a heterostructure with the Si film. Becomes Therefore, application of this Si _1-x Ge _x film to semiconductor devices such as hetero-bipolar transistors and photodiodes has been vigorously pursued.

By the way, in the case of forming a PN junction, which is the basis of device fabrication, in a structure containing such a Si _1-x Ge _x film, for example, Si films are formed on the upper and lower sides of the Si _1-x Ge _x film. Forming,
A method of making the upper and lower two Si films P-type and N-type respectively ^{1) 2) 3)} , or growing a P-type or N-type Si _1-x Ge _x film by performing impurity doping while performing crystal growth The main methods are ^{3) and 4)} .

Reference 1) H. Temkin et al., Appl. Phys. Lett. 48 (1
5), P.963 2) V.Kesan et al., IEDM 90, P.637 3) G.Higashi et al., Appl.Phys.Lett.56 (25), P.2560 4) H.Presting et al., J.Appl.Phys.68 (11), P.5653

[0005]

The method of forming a PN junction as described above has a problem that only a PN junction perpendicular to the substrate surface, that is, a vertical PN junction can be formed.

The present invention has been made in view of the above circumstances, and by forming a P-type region and an N-type region in a Si _1-x Ge _x film by an ion implantation method, for example, a PN parallel to the substrate surface is formed. An object of the present invention is to provide a semiconductor element manufacturing method capable of forming a junction, that is, a lateral PN junction and forming the PN junction in an arbitrary shape according to a mask.

[0007]

A method for manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device, wherein a P 1 -type region and / or an N-type region is formed in a laminated structure of a Si _1-x Ge _x (x = 0.2 ± 0.1) film and a Si film. a method of manufacturing a semiconductor device by forming a region, characterized in that the Si _1-x in Ge _x film by implanting B ions and / or P ions to form the P-type region and / or the N-type region And

[0008]

In the semiconductor element manufacturing method of the present invention, B ions,
Implanting P ions into a predetermined region of the Si _1-x Ge _x film, P-type region, an N type region is formed on each ion is diffused Si _1-x Ge _x intima.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings showing the embodiments thereof.

P-type in the Si _1-x Ge _x film by ion implantation,
When forming the N-type region, for example heat resistance, since the physical properties such as diffusion coefficient of impurities in the Si _1-x Ge _x mixed crystal Si crystals are different, the development of new process conditions, and optimization requires Is. Hereinafter, ion implantation conditions, activation annealing conditions, and ohmic electrode formation conditions for the Si _1-x Ge _x mixed crystal necessary for forming a PN junction by ion implantation in the Si _1-x Ge _x film will be described.

First, in the process using the Si _1-x Ge _x film, the maximum process temperature is suppressed to about 850 ° C. or lower.
Also, the amount of B ion implantation for forming the P-type region is set to 5 × 10 5.
^{The amount is 15} cm ⁻² or less, and the amount of P ion implantation for forming the N-type region is 5 × 10 ¹⁴ cm ⁻² or more. Also, activation annealing of B and P ions is performed at 800 to 850 ℃ and 600 to 700 ℃, respectively.
Done in. Furthermore, P ⁺ contact and N ⁺ contact are formed by aluminum, and the sintering temperature of aluminum is increased.
250 to 300 ℃.

Next, the reason for setting such various conditions will be described. Note that the following example, Si _1-x Ge _x film is x = 0.2, that is, using the Si _0.8 Ge _0.2 layer.

First of all, FIG. 1 shows the results of investigating how the crystallinity of the Si _0.8 Ge _0.2 film changes by high temperature annealing based on the Rutherford backscattering method. From the relationship between the surface χ _min of the annealed film and the annealing temperature, the same surface χ _min as during growth was obtained up to the annealing temperature of 850 ° C.
No change in crystallinity is observed, but χ exceeds 850 ° C
It can be seen that the _min value sharply increases and the crystallinity deteriorates significantly. Therefore, in order to prevent the deterioration of the crystallinity of the Si _1-x Ge _x film, it is necessary to suppress the maximum process temperature to about 850 ° C or lower.

As shown in FIG. 2, a Si _0.8 Ge _0.2 film with 60 keV, 1 × 10
B ion is implanted under the condition of ¹⁵ cm ^-2 , and the annealing temperature and Si _0.8 Ge _0.2
The relationship with the sheet resistance of the film is shown. Although the sheet resistance decreases at an annealing temperature of 850 ℃ or higher, the rate of change is 8
It is smaller than that of 50 ℃ or below. This is considered to be due to the deterioration of crystallinity due to high temperature annealing. Further, FIG. 3 shows the dependence of the sheet resistance value of the Si _0.8 Ge _0.2 film annealed at 850 ° C. after the B ion implantation on the ion implantation amount. From Figure 3, B
It can be seen that the sheet resistance value is hardly reduced when the implantation amount is 5 × 10 ¹⁵ cm ^-2 or more. When implanting B ions, if the dose is 5 × 10 ¹⁵ cm ^-2 or less, 850 ℃
Annealing can activate B ions without causing a significant decrease in mobility or segregation of impurities. As a result of the above, the implantation amount of B ions and the activation temperature were 5 × 10 ¹⁵ cm ^-2 or less and 800-
Set it to 850 ° C.

Next, 120 keV, 1 × 10 ¹⁵ was applied to the Si _0.8 Ge _0.2 film.
FIG. 4 shows the relationship between the annealing temperature and the sheet resistance when P ions are implanted under the condition of cm ⁻² . At an annealing temperature of 600 ° C. or higher, the sheet resistance does not change so much, and at 800 ° C., on the contrary, the result increases. Therefore, the activation temperature of P ions is preferably 600 to 700 ° C.

FIG. 5 shows a Si _0.8 Ge _0.2 film with 120 keV and 1 × 10 6.
After implanting P ions (N-type) under the condition of ¹⁵ cm ^-2 , aluminum is vapor-deposited and the sinter temperature condition in the nitrogen atmosphere is 200 ~.
The current-voltage characteristics are shown for a range of 400 ° C (20 minutes). It can be seen that a temperature of 200 ° C or higher is required to maintain ohmic contact, and the contact resistance is approximately constant at 250 ° C or higher. However, at 350 ° C., aluminum diffuses abnormally inside the Si _0.8 Ge _0.2 film and the specific resistance of the N-type region increases. Therefore, the sintering temperature for forming a good aluminum electrode in the N-type region is appropriately in the range of 250 to 300 ° C. Then, by the aluminum sintering temperature 250 to 300 ° C., without the need for barrier metal since it is possible to prevent the abnormal diffusion of aluminum into Si _1-x Ge _x film in,
It is possible to form an ohmic electrode only with aluminum.

FIG. 6 shows the relationship between the P ion implantation amount at the activation annealing temperature of 700 ° C. and the sheet resistance of the Si _0.8 Ge _0.2 film. When the implantation amount becomes smaller than 5 × 10 ¹⁴ cm ^-2 , the sheet resistance rapidly increases. Also, set the annealing temperature to 700
℃, the aluminum sinter temperature is fixed at 300 ℃, P
Fig. 7 shows current-voltage characteristics when the ion implantation amount is changed.
Shown in. When the P ion implantation amount is 1 × 10 ¹⁴ cm ^-2 , it exhibits non-ohmic properties, but when it is 5 × 10 ¹⁴ cm ^-2 or more, it exhibits ohmic properties. Therefore, in order to form an aluminum electrode having a good ohmic contact, a P ion implantation amount of 5 × 10 ¹⁴ cm ^-2 or more is required.

Next, as one embodiment of the present invention, a lateral type on a Si _0.8 Ge _0.2 / Si / Sapphire structure utilizing the ion implantation conditions, activation conditions and electrode formation conditions determined as described above is used.
An example of manufacturing a pin photodiode will be described with reference to FIG.

Substrate 1 was obtained by molecular beam epitaxial growth of high resistance Si film (film thickness: 170 nm) 1b and Si _0.8 Ge _0.2 film (film thickness: 170 nm) 1c on sapphire (1 bar 102) 1a. The element is separated by dry etching (FIG. 8A).

Next, the SiO ₂ film 2 is deposited on the entire area by the CVD method (FIG. 8 (b)). Using the photoresist 3 patterned according to the P-type region to be formed as a mask, 60 keV, 1 ×
After implanting B ions into the Si _0.8 Ge _0.2 film 1c under the condition of 10 ¹⁵ cm ^-2 , furnace annealing is performed at 850 ° C. in a nitrogen gas atmosphere for 60 minutes to activate the B ions to make the P-type region 4 Si.
_It is formed in the _0.8 Ge _0.2 film 1c (FIG. 8 (c)).

Next, with the photoresist 5 patterned according to the N-type region to be formed as a mask, 120 keV,
After implanting P ions under the condition of 1 × 10 ¹⁵ cm ^-2 , furnace annealing is performed at 700 ° C. in a nitrogen gas atmosphere for 60 minutes to activate the P ions so that the N type region 6 is made into the Si _0.8 Ge _0.2 film 1c. It is formed inside (FIG. 8 (d)). Next, the antireflection film 7 is formed on the entire area (FIG. 8E). After the antireflection film 7 made of a SiO ₂ film is partially removed by etching to form a contact hole 8, aluminum 9 is vapor-deposited in the formed contact hole 8 (FIG. 8 (f)), and in a nitrogen gas atmosphere, By sintering aluminum 9 under the condition of 300 ° C for 20 minutes,
A lateral pin photodiode as shown in FIG. 9 is completed.

FIG. 10 shows current-voltage characteristics of the lateral pin photodiode shown in FIG. As can be seen from FIG. 10, the lateral pin photodiode manufactured according to the present invention exhibits a good PN junction characteristic and sufficiently fulfills the function as a photodiode.

[0023]

As apparent from the foregoing description, according to the present invention, P-type regions in Si _1-x Ge _x film by ion implantation, it is possible to form the N-type region, depending on the mask shape used It is possible to fabricate an element with an arbitrary shape at an arbitrary position, and its effect is extremely large, as it contributes to the process technology and device technology in device application.

[Brief description of drawings]

FIG. 1 is a diagram showing a change in crystallinity of a Si _0.8 Ge _0.2 film by high temperature annealing.

FIG. 2 is a diagram showing a relationship between a sheet resistance of a Si _0.8 Ge _0.2 film after B ion implantation and an annealing temperature.

FIG. 3: Si _0.8 annealed at 850 ° C. after B ion implantation
It is a figure which shows the sheet resistance of _Ge0.2 film _| membrane and the relationship of the amount of ion implantations.

FIG. 4 is a diagram showing a relationship between a sheet resistance of a Si _0.8 Ge _0.2 film after P ion implantation and an annealing temperature.

FIG. 5 is a diagram showing a change in ohmic property of an aluminum electrode in an N-type region depending on a sintering temperature.

FIG. 6: Si _0.8 annealed at 700 ° C. after P ion implantation
It is a figure which shows the sheet resistance of _Ge0.2 film _| membrane and the relationship of the amount of ion implantations.

FIG. 7: Aluminum electrode ohmic P of N type region
It is a figure which shows the change with the amount of ion implantations.

FIG. 8 is a cross-sectional view showing a PN junction formation process in a Si _0.8 Ge _0.2 / Si / Sapphire structure according to the present invention.

FIG. 9 is a cross-sectional view of a lateral pin photodiode manufactured by the method of the present invention.

FIG. 10 is a diagram showing current-voltage characteristics of a lateral pin junction diode manufactured according to the present invention.

[Explanation of symbols] 1 substrate 1a sapphire 1b Si film 1c Si _0.8 Ge _0.2 film 4 P-type region 6 N-type region 9 Aluminum

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/165 7377-4M

Claims (1)

[Claims] 1. A method for producing a semiconductor device by forming a P-type region and / or an N-type region in a laminated structure of a Si _1-x Ge _x (x = 0.2 ± 0.1) film and a Si film, Si _1-x Ge _x
By implanting B ions and / or P ions into the film, the P
A method of manufacturing a semiconductor element, which comprises forming a mold region and / or an N-type region.