KR930010675B1 - Manufacturing method of semiconductor device using mbe process - Google Patents

Abstract

The semiconductor device is mfd. by (a) forming a first oxide film (2) on the semiconductor substrate (1), defining a first device region, and removing the film (2), (b) forming a first epitaxial layer (3) on the region, (c) forming a second oxide film (5) on the whole surface, defining a second device region, and removing the film (5), (d) forming a second epitaxial layer (6) on the region, (e) forming a third oxide film (8) on the whole surface, defining a third device region, and removing the film (8), (f) forming a third epitaxial layer (9) on the region, (g) forming a forth oxide film (11) on the whole surface, and (h) forming a contact hole (12) on the layers (3,6,9), and forming an electrode (13).

Description

Semiconductor device manufacturing method using MBE

1 is a cross-sectional view of a conventional bipolar transistor structure.

Figure 2a-n is a cross-sectional view of the manufacturing process according to the present invention.

* Explanation of symbols for main parts of the drawings

1: P type substrate 2, 5, 8: oxide film

3, 9: N + epitaxial layer 6: P epitaxial layer

4, 7, 10: PR layer 4a: Pr + Si + As layer

7a: Pr + Si + B layer 10a: Pr + Si + As layer

11: field oxide film 12: contact hole

13: metal

The present invention relates to a method for manufacturing a semiconductor device using a molecular beam epitaxy (MBE), in particular single crystal epitaxy capable of controlling the vertical distribution of impurities in the base, emitter and collector region at a low temperature below 1000 ℃ using MBE By forming a shir layer, a vertical bipolar integrated circuit can be manufactured.

The prior art will be described in detail with reference to the attached FIG. 1 as follows.

First, in order to reduce the series resistance of the collector on the P-type substrate, the highly doped N + buried layer is diffused at high temperature, and then the N-type epitaxial layer is grown at a high temperature of 1000 ° C-1150 ° C.

Subsequently, P + was diffused for a long time at a temperature of 1000 ° C. or higher to form an isolation region between the devices, and then N + was formed using an ion implanter and a furnace to form a base, an emitter, and a collector. And P is injected.

Next, to form an electrode in the active area, a photo / etch process is performed on the contact portion to deposit a metal, and then a photo / etch process is performed on the metal portion to complete the bipolar transistor.

However, the prior art is a wafer bent due to the buried layer forming process and the junction isolation region forming process performed at a high temperature of 1100-1200 ℃ and the epitaxial layer forming process also performed at a high temperature of 1150 ℃ and OISE (Oxidation Induced Stacking Fault) There is a problem that crystal defects may occur, and because the process of making each active region is complicated, the process time is long and a lot of equipment is required.

The present invention is to eliminate the above problems and will be described in detail with reference to the accompanying Figure 2 as follows.

First, the oxide film 2 is formed on the P-type substrate 1 as shown in (A), and then subjected to a photo / etch process to define the N + epitaxial layer 3 as a collector as shown in (B). The oxide film 2 can be formed by any of thermal oxidation or normal CVD.

Next, as shown in (C), the N + epitaxial layer 3 is grown using silicon ions and arsenic ions (or silicon and antimony) with MBE. The ion concentration of arsenic or antimony can be varied to a collector concentration that can satisfy the desired electrical parameters.

Then, using a conventional lift-off method as shown in (D), Pr + Si + As layer 4a (or Pr + Si + Sb) in which silicon and arsenic (or silicon and antimony) are mixed with Pr Layer) is removed together with the underlying PR layer (4).

Subsequently, the oxide film 5 is formed again as in (E) (F) (G) (H) as in the collector formation process of (A) (B) (C) (D), and then the base is subjected to a photo / etch process. As a result, the P-type epitaxial layer 6 is defined and the P-type epitaxial layer 6 is deposited using boron and silicon ions at a desired concentration using MBE, and then the Pr + Si + B layer is again lift-off. (7a) is removed together with the PR layer 7.

Similarly, after forming the oxide film 8 as (I) (J) (K) (L), the N + epitaxial layer 9 is defined as an emitter through a photo / etch process, and then MBE is used to The N + epitaxial layer 9 is deposited with silicon and arsenic (or silicon and phosphorus) ions, and the Pr + Si + As layer 10a (or PR + Si + P layer) is formed by using a repeat-off method. 10) Remove together. At this time, the MDE method is different from the CVD epitaxial growth method as a deposition method, and its characteristic is that it proceeds at low temperature unlike epitaxial growth.

In addition, accurate control of doping is possible by minimizing out diffusion and auto doping. The general temperature of MBE is 400-800 ° C, which is lower than the general epitaxy temperature.

That is, the silicon source (Source) used in the conventional VPE (Vapor Phase Epitaxy) process is SiCl ₄ , SiHcl _s , SiH ₂ Cl ₂ , SiH ₄ The temperature range is most 1000 ℃ as shown in Table 1) Therefore, when the silicon layer containing impurities are grown by the VPE growth method, the impurities cannot be auto-doped to an undesired part due to the high temperature of 1000 ° C. or higher, whereas the MBE method applied in the present invention is not auto-doped. At this low temperature, the epitaxial layer is formed and heat treated at the minimum temperature to electrically activate the impurity, thereby obtaining a desired step junction.

TABLE 1

Since the silicon of the N +, P, and N + epitaxial layers 3, 6 as collectors, bases, and emitters formed by the above processes are not single crystals, As, Sb, B, P, etc., which are impurities, are not active. Anneal at a temperature of 700-950 ° C.

At this time, the annealing temperature of 700-950 ℃ is a temperature for electrically activating the impurities contained in the epitaxial layers (3) (6) (9) without warping or crystal defects of the P-type substrate (1) It is usually run.

At this time, the field oxide film 11 is formed as shown in M, and the contact hole 12 is defined by performing a photo / etch process on the field oxide film 11.

Finally, after depositing metal 13 to form electrodes on the collector, base, and emitter N +, P, and N + epitaxial layers 3, 6, and 9 as shown in (N). The bipolar transistor is completed by photo / etching the metal 13.

As described above, according to the present invention, since the vertical distribution of impurities is controllable in the base, emitter, and collector regions at a temperature lower than 1000 ° C, the warpage and crystal defects of the wafer, which may be caused at high temperatures, are not only prevented, but also by themselves. Since the oxide layer isolation process is performed, the conventional junction isolation process is unnecessary, and since the impurity and silicon are laminated together using the MBE of the emitter, base, and collector regions, there is no need to distinguish between the epitaxial layer process and the impurity doping process. There is an excellent effect that can be simplified and the process time can be greatly reduced.

Claims (4)

The first step of forming the first oxide film 2 on the semiconductor substrate 1, defining the first device region, and removing the first oxide film 2 in the first device region, the MBE method in the first device region. In the second process of forming the first epitaxial layer 3 containing the first impurity, after defining the second device region for forming the second oxide film 5 on the front surface, the second oxide film 5 of the second device region A third step of removing the oxide, a fourth step of forming the second epitaxial layer 6 containing the second impurity in the second device region by the MBE method, and a third oxide film 8 formed on the entire surface of the second device region A fifth step of removing the third oxide film 8 of the third device region after the definition thereof, a sixth step of forming a third epitaxial layer 9 including the third impurity in the third device region by the MBE method, and heat treatment To activate the first, second, and third impurities and to form a fourth oxide film 11 on the entire surface, the contact holes in the first, second, and third epitaxial layers 3, 6, and 9, respectively. Eighth process of forming 12 and forming electrode 13 A semiconductor device manufacturing method using the MBE, characterized by made of an. 2. A bipolar transistor using an MBE according to claim 1, wherein the first, second, and third impurities, which are stacked in three active regions defined for forming the collector, the base, and the emitter, are made of arsenic, boron, and phosphorus, respectively. Manufacturing method. The bipolar transistor using an MBE according to claim 1, wherein the first, second, and third impurities, which are stacked in three active regions defined to form a collector, a base, and an emitter, are formed of antimony, boron, and arsenic, respectively. Manufacturing method. The method of claim 1, wherein the annealing temperature is 700 ° C-950 ° C.

Images