KR0144340B1 - Method of fabricating ultra thin epitaxial film - Google Patents
Method of fabricating ultra thin epitaxial filmInfo
- Publication number
- KR0144340B1 KR0144340B1 KR1019900003162A KR900003162A KR0144340B1 KR 0144340 B1 KR0144340 B1 KR 0144340B1 KR 1019900003162 A KR1019900003162 A KR 1019900003162A KR 900003162 A KR900003162 A KR 900003162A KR 0144340 B1 KR0144340 B1 KR 0144340B1
- Authority
- KR
- South Korea
- Prior art keywords
- epitaxial layer
- thin epitaxial
- layer
- epitaxial film
- ultra thin
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 230000004888 barrier function Effects 0.000 claims description 12
- 238000002955 isolation Methods 0.000 claims description 8
- 229910052785 arsenic Inorganic materials 0.000 claims description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000001259 photo etching Methods 0.000 claims description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 6
- 229910052787 antimony Inorganic materials 0.000 description 4
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
내용없음No content
Description
제 1도(a)∼(c)는 종래의 기술에 따른 에피텍셜층 제조공정도1 (a) to (c) is an epitaxial layer manufacturing process drawing according to the prior art
제 2도(a)∼(d)는 본 발명에 따른 초박막 에피텍셜층 제조공정도2 (a) to (d) is a manufacturing process chart of the ultra-thin epitaxial layer according to the present invention
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : P형 기판 2 : 배리드 레이어1: P-type substrate 2: Barrier layer
3 : 필드옥사이드 4,5 : 에피텍셜층3:
6 : 아이솔레이션6: isolation
본 발명은 반도체 제조공정중 에피텍셜층 형성방법에 관한 것으로, 특히 배리드레이어(Buried Layer Dopant)로 안티모니(Sb)를 사용하지 않고 안티모니에 비하여 실리콘(Si)내의 용해도(Solubility)가 큰 비소(As;Arsenic)나 인(P:Phosphorus)을 사용할수 있도록 하므로서 배리드레이어의 하이도핑(High Doping)이 가능하여 소자의 전기적 특성을 향상시키도록한 초박막 에피텍셜층 제조방법에 관한 것이다.BACKGROUND OF THE
제 1도(a)∼(c)는 종래의 기술에 따른 에피텍셜층 제조방법을 설명하기 위한 공정도로서 제 1도(a)에 도시된 바와같이 P형기판(1:Ptype Substrate)상에 옥시데이션(Oxidation)후 배리드레이어가 형성될 부분을 포토에치(Photo Etch)하고, 안티모니(Sb)를 도핑하여 N+형 배리드레이어(2)를 형성한다. 다음 제 2도(b)에 도시된 바와같이 N형 에피텍셜층(4)을 형성(Phosphorus Doping)한후, 제 2도(c)에 도시된 바와같이 옥시데이션후 아이솔레이션 부분을 포토에치하고, P+이온을 주입한 다음 ROI(Recess Oxide Isolation)를 하여 옥사이드 아이솔레이션(6)을 형성한다.1 (a) to (c) are process charts for explaining the epitaxial layer manufacturing method according to the prior art, as shown in FIG. 1 (a), on the P-type substrate (1: Ptype Substrate). After etching, the portion where the barrier is to be formed is photo etched and doped with antimony Sb to form an N + type barrier 2. Next, as shown in FIG. 2 (b), after forming the N-type epitaxial layer 4 (Phosphorus Doping), as shown in FIG. 2 (c), photo-etching the isolation part after oxidization, Oxide isolation (6) is formed by implanting P + ions followed by Recess Oxide Isolation (ROI).
그러나 이와같은 종래의 기술에 있어서는 액티브 에피텍셜층을 디화인(Define)하기 위하여 도핑 프로화일(Doping Profile)콘트롤시 자동도핑(Auto Doping), 배리드레이어 업 디퓨젼(Up Diffusion)등의 문제로 인하여 에피텍셜층의 두께를 낮추는데 어려움이 있어 소자 크기가 커짐은 물론 자동도핑, 업 디퓨젼에 의한 브레이크 다운 전압(Break Down Voltage)의 저하를 초래하는 문제점이 있었다.However, in the related art, due to problems such as Auto Doping and Barrier Up Diffusion during doping profile control to define the active epitaxial layer. It is difficult to reduce the thickness of the epitaxial layer, thereby increasing the size of the device as well as causing a decrease in the breakdown voltage due to auto doping and up diffusion.
본 발명은 상기한 문제점을 제거하기 위해 선택적(Selective) 에피텍셜층 형성으로 초박막 에피텍셜층을 형성하기 위한 것으로서, 제 2도 (a)∼(d)를 참고로 상세히 설명하면 다음과 같다.The present invention is to form an ultra-thin epitaxial layer by forming a selective epitaxial layer in order to eliminate the above problems, and will be described in detail with reference to Figures 2 (a) to (d).
우선 제 2도(a)에 도시된 바와같이 P형 기관(1)상에 옥사이드(3)를 형성한후 배리드레이어가 형성될 부분을 포토에치 한다음 비소(As+) 또는 인(P+)을 이온 임플란테이션(Ion Implantation)하고 열처리(Annealing)하여 배리드레이어(2)를 형성한다. 다음 제2도(b)에 도시된 바와같이 에피텍셜층 형성시와 아이솔레이션시 배리드레이어로부터의 업 디퓨전을 보상하고 업 디퓨전 영역(Area)을 제한하기 위해 붕소(B:Boron)를 사용하여 P형의 선택적 에피텍셜층(4)을 성장시킨후, 에치백(Etch Back)하여 표면 평면화(Planarization)를 실시한다.First, as shown in FIG. 2 (a), an
이후 제 2도(c)에 도시된 바와같이 옥사이드(3)를 제거하고, n형 에피텍셜층(5)을 성장시킨후 표면 평면화를 실시 한다음 제 2도(d)에 도시된 바와같이 Locos(Local Oxide Isolation)공정을 통해 옥사이드 아이솔레이션(6)을 형성하며 이때 불순물(Dopant)은 P형의 선택적 에피텍셜층(4)으로 업 디퓨젼 된다.Thereafter, the
따라서 본 발명에 따른 초박막 에피텍셜층 제조방법은 선택적 에피텍셜층에 의해 업 디퓨전을 최소화하며 배리드 영역을 크리티컬(Critical)하게 콘트롤할수 있어 동일 두께의 에피텍셜층에서 소자의 액티브 영역을 최대화할수 있으며, 이에따라 에피텍셜층의 정확한 디파인이 가능하므로 초박막 에피텍셜층을 형성할수 있어 소자의 크기를 줄일수 있고, 안티모니(Sb)에 비하여 실리콘내의 용해도가 큰 비소(As)나 인(P)을 배리드레이어의 불순물로 사용할수 있어 배리드레이어의 하이도핑(Sheet Resistance가 낮아짐)이 가능하여 바이폴라의 경우 NPN트랜지스터의 컬렉터 저항을 크게 줄일수 있으며, 배리드레이어 불순물로 실리콘과의 크기(Size)차이에 기인한 미스피트팩터(Misfit Factor)가 적은 비소(As)와 인(P)은 사용할수 있어 에피텍셜층의 크리스탈 라인 디피트(Crystalline Defeet)의 발생을 최소화 할수 있어 수율을 향상시킬수 있고, 자동도핑, 배리드 업 디퓨젼을 최소화 하므로 에피텍셜층의 도핑 프로화일이 우수하여 소자의 전기적 특성을 향상시킬수 있는 효과를 갖는다.Therefore, the method for manufacturing an ultra-thin epitaxial layer according to the present invention minimizes up-diffusion by the selective epitaxial layer and critically controls the buried region, thereby maximizing the active region of the device in the epitaxial layer of the same thickness. As a result, the epitaxial layer can be precisely defined so that an ultra-thin epitaxial layer can be formed, thereby reducing the size of the device and releasing arsenic (As) or phosphorus (P), which have higher solubility in silicon than antimony (Sb). It can be used as an impurity of lead layer, so it is possible to do high doping (lower sheet resistance) of barrier layer. In the case of bipolar, the collector resistance of NPN transistor can be greatly reduced, and the size difference with silicon due to barrier layer impurity Arsenic (As) and phosphorus (P) with low misfit factors due to the use of crystal lines of epitaxial layers can be used. And it can improve the yield it can minimize the occurrence of (Crystalline Defeet), minimize the auto-doped, lead times up diffusion so excellent doping profile of the epitaxial layer and has an effect which can improve the electrical characteristics of the device.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900003162A KR0144340B1 (en) | 1990-03-09 | 1990-03-09 | Method of fabricating ultra thin epitaxial film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900003162A KR0144340B1 (en) | 1990-03-09 | 1990-03-09 | Method of fabricating ultra thin epitaxial film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR910017533A KR910017533A (en) | 1991-11-05 |
| KR0144340B1 true KR0144340B1 (en) | 1998-08-17 |
Family
ID=19296839
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019900003162A KR0144340B1 (en) | 1990-03-09 | 1990-03-09 | Method of fabricating ultra thin epitaxial film |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0144340B1 (en) |
-
1990
- 1990-03-09 KR KR1019900003162A patent/KR0144340B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR910017533A (en) | 1991-11-05 |
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