JPH02106035A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To prevent the deterioration in the uniformity and the reproducibility of element characteristics by arranging two kinds of protective films for annealing so as to be laminated, selectively activating implantation ion, and electrically isolating elements. CONSTITUTION:Two kinds of protecting films 3, 5, whose film properties are mutually different, are arranged on a GaAs substrate 1 so as to be laminated, and an annealing process for activation is contained. At the time of activation annealing, the evaporation of As atom is little, implantated impurity is easy to enter a Ga site, and the activity ratio is high, in a region where the film 3 having high blocking activity for As atom diffusion is formed. On the other hand, the implanted impurity enters also the As site, the activity ratio decreases, and elements are isolated by the generation of a depletion layer, in the region where a film 5 having a low blocking ratio is formed. Thereby, the decrease in electric characteristics, uniformity and reproducibility caused by element isolation can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of manufacturing various gallium arsenide semiconductor devices using ion implantation technology.

[Conventional technology]

Due to advances in ion implantation technology for gallium arsenide, Ga
Development of As Ic is progressing.

When manufacturing GaAs Ic or the like using ion implantation technology, in recent years electrical isolation between element groups has been achieved by selective ion implantation using a resist.

FIG. 3 is a process diagram showing the process of isolation between elements by conventional selective ion implantation. First, as shown in FIG. 3(A), a resist 24 is applied on a semi-insulating GaAs substrate 21, and a After buttering as shown in Figure (B), ions of n-type impurities such as silicon are implanted as shown in Figure 3 (C), after which the resist 24 is removed, activation annealing is performed, and ions are implanted. Resist 24 between areas 27
So-called isolation between elements is performed by separating the elements by regions where ions are not implanted.

[Problem to be solved by the invention]

By the way, in such a conventional method, the resist 24 is coated on the GaAs substrate, patterned to expose the active layer formation portion, and then ion implantation is performed. However, when the active layer is thin, the electrical characteristics of the active layer are easily affected by the substrate surface condition, and surface contamination impairs the characteristics, uniformity, and reproducibility. result.

As a measure to prevent contamination of the substrate surface by such a resist, there is a conventional through-injection method using an insulating film. In this method, after forming a thin insulating film such as a SiN film on a substrate,
This method involves coating and patterning a resist, and then injecting ions through the insulating film.

This method avoids contamination of the substrate surface by covering the substrate surface with an insulating film, but the characteristics of the active layer are directly affected by the thickness and quality of the insulating film, and when the active layer is thin, It is extremely difficult to maintain electrical characteristics, uniformity, and reproducibility at the level required for IC (particularly digital IC) manufacturing.

The present invention has been made in view of the above circumstances, and its purpose is to provide a method for manufacturing semiconductor devices that can prevent deterioration in electrical characteristics, uniformity, and reproducibility caused by separation between devices. It is on offer.

[Means to solve the problem]

The method for manufacturing a semiconductor device according to the present invention includes a step of laminating two types of protective films having different film qualities on a GaAs substrate and performing activation annealing.

It also includes a step of performing isolation between elements based on the difference in activation rate between two types of protective films of different film quality stacked on the GaAs substrate.

[Effect]

In the present invention, when activation annealing is performed, As atoms evaporate less in regions where a film with a high blocking ability for As atoms is provided, implanted impurities easily enter Ga sites, and the activation rate decreases. In a region where a film with a high stopping power and a low stopping power is provided, the implanted impurity also enters the As site, the activation rate decreases, depletion occurs, and isolation between elements is achieved.

[Example 1] The present invention will be specifically explained below based on the drawings.

FIG. 1 is a diagram showing the main steps when the method of the present invention is applied to a MESFET having only an n-type active layer. First, as shown in FIG. 1(a), St" ions are implanted into the entire surface of a semi-insulating GaAs substrate 1 to form an implanted layer 2, and then a layer 2 is formed on the surface of the semi-insulating GaAs substrate 1, which has a blocking ability against the diffusion of As atoms, such as SjN. A high protective film 3 is formed to a thickness of 100 mm.

The ion implantation conditions for St” ions are 15KeV, ?ffi
degree: IXIO 13 cm-''. The protective film 3 is formed by, for example, ECR (Electron Cyclotro
n Re5onance) Plasma CVD (Chemi
Cal Vapor Deposition) method under the following conditions.

SiH4 gas flow rate: 13 secM N2 gas flow rate: 305 CCM Micro-electrified crab 600 cut substrate Temperature: room temperature Next, after patterning the resist 4 on the surface of the protective film 3 as shown in Fig. 1 (b), the resist 4 was patterned as shown in Fig. 2 (b). As shown in c), the protective film 3 is removed by etching except for the active layer portion covered with the resist 4.

As shown in FIG. 1(d), a protective film 5 made of SiN or the like having a low stopping power against As atoms is coated over the surface of the protective film 3 and the exposed surface of the injection layer 2 with a thickness of 50% and the same <
A protective film 6 made of SiN or the like and having a high blocking ability against As atoms is formed in a thickness of 500 layers.

The formation of the protective films 5 and 6 is also performed using the ECR plasma CVD method or the like.

(Preparation conditions for protective film 5) SiH4 gas flow rate: 40SCCM N2 gas flow rate: 25SCCM Microwave type crab 300W substrate Temperature: room temperature This protective film 5 has a high silicon content and high hydrogen content, and has a high As content during activation annealing. This film has a low stopping power against atomic diffusion.

(protection)l! (Production conditions in 6) This is the same as the protective film 3.

Next, by performing activation annealing at 850° C. for 5 seconds using a lamp annealing device or the like, as shown in FIG.
is formed, and isolation between elements is achieved.

Note that after activation annealing, the diffusion of ^S atoms into the film was below the measurement limit when analyzed by Auger electron spectroscopy.

[Embodiment 2] FIG. 2 is a main process diagram showing another example in which the method of the present invention is applied to a MESFET having an n-type operating layer and a deep n-type operating layer.

First, as shown in FIG. 2(a), St'' ions are implanted to a predetermined depth into the surface of a semi-insulating GaAs substrate 1 to form an implantation layer 2, and a protective film 3 of high stopping power such as SiN is formed on the surface. 10
Form to a thickness of about 0 people.

Thereafter, as shown in FIG. 2(B), the resist is patterned and the protective film 3 other than the active layer portion is removed by etching. 5 to about 400 people, followed by Si
Protective film 6 with high blocking ability against diffusion of S atoms in N etc.
About 500 people stacked it to form a layer.

Patterning the resist 9 as shown in FIG. 2(d),
Source of FET as shown in Figure 2 (e).

Protective films 3, 5 .
Through-implanting St'' ions through 6.

The implantation conditions are 150KeV, 5Xl013c+n-
” is.

The resist 9 is removed and activation annealing is performed.

As a result, as shown in FIG. 2(f), the source 11. A depletion region 8 is formed between the drain 12 and adjacent devices to achieve blocking isolation.

〔effect〕

As described above, in the method of the present invention, by stacking two types of annealing protective films, implanted ions can be selectively activated and electrical isolation between elements can be achieved, and surface contamination of the active layer can be prevented. The present invention has excellent effects such as uniformity of device characteristics and reproducibility without deterioration.

[Brief explanation of drawings]

FIG. 1 is a process diagram of the method of the present invention, FIG. 2 is a process diagram showing another embodiment of the invention, and FIG. 3 is a process diagram of the conventional method. 1... GaAs substrate 2... Injection layer 3... As
Protective film with high blocking ability against diffusion of atoms 4...Resist 5...Protective film with low blocking ability against diffusion of As atoms 6...Protective film with high blocking ability against diffusion of As atoms 7...Operation Layer 8: Depletion area patent Applicant: Sanyo Electric Co., Ltd. Representative patent attorney Noboru Kawano Funeral map

Claims (1)

[Claims] 1. A method for manufacturing a GaAs semiconductor device using an ion implantation method, including the step of laminating and arranging two types of protective films of different film quality on a GaAs substrate and performing activation annealing. A method for manufacturing a semiconductor device, characterized by: 2. A method for manufacturing GaAs semiconductor devices using ion implantation includes a step of separating devices based on the difference in activation rate between two types of protective films of different film quality stacked on a GaAs substrate. Features: A method for manufacturing semiconductor devices.