JPS62213131A - Manufacture of iii-v semiconductor device - Google Patents

Abstract

PURPOSE:To enable the attainment of the insulative isolation between field effect transistors without impairing the surface smoothness of a semiconductor substrate, by a method wherein the surface of a P-type III-V semiconductor layer is covered with silicon oxynitride film except for a region for forming the field effect transistors having an N-channel and a P-channel, and infrared short-time annealing is applied thereto. CONSTITUTION:When a deep electron trap is introduced from outside into a P-type conductor layer 2, the level of electrons caught so far by the electron trap lowers to a shallow acceptor level, and therefore the emission of free holes into a valence band is hindered. When a shallow acceptor level concentration is denoted by N, and a deep electron trap concentration by NDD, a free hole concentration (p) is expressed by p=NA-NDD. If NDD is introduced in a more quantity than NA, accordingly, (p) turns less than 0, and a semiconductor 1 turns to be of high resistance. When infrared short-time annealing is applied to a P-type III-V semiconductor whose surface is covered with a silicon oxynitride film 8, the deep electron trap is formed, and consequently high resistance is attained. By this method, the insulative isolation between field effect transistors can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing an IV group semiconductor device, and particularly to a method for manufacturing a IV group semiconductor device using an ion implantation method.

I'Prior art] In recent years, with the aim of increasing the speed of semiconductor integrated circuits, G
Development of aAs integrated circuits is actively underway. GaA
A field effect transistor is generally used as a basic element of an integrated circuit. N-type layers formed by epitaxial or ion implantation methods are widely used as active layers in field-effect transistors, but in recent years Ga
Complementary circuits are also attracting attention for the purpose of reducing power consumption in As1l product circuits (for example, a paper by Nakayama et al. is listed on page 551 of the proceedings of the 45th Annual Conference of the Japan Society of Applied Physics). In the complementary circuit, in addition to the conventional n-type operation layer, it is necessary to form an n-type operation layer on the same substrate, E, with good controllability. In order to operate the n-channel field effect transistor and the p-channel field effect transistor manufactured on the same substrate as independent elements, it is necessary to electrically insulate the two types of field effect transistors. As a method of electrically insulating two conductive regions, a method using mesae...I trenching is well known. FIG. 3 shows a cross-sectional view of a semiconductor chip showing an example of a conventional ■-v group semiconductor device. In the mesa etching method,
A part of the p-type GaAs layer 2, which is a conductive layer, is selectively removed using an etching liquid or an etching gas to electrically insulate the two types of field effect transistors.

[Problem that the invention seeks to solve]

The conventional method of manufacturing a 1-V group semiconductor device in which the conductive layer is selectively removed by the above-mentioned mesa-etching method has the advantage of being simple and ensuring reliable isolation. However, the portion ili formed by etching! Since the groove significantly deteriorates the flatness of the semiconductor substrate, it has the disadvantage that it tends to cause disconnection of the electrode wiring. Therefore, from the viewpoint of yield, it is not preferable to use such a mesa etching separation method as a manufacturing process for large-scale integrated circuits.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a 1-V group semiconductor device, which enables isolation between elements without impairing the flatness of a semiconductor substrate.

[Means for solving problems]

The manufacturing method of the ■-V group semiconductor device of the present invention is based on the method of manufacturing a p-type 1 [1-V group semiconductor layer epitaxially grown on a semi-insulating substrate 1] by using an ion implantation method on a field-effect semiconductor layer having an n-channel and a p-channel, respectively. A method comprising at least a step of forming a transistor, and a step of covering the surface of the p-type 111-V group semiconductor layer other than at least the field effect transistor forming region with a silicon oxynitride film, and then performing short-time infrared annealing. be.

[Effect]

The present invention is based on the principle that a shallow acceptor level in a p-type semiconductor is compensated for by a deep electron trap, thereby increasing the resistance of the semiconductor. I[[-In group V semiconductors, Be
, Ml, Zn, etc. are known as acceptor impurities, and all of these impurities form a shallow acceptor level, emit free holes to the valence band, and exhibit p-type conductivity. When a deep electron trap is introduced from the outside into this p-type conductive layer, the electrons trapped in the electron trap fall to the shallow acceptor level, which prevents free holes from being released into the valence band. It will be done. Now, if the shallow acceptor level concentration is expressed as 1 and the deep electron I/wrap concentration as 1 Joo, then the free hole concentration p is expressed as p=N^-NDD. Therefore, if a larger amount of 1loo than N^ is introduced, p<0 and the semiconductor becomes highly resistive.

When a p-type ■-■ group semiconductor whose surface is covered with a silicon oxynitride film is subjected to short-time infrared Il annealing, deep electron traps are formed and the resistance increases, making it possible to perform insulation separation between field-effect transistors. can.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) to 1(f) are cross-sectional views of semiconductor chips arranged in the order of manufacturing steps for explaining one embodiment of the present invention.

As shown in Figure 1(a), LEC with surface orientation <100>
(Liquid t! neapsulated Cz
Andog semi-insulating Ga by the ochralski method
A vapor phase growth method (M
(O-CVD method) hole concentration I x 1017ct
A p-type GaAs layer 2 with a thickness of 150 nm is epitaxially grown. In addition to the MO-CVD method, a liquid phase growth method, a vapor phase growth method, a molecular beam epitaxial growth method, etc. may be used.

Next, as shown in FIG. 1(b), 30% Si ions were added.
N-type channel region 3 is formed by selectively implanting 3×10” C11-2 at keV.

Next, as shown in FIG. 1(C), 500 nrn of a heat-resistant metal (for example, WSix) is sputter-deposited as a gate metal, and dry etching is performed using SF6 gas to form a layer on the n-type channel region 3 and the p-type GaAs layer. A gate electrode 4 having a gate length of 1 μm is selectively formed on each of the gate electrodes 2 and 2 . The p-type GaAs layer 2 in contact with the gate electrode 4 serves as a p-type channel region.As shown in FIG. 1(d), a field effect transistor having p-type and p-type channels is formed. As the contact layer for the source and drain regions of
The n4 contact layer 5 and the p1 contact layer 6 are each formed in a self-lined manner by implanting 3.times.10" am@-2 at VV.

Next, as shown in FIG. 1(e), as an annealing protective film for the ion implantation layer, a 5fJ4 film 7 is applied to the p channel region and the p+ contact layer 6, and a refractive index 1 film 7 is applied to the other regions. Silicon oxynitride (SiOx
Ny) films 8 are each deposited to a thickness of 1100 nm. This 5iO
Any known method may be used to deposit XN, but for example, as described in Japanese Patent Application Laid-Open No. 60-39837,
8me/ff1in).

A vapor phase growth method may be used in which 02 (flow rate 20 mf/sin) is intermittently introduced into NH3 (flow rate 400 m e /win). When using this method, 02 gas is introduced for 1 second at intervals of 15 seconds. When performed periodically, S with a refractive index of 1.75
An iO,N, film (actually, a laminated insulation JI of a layer with a high nitrogen composition and a layer with a low nitrogen composition!) is obtained.

Next, using a tungsten halogen lamp,
Infrared short-time annealing is performed at ℃ for 3 seconds.
g) or transient annealing (traosi-c)
This is also called nt annealing. As a result, in the ion-implanted region, p-type and p-type
A type conductive layer is formed, but in the areas where ion implantation was not performed, a large amount of electron traps (EL2) are introduced by infrared short-time annealing, resulting in a resistivity of 5X1.
A high resistance GaAs layer 9 having a resistance of 06 to 1.times.10.sup.7 .OMEGA..multidot.1 is formed.

FIG. 1(f) shows the state when the 5iJ4 film 7, SiO, N, and film 8 are removed.

A deep electron trap in a GaAs semiconductor is an EL with an activation energy of about 0.8 eV from the bottom of the conduction band.
The 2nd level is well known. Although there are still many unknowns about the identity of this EL2 level, its concentration often changes with heat treatment.

Figure 2 shows the surface of an n-type GaAs substrate that does not contain the EL2 level after being coated with various protective films made of SiO and N.
This figure shows the dependence of the EL2 concentration on the refractive index of the protective film when short-time infrared annealing is performed at 0° C. for 3 seconds. SiO, N with a refractive index of 1.7 to 1.8.

When annealing is performed using a protective film, the generation of the EL2 level is maximized. This is Sin for p-type GaAs.

This shows that it is possible to increase the resistance of a p-type GaAs layer by performing short-time infrared annealing using a N,I protective film.

In this way, through the annealing process of the ion implanted layer,
A conductive layer can be formed in the ion-implanted region and a high-resistance layer can be formed in the non-ion-implanted region at the same time, and device isolation between each field effect transistor having an n-channel and a p-channel can be achieved in a planar state. becomes. The mutual conductance of the complementary field effect transistor prototyped using this method is 200 t in the n-type channel.
n S/layer ■ (threshold voltage: -0, IV), p
30m5/m5 (L threshold voltage knee 0.AV
) showed the characteristics of In addition, the withstand voltage between two field effect transistors having the same conductivity type is good at more than IOV,
Results sufficient to prove the usefulness of the present invention were obtained.

〔Effect of the invention〕

By using the method of the present invention, n-channel and ρ
This has the advantage that element isolation between two types of field effect transistors each having a channel can be achieved without impairing the surface flatness of the semiconductor substrate.

[Brief explanation of drawings]

1(a) to 1(f) are cross-sectional views of semiconductor chips arranged in the order of manufacturing steps for explaining one embodiment of the present invention;
The figure is a characteristic diagram for explaining the present invention in detail, and FIG. 3 is a sectional view of a semiconductor chip showing an example of a conventional nI-V group semiconductor device. 1...Semi-insulating GaAs substrate, 2...p-type GaAs
layer, 3... n-type channel region, 4... gate electrode,
5...n+ contact layer, 6...p+ contact layer, 7...Si3N4 film, 8-5iO,N layer, 9...
・High resistance GaAs layer. Figure 1/, 4/, 7 1J 2. θS
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Claims (1)

[Claims] p-type III-V epitaxially grown on a semi-insulating substrate
forming a field effect transistor having an n-channel and a p-channel on the group semiconductor layer using ion implantation; and oxidizing at least the surface of the p-type III-V group semiconductor layer other than the field effect transistor formation region. III- characterized by having at least a step of performing short-time infrared annealing after covering with a silicon nitride film.
A method for manufacturing a group V semiconductor device.