JPS61158181A - Manufacture of mis-type semiconductor device - Google Patents

Abstract

PURPOSE:To realize a semiconductor device with its ON resistance lower and switching speed higher by a method wherein the width of a channel region is narrowed. CONSTITUTION:On a low-temperature N-layer 2 covering a semiconductor substrate N<+>-layer 1, an SiO2 insulating films 5a, 5b, polycrystalline silicon layer 6 for electrodes, CVD-SiO2 layer 5C are formed by deposition, in that order. A photoresist 7 is formed thereon, wherewith the polycrystalline silicon layer 6 is patterned, which is followed by the implantation of P<+>-type impurity ions. A process follows wherein the photoresist 7 is removed, heating is accomplished for the formation of a P<+>-type layer 3b, and then low-temperature P-type impurity ions 4a are implanted. The pattern of the CVD-SiO2 layer 5C is removed, and thermal diffusion is accomplished for the formation of a P-layer 4b for a channel region. After this, a source N<+>-type region is formed by means of ion implantation, a CVD-SiO2 layer 5d is deposited, heat treatment is accomplished and, finally, a contact hole is provided for the construction of an Al electrode 9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, particularly an MIS type semiconductor device.

[Technical background of the invention and its problems] Among MIS type semiconductor devices, MOS FETs (insulated gate field effect transistors) in particular have been well known as low voltage and low power devices, but recently, high voltage and low power devices have been used.
It has become possible to design high-power devices and is now used as a power device.

Next, we will introduce the conventional high-voltage power MO8FET known as Retei DSA (formerly RFUS-5ELF-A).
1i17nleint) structure FET (hereinafter referred to as D-M
A method of manufacturing the O8FET will be described with reference to FIG.

First, an n-type semiconductor [12] is formed on an n+ semiconductor substrate 1, a P+ layer 3 is selectively formed, and a gate oxide film 5a is formed to a thickness of, for example, 1000^ on the surface thereof (see Fig. 3(a).
)). Next, a polycrystalline silicon pattern 6a that will become a gate electrode is formed to a thickness of, for example, 6000^, and the part where the pattern is not formed is used as an opening window, and an n-type impurity,
For example, a p-type semiconductor layer 4 is formed below the opening by ion implanting boron and performing a diffusion process. This p
This is a portion where the type semiconductor layer 4 becomes a channel region. (Figure 3(b)). Next, a resist film 7 is formed in the middle part of the opening by a photo process, and the polycrystalline silicon pattern 6a and the oxidized portion 115a where the resist film 7 is not formed are removed by etching (see FIG. 3).
C)). Next, by forming an n-type impurity, such as phosphorus or arsenic, by ion implantation and then performing diffusion, an n + -type semiconductor 1!18 is formed on the p-type channel region. Furthermore, by removing the mask pattern, the structure shown in FIG. 3(d) is obtained. PSGW using the CVD method
For example, A5G is formed with a thickness of 8000^ (see Fig. 3).
e)). Next, by performing anisotropic etching on the upper part of the p+ pear-shaped source region, the oxide film 5a and PSGl are etched.
15c is removed to form an opening. Thereafter, an aluminum electrode 9 is formed to obtain a structure as shown in FIG. 3(f).

As described above, since the p-type channel region and the n+ type source region were diffused using one opening of the conventional MIS type half-type semiconductor device, there was a problem that the threshold value varied. This is because diffusion normally goes in the lateral direction, resulting in a lower concentration, but since the n+ type layer is further diffused there, the lower concentration part of the previous p type diffusion layer must be used as the channel region. Depends on what you don't get. For this reason, in the past, the p-channel layer was formed deep, for example, 4 to 5 .mu.m, and the nI layer was formed as narrow as 1 .mu.m, so as not to be affected by the concentration. The fact that the channel width cannot be narrowed means that the gm cannot be made large, which leads to the big problem that the ON resistance cannot be lowered and the switching speed cannot be improved.

[Object of the invention] The present invention has been made in view of the above circumstances, and the present invention has been made in view of the above circumstances.
It is an object of the present invention to provide a method for manufacturing a semiconductor device that can reduce the ON resistance and improve the switching speed by narrowing the width of the channel region of the semiconductor device.

[Summary of the Invention J In order to achieve the above object, the present invention includes a step of forming a semiconductor or conductor layer on the main surface of a conductor substrate of a first conductivity type via a first insulating film, and a step of forming a semiconductor or conductor layer on the main surface of a conductor substrate of a first conductivity type. a step of selectively patterning the second insulating film so that an opening is automatically formed; and a step of patterning the second insulating film using a part of the second insulating film pattern as a mask. After selectively patterning the semiconductor or conductor layer, a first semiconductor device of a conductivity type opposite to the first conductivity type is placed on the first conductivity type semiconductor substrate using the second insulating film or the semiconductor or conductor layer as a mask. forming a second semiconductor layer of the opposite conductivity type to the first conductivity type in the first conductivity type semiconductor substrate by performing ion implantation through the semiconductor or conductor layer from the opening of the second insulating film pattern; and a step in which at least the first semiconductor layer and the second semiconductor layer are electrically connected on the main surface of the semiconductor substrate directly under the first insulating film. .

[Embodiments of the invention] Examples of the present invention are shown in FIGS. 1<a) to (CI).

First, on an n-on n+ substrate having a 0 layer 2 with a lower concentration than this on an n+ layer of a semiconductor substrate, about 4000 8 5i
Form O25 and selectively pattern. Next, thermal oxidation 15a that will become the gate 5102 is formed to a thickness of approximately 1000 mm, and polycrystalline silicon 6 for the gate electrode is formed thereon to a thickness of approximately 3000 mm.
A deposited and further formed on top of it by CVD method.
Deposit approximately 6000A of o-si025G (first
Figure (a)).

Next, the CvD-8'1
Selectively patterning 025C (Fig. 1(b))
. Next, the photoresist is left on the desired pattern using photoetching technology, used as an etching mask with CVD 5i025G, patterning is carried out on polycrystalline silicon 6, and P+ impurity ion implantation, for example boron ions 3a, is carried out at a dose of 6X 10 "tya-". 20 in
It is implanted with an acceleration energy of about 0 KeV (Fig. 1 (
C)). The photoresist is then removed by a etchant, e.g.
Diffusion is performed at a temperature of about 0° C. to form P” 13b. After that, in order to form a channel region, low concentration P type impurity ions 4a, such as boron ions, are added at 1×10
Implantation was performed at a dose of 14 cR-'' and an acceleration energy of 150 KeV (FIG. 1(d)).

At this time, boron ions are insulating! *50 Passes through the polycrystalline silicon directly under the opening and reaches the n-type silicon substrate 2,
A channel p-type layer 4a is formed here.

Next, after selectively etching the CVD-3i 025C pattern, one layer 4b of the channel region is formed by thermal diffusion (FIG. 1(e)). After that, the source n" region 8 is formed by ion implantation, and then the 1CVD-8i 025G
After depositing about 8000A, heat treatment is performed (see Fig. 1(f)
)). Finally, a contact hole is formed and an AI electrode 9 is formed to obtain the structure shown in FIG. 1(g).

In addition, CVD-3i025C mentioned in this example
, PSG, 5i3Na, or an alumina film. Further, although polycrystalline silicon 6 was used as the gate electrode material, there is no need to be particular about this material; for example, MO, N+.

Melting point metals such as W, Ti, Ta, etc., or metal silicides such as molybdenum silicide, nickel silicide, danksten silicide, platinum silicide, etc. may be used.

In this example, ions are implanted through the polycrystalline silicon layer that is the gate electrode material to form the channel region.
The greatest feature is that there is no concentration gradient in the channel region, and therefore an element with a constant gate threshold voltage vth can be formed. Next, the second embodiment to be described is an embodiment that takes advantage of the above characteristics and also lowers the gate wiring resistance by increasing the thickness of the polycrystalline silicon layer.

[Second example] Other embodiments are shown in FIGS. 2(a) to 2(f).

First, on a semiconductor substrate having an n+ layer 1 and an 0 layer 2, a gate oxide layer 15a is formed on the substrate to a thickness of about 1,000 yen, a gate electrode of polycrystalline silicon 6 is formed on the substrate to a thickness of about 8,000 yen, and an insulating film, e.g. Approximately 300 OA of 5i3N45C is deposited, first a selective etching pattern is formed on 5i3Na by photo-etching, and the polycrystalline silicon underneath is anisotropically etched halfway to approximately 400 OA using the same etching mask (second Figure (a)).

Incidentally, the anisotropic etching was performed by reactive ion etching, which is a general dry etching.

Next, photoresist 7 was formed using photoetching technology.
is formed, and P+ type impurity ions 3a are ion-implanted (
Figure 2(b)). Next, the photocyst 7a is removed, and a P+ layer 3b is formed by diffusion, so that the P-type impurity ions 4a are allowed to pass through only the groove of the polycrystalline silicon 6 in the recess.
For example, impurity ions such as boron are heated to about 200 to 300K.
Ion implantation is performed with acceleration energy such as eV (Figure 2 (
C)). Next, diffusion is performed to form a channel region P pattern 4b, and then a photoresist pattern 7b is formed again by photoetching technique. Next, to form a source region, n++ impurity ions 8a, for example, phosphorus, are added to 6X10"011
It is implanted with an acceleration energy of approximately 100 KeV at a dose of 4 (Fig. 2(d)).

At this time, if 31P+ ions are implanted with an acceleration energy of 100 KeV, the projection range of 31p" in 3i is about 1000. In other words, since the peak value of the highest concentration is about 1000, polycrystalline silicon 31p+ ions do not pass through the groove of the recess.Next,
50 OA of thermally oxidized FJ5e is formed, approximately 6000 OA of CVD 115d is deposited, and heat treatment is performed to form the source n+ region 14.
8b (Fig. 2(e)). Finally, a contact hole is formed and an AIN pole 9 is formed to obtain the structure shown in FIG. 2(f).

[Effects of the Invention] According to the present invention detailed above, the distance between the channel and the source region can be formed accurately, a channel region with a constant surface concentration can be formed, and the channel width can be narrowed. Since it is not affected even if non-uniformity of impurity m degree occurs due to the principle of diffusion, it is possible to provide a semiconductor device that can prevent variations in the threshold value, can increase the length of 9 m, has a small on-resistance, and can improve the switching speed.

[Brief explanation of the drawing]

FIGS. 1(a) to (a) are cross-sectional views showing one embodiment of the present invention in the order of steps, and FIGS. 2(a) to (f) are cross-sectional views showing another embodiment of the present invention in the order of steps. and Fig. 3(a)
7(f) are cross-sectional views showing the conventional manufacturing method in the order of steps. 1... n+ type semiconductor substrate, 2... n type semiconductor layer, 3
...Oxide film, 4...Polycrystalline silicon layer, 5...n
type semiconductor layer, 6... Nitride film, 7... N1 type semiconductor device Figure 3 (f) Procedural amendment February 7, 1985 2. Title of invention Method for manufacturing MTS type semiconductor device 3. Amendment Patent applicant 5. Date of amendment order. 6. Detailed description of the invention and brief description of the drawings to be amended. 7. Contents of the amendment (1). 4. "Photo process" in the 5th line of the page is corrected to "photo etching process." (2) Delete the sentences from lines 7 to 10 on page 12, and insert the following sentences in their place. Note: 1...0+ type half layer, 2...n
type semiconductor substrate, 3b...p diffusion layer, 58-5
G: Insulating film, 6: Polycrystalline silicon, 8: Source n+ layer, 9: Aluminum electrode. ”

Claims (4)

[Claims] (1) A step of forming a semiconductor or conductor layer on the main surface of a semiconductor substrate of a first conductivity type via a first insulating film, a step of forming a second insulating film thereon, and a step of forming a second insulating film thereon; selectively patterning the insulating film of the first conductive type semiconductor substrate after selectively patterning the semiconductor or conductive layer using a part of the second insulating film pattern as a mask; forming a first semiconductor device of a conductivity type opposite to that of the mold using the second insulating film or the semiconductor or conductor layer as a mask; and forming the semiconductor or conductor layer from the other opening of the second insulating film pattern. forming a second semiconductor layer opposite to the first conductivity type in the first conductivity type semiconductor substrate by performing ion implantation through the first conductivity type semiconductor substrate; M characterized in that it includes a step of electrically connecting on the main surface of the semiconductor substrate directly under the film.
A method for manufacturing an IS type semiconductor device. (2) The method for manufacturing an MIS type semiconductor device according to claim 1, wherein the semiconductor layer formed on the first insulating film is polycrystalline silicon. (3) forming a recess in a part of the polycrystalline silicon pattern; and implanting ions into the semiconductor substrate immediately below the first insulating film through the recess of the polycrystalline silicon layer; MI according to claim 1 or 2, characterized in that the MI includes the step of forming two semiconductor layers.
A method for manufacturing an S-type semiconductor device. (4) A MOS type semiconductor device is manufactured in which the semiconductor substrate is used as a drain, the first insulating film is used as a gate insulating film, the semiconductor layer is used as a gate electrode, and the second semiconductor layer is used as a channel region. The method for manufacturing an MIS semiconductor device according to any one of items 3 to 3.