JPS6180862A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6180862A JPS6180862A JP20270984A JP20270984A JPS6180862A JP S6180862 A JPS6180862 A JP S6180862A JP 20270984 A JP20270984 A JP 20270984A JP 20270984 A JP20270984 A JP 20270984A JP S6180862 A JPS6180862 A JP S6180862A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- silicon layer
- semiconductor device
- substrate
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 78
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000012535 impurity Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 19
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 14
- 239000010410 layer Substances 0.000 claims description 44
- 238000000151 deposition Methods 0.000 claims description 13
- 238000005468 ion implantation Methods 0.000 claims description 10
- 150000002500 ions Chemical class 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 7
- 239000011229 interlayer Substances 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 12
- 239000011574 phosphorus Substances 0.000 abstract description 12
- 239000000463 material Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 238000007669 thermal treatment Methods 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 230000001133 acceleration Effects 0.000 description 6
- 230000010354 integration Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 1
- 229910015890 BF2 Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910021339 platinum silicide Inorganic materials 0.000 description 1
- 238000005063 solubilization Methods 0.000 description 1
- 230000007928 solubilization Effects 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising semiconducting material
Abstract
Description
【発明の詳細な説明】
〔発明の技（付分野〕
本発明は、半導体装置の製造方法に関し、特にＭＩＳ型
半導体装置のソース、ドレイン領域と多結晶シリコンか
らなる配線との接続工程を改良した方法に係わる。[Detailed Description of the Invention] [Techniques of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and in particular, to an improved process for connecting the source and drain regions of an MIS type semiconductor device to wiring made of polycrystalline silicon. It concerns the method.
最近、半導体装置の高集積化の目的から多層配線技術が
多く採用され、それに伴ってソース、ドレイン領域と接
続する配線を多結晶シリコンにより形成したＭ ＯＳ型
半導体装置が開発されている。Recently, multilayer wiring technology has been widely adopted for the purpose of increasing the degree of integration of semiconductor devices, and MOS type semiconductor devices in which wiring connecting source and drain regions are formed of polycrystalline silicon have been developed.
こうした半導体装置（例えばｎチャンネルＭＯ８型半導
体装置）は、従来、次のような方法によって製造されて
いる。Such semiconductor devices (for example, n-channel MO8 type semiconductor devices) have conventionally been manufactured by the following method.
まず、ｐ型シリコン基板の主面に素子分離領域としての
フィールド酸化膜を形成した後、熱酸化処理を施してフ
ィールド酸化膜で分離された基板の島領域にゲート醒化
膜を形成する。つづいて、全面にゲート電極材料膜であ
る多結晶シリコン膜を堆積した後、該多結晶シリコン膜
をパターニングしてゲート電極を形成する。ひきつづき
、前記フールド酸化膜及びゲート電極をマスクとしてｎ
型不純物、例えばリンを基板の島領域にイオン注入し、
活性化してｎ＋型のソース、ドレイン領域を形成する。First, a field oxide film is formed as an element isolation region on the main surface of a p-type silicon substrate, and then thermal oxidation is performed to form a gate oxidation film on the island region of the substrate separated by the field oxide film. Subsequently, after depositing a polycrystalline silicon film as a gate electrode material film over the entire surface, the polycrystalline silicon film is patterned to form a gate electrode. Subsequently, using the field oxide film and gate electrode as a mask,
ion implantation of a type impurity, e.g. phosphorus, into the island region of the substrate;
Activation forms n+ type source and drain regions.
更に、全面に層間絶縁膜であるＣｖＤ−３ｉ０２１Ａを
堆積し、前記ソース、ドレイン領域に対応するＣＶＤ−
５ｉ０２膜にコンタクトホールを開口した後、全面に多
結晶シリコン膜を堆積する。次いで、多結晶シリコン膜
にリンの拡散又はイオン注入を行なった後、９５０℃以
上の熱処理を施してコンタクトホール内のｎ＋型ソース
・ドレイン領域と多結晶シリ０ンとの界面に生
１成された自然酸化膜を熱的に破壊してそれらをオーミ
ック接続する。この後、該多結晶シリコン膜をパターニ
ングしてソース、ドレインの配線を形成する。Furthermore, CvD-3i021A, which is an interlayer insulating film, is deposited on the entire surface, and CVD-3i021A is deposited on the entire surface, and CVD-3i021A is deposited on the entire surface.
After opening a contact hole in the 5i02 film, a polycrystalline silicon film is deposited on the entire surface. Next, after phosphorus is diffused or ion-implanted into the polycrystalline silicon film, heat treatment is performed at a temperature of 950°C or higher to form a layer at the interface between the n+ type source/drain region and the polycrystalline silicon in the contact hole.
1) The formed natural oxide film is thermally destroyed to establish an ohmic connection between them. Thereafter, the polycrystalline silicon film is patterned to form source and drain wiring.
ところで、Ｍ ＯＳ型半導体装置においては、集積度を
向上する目的でソース、ドレイン領域がシャロー化され
、これに伴ってソース、ドレイン領域の形成時の活性化
のための熱処理湿度が低温側に抑えられる傾向にある。By the way, in MOS type semiconductor devices, the source and drain regions are made shallow in order to improve the degree of integration, and as a result, the humidity of the heat treatment for activation during the formation of the source and drain regions is kept to a low temperature side. There is a tendency to
このため、従来のような高温熱処理の適用は困難となり
、その結果ソース、ドレインｉＩ［と多結晶シリコンと
の界面に生成された自然ａ化膜を充分に破壊できなくな
り、それら領域と多結晶シリコンからなる配線との間か
非抵抗接触となる。For this reason, it becomes difficult to apply conventional high-temperature heat treatment, and as a result, it becomes impossible to sufficiently destroy the natural aluminium film formed at the interface between the source and drain iI and polycrystalline silicon, and these regions and polycrystalline silicon There is a non-resistance contact between the wire and the wire.
本発明は、シャロー化に伴う低（品プロセスを適用した
場合でもソース、トレイン領域と多結晶シリコンからな
る配線とを良好にオーミック接続し得る高集積度で高速
動作が可能な半導体装置の製造方法を提供しようとする
ものである。The present invention provides a method for manufacturing a semiconductor device capable of high-integration and high-speed operation, which can provide good ohmic connection between the source and train regions and wiring made of polycrystalline silicon even when a low-performance process is applied due to shallow processing. This is what we are trying to provide.
（発明の概要〕
本発明は、第１導電型の半導体基板主面に素子分離領域
を選択的に形成する工程と、この素子分離領域で分離さ
れた基板の島領域にゲート絶縁膜を介して多結晶シリコ
ンからなるゲート電極を形成する工程と、前記素子分離
ｖＡ域及びゲート電ｔｆｆｉをマスクとして第２導電型
の不純物を前記島領域にドーピングして第２導電型のソ
ース、ドレイン領域形成する工程と、このゲート電極を
含む全面に層間絶縁膜を形成する工程と、前記ソース、
ドレイン領域に対応する前記層間絶縁膜にコンタクトホ
ールを開口する工程と、前記層間絶縁膜上に薄い第１の
多結晶シリコン層を堆積し、不純物を少なくとも前記コ
ンタクトホール内の多結晶シリコン層部分を通して基板
表面にイオン注入して基板と多結晶シリコン層の界面の
自然酸化膜を劣化乃至破壊する工程と、全面に第２の多
結晶シリコン層を堆積した後、前記第１及び第２の多結
晶シリコン層をパターニングしてソース、ドレインの配
線を形成する工程とを具備したことを待機とするもので
ある。かかる本発明方法によれば、既述の如くシャロー
化に伴う低温プロセスを適用した場合でもソース、ドレ
イン領域と多結晶シリコンからなる配線とを良好にオー
ミック接続できる。(Summary of the Invention) The present invention includes a step of selectively forming an element isolation region on the main surface of a semiconductor substrate of a first conductivity type, and forming an island region of the substrate separated by the element isolation region via a gate insulating film. A step of forming a gate electrode made of polycrystalline silicon, and doping impurities of a second conductivity type into the island region using the element isolation vA region and gate electric potential tffi as a mask to form source and drain regions of a second conductivity type. a step of forming an interlayer insulating film over the entire surface including the gate electrode;
a step of opening a contact hole in the interlayer insulating film corresponding to the drain region, depositing a thin first polycrystalline silicon layer on the interlayer insulating film, and introducing impurities through at least a portion of the polycrystalline silicon layer in the contact hole; After a step of implanting ions into the substrate surface to degrade or destroy the natural oxide film at the interface between the substrate and the polycrystalline silicon layer, and depositing a second polycrystalline silicon layer on the entire surface, the first and second polycrystalline silicon layers are removed. The process includes a step of patterning the silicon layer to form source and drain wiring. According to the method of the present invention, as described above, even when a low-temperature process associated with shallowing is applied, a good ohmic connection can be made between the source and drain regions and the wiring made of polycrystalline silicon.
しかも、前記イオン注入に際して低い加速電圧で第１の
多結晶シリコン層とソース、ドレイン領域との界面の自
然酸化膜を破壊して良好なオーミック接続を実現できる
と共に、ソース、ドレイン領域を所期目的の浅い接合深
さにでき、かつ接合リークを防止できる。従って、高集
積度で高速動作が可能な半導体装置を得ることができる
。Moreover, during the ion implantation, the natural oxide film at the interface between the first polycrystalline silicon layer and the source and drain regions can be destroyed by using a low acceleration voltage to realize good ohmic connections, and the source and drain regions can be connected to the desired purpose. This allows for a shallow bonding depth and prevents bonding leaks. Therefore, it is possible to obtain a semiconductor device with a high degree of integration and capable of high-speed operation.
上記第１の多結晶シリコン層の厚さは、１００〜１００
０人の範囲にすることが望ましい。この理由は、その厚
さを１００人未満にすると、ソース、ドレイン領域との
良好なオーミック接続を実現することが困難となる。一
方、該多結晶シリコン層の厚さがｉ ｏｏｏ人を越える
と、イオンを高加速電圧でイオン注入し１ｑる高価なイ
オン注入装置を必要とするばかりか、不純物が導電性を
与えるリンやボロン等の場合、イオン注入した不純物の
２度プロファイルが浅いソース、ドレイン領域の接合に
まで伸び、該ソース、トレイン領域の接合深さが所期目
的の深さより深くなり、素子の微細化を妨げたり、或い
は不純物が４電性を付与しないＡｒ等を使用した場合、
浅いソース、ドレイン領域の接合への欠陥の導入等によ
り接合リークを招く恐れが生じる。また、第２の多結晶
シリコン層の厚さは、第１の多結晶シリコン層との総和
が２００ＱÅ以上になるよう設定すればよい。The thickness of the first polycrystalline silicon layer is 100 to 100
It is desirable to set the number to 0 people. The reason for this is that if the thickness is less than 100, it becomes difficult to realize good ohmic connection with the source and drain regions. On the other hand, if the thickness of the polycrystalline silicon layer exceeds IoOO people, not only will an expensive ion implantation device for implanting 1q ions at a high acceleration voltage be required, but also impurities such as phosphorus or boron that provide conductivity will be needed. In such cases, the 2-degree profile of the ion-implanted impurity extends to the shallow junction of the source and drain regions, and the junction depth of the source and drain regions becomes deeper than the intended depth, impeding device miniaturization. , or when impurities such as Ar are used, which do not impart tetraelectricity,
There is a risk that junction leakage may occur due to the introduction of defects into the junctions of the shallow source and drain regions. Further, the thickness of the second polycrystalline silicon layer may be set so that the total thickness of the second polycrystalline silicon layer and the first polycrystalline silicon layer is 200QÅ or more.
上記不純物としては、例えばＰ、Ａｓ、Ｂ、ＢＦ２ 、
Ｓ ｉ及びＡｒの少なくとも１種を使用できる。特に
、導電性を与えない３ｉやＡｒはｎ＋型及びｐ“型の両
方のソース、ドレイン領域と多結晶シリコンとのオーミ
ック接続に適用できる。Examples of the above impurities include P, As, B, BF2,
At least one of Si and Ar can be used. In particular, 3i and Ar, which do not provide conductivity, can be applied to ohmic connections between both n+ type and p'' type source and drain regions and polycrystalline silicon.
上記不純物をソース、ドレイン領域と第１の多結晶シリ
コン層との界面にイオン注入する際には、ソース、ドレ
イン領域と多結晶シリコンとの間に生成された自然酸化
膜を破壊して良好なオーミック接続を達成する観点から
、前記界面における不純物のイオン注入量がｌＸ１０１
・６ｍ“・〜１×１ １×１０１７ｏｎ”の範囲
に設定することが望ましい。When ion-implanting the above impurities into the interface between the source and drain regions and the first polycrystalline silicon layer, the natural oxide film formed between the source and drain regions and the polycrystalline silicon is destroyed and a good From the viewpoint of achieving ohmic connection, the amount of impurity ions implanted at the interface is lX101
・It is desirable to set it in the range of 6 m ".~1×1 1×1017 on".
なお、不純物のイオン注入後に前記自然酸化膜をより確
実に破壊し、低抵抗化するために、９５０′Ｃ以下の温
度で熱処理を施してもよい。Note that after the impurity ion implantation, heat treatment may be performed at a temperature of 950'C or lower in order to more reliably destroy the natural oxide film and lower the resistance.
また、上記第１及び第２の多結晶シリコン層をパターニ
ングする前に、配線の低抵抗化を目的として該第２の多
結晶シリコン苦土に金属や金属シリサイドの膜を被覆し
てもよい。かかる金属としては、例えばモリブデン、タ
ングステン、チタン、タンタル、白金等を、金属シリサ
イドとしては、洞えばモリブデンシリサイド、タングス
テンシリサイド、チタンシリサイド、タンタルシリサイ
ド、白金シリサイド等を夫々挙げることができる。Furthermore, before patterning the first and second polycrystalline silicon layers, the second polycrystalline silicon layer may be coated with a film of metal or metal silicide for the purpose of lowering the resistance of the wiring. Examples of such metals include molybdenum, tungsten, titanium, tantalum, and platinum, and examples of metal silicides include molybdenum silicide, tungsten silicide, titanium silicide, tantalum silicide, and platinum silicide.
以下、本発明の実施例を第１図（ａ）〜（ｇ）を参照し
て詳細に説明する。Embodiments of the present invention will be described in detail below with reference to FIGS. 1(a) to 1(g).
まず、比抵抗１〜１０Ω” ｃｍ、面方位（１００）の
ρ型シリコン基ｉ反１の主面にボロンのイオン注入技術
及び選択醇化技術により素子分離領域としての厚さ４０
００人のフィールド配化膜２及び該フィールド酸化ｔ＋
！Ｊ ２下の基板表面のｐ型反転防止唐３を夫々形成し
たく第１図（ａ）図示）。っづいて、ドライ酸素雰囲気
中て熱酸化処理を施してフィールド酸化膜２で分離され
た基板１の島領域表面に厚さ２５０人のゲート酸化膜４
を成長させた後、全面に厚さ３５００人の多結晶シリコ
ン膜を堆積し、ＰＯＣ２３の雰囲気下で多結晶シリコン
膜にリン拡散を行ない該多結晶シリコン膜を低抵抗化さ
せ、更にフＡットエッチング技術により多結晶シリコン
膜をパターニングしてゲート電極５を形成した。この後
、フィールド酸化膜２及びゲート電極５をマスクとして
ｎ型不純物、例えば砒素を加速電圧４０ｋｅＶ、ドーズ
但
５ｘ １０１５ｃｍ”の条件でイオン注入を行ない、活
性化処理を徳してｎ＋型のソース、ドレイン領域６．７
を前記島＠域に形成した（同図（ｂ）図示）。First, the main surface of a ρ-type silicon substrate with a specific resistance of 1 to 10 Ω" cm and a plane orientation of (100) was formed to a thickness of 40 Ω as an element isolation region by boron ion implantation technology and selective solubilization technology.
00 field oxide film 2 and the field oxidation t+
! It is desired to form a p-type anti-inversion layer 3 on the substrate surface below J2 (as shown in FIG. 1(a)). Next, a gate oxide film 4 with a thickness of 250 nm is formed on the surface of the island region of the substrate 1 separated by the field oxide film 2 by thermal oxidation treatment in a dry oxygen atmosphere.
After growing, a polycrystalline silicon film with a thickness of 3,500 μm was deposited on the entire surface, and phosphorus was diffused into the polycrystalline silicon film in an atmosphere of POC23 to lower the resistance of the polycrystalline silicon film, and further flat etching was performed. A gate electrode 5 was formed by patterning the polycrystalline silicon film using a technique. Thereafter, using the field oxide film 2 and the gate electrode 5 as a mask, ions of an n-type impurity, such as arsenic, are implanted at an acceleration voltage of 40 keV and a dose of 5 x 1015 cm. Drain region 6.7
was formed in the island @ area (as shown in FIG. 2(b)).
次いで、全面に厚さ３０００人のＣＶＤ−８ｉＯ２膜８
を堆積した後、前記ソース、ドレイン領１戎６．７に対
応ｔ６ｃＶＤ−３ｉ○ｚｌｌＱ８にコンタクトホール９
を開口した（同図（Ｃ）図示）。Next, a CVD-8iO2 film 8 with a thickness of 3000 was applied to the entire surface.
After depositing contact holes 9 in t6cVD-3i○zllQ8 corresponding to the source and drain regions 1 and 6.7.
was opened (as shown in the same figure (C)).
つづいて、全面に厚さ４００人の第１の多結晶シリコン
層１０を堆積した後、全面にリンを加速電圧４０ｋｅＶ
、ドーズ吊ｌ Ｘ １×１０１７ ｃｍ−’の条件でイ
オン注入したく同図（ｄ）図示）。この時、コンタクト
ホール９内のソース、ドレイン領域６．７と第１の多結
晶シリコン層１０との界面には５Ｘ１０ ｃｌ’の濃
度のリンが注入され、それら界面の自然ｎｉ化股が！Ｉ
Ｉ！ｌ壊された。ひきつづき、全面に厚さ１６００人の
第２の多結晶シリコン層１１を堆積した後、リンを加速
電圧４０ｋｅＶ、ドーズｆｆ１ＩＸ１×１０１７ｃａ＋
”の条件でイオン注入した（同図（ｅ）図示）。この後
、第１及び第２の多結晶シリコン層１０．１１をフオッ
トエッチング技術によりパターニングして前記ソース、
ドレイン領域６．７とコンタクトホール９を通して接続
されたソース、トレインの配線１２．１３を形成した（
同図（ｆ）図示）。Subsequently, after depositing a first polycrystalline silicon layer 10 with a thickness of 400 nm over the entire surface, phosphorus was applied over the entire surface at an accelerating voltage of 40 keV.
, the ion implantation was performed under the condition of a dose of 1 x 1017 cm-' (as shown in Fig. 4(d)). At this time, phosphorus with a concentration of 5×10 Cl' is injected into the interface between the source and drain regions 6.7 and the first polycrystalline silicon layer 10 in the contact hole 9, and the natural nickel formation at these interfaces is formed! I
I! l It was destroyed. Subsequently, after depositing a second polycrystalline silicon layer 11 with a thickness of 1600 on the entire surface, phosphorus was heated at an acceleration voltage of 40 keV and a dose of ff1IX1×1017ca+.
Ion implantation was carried out under the following conditions (as shown in FIG. 2(e)). Thereafter, the first and second polycrystalline silicon layers 10 and 11 were patterned by photo-etching technology to form the source and
Source and train wirings 12 and 13 connected to the drain region 6.7 through the contact hole 9 were formed (
Figure (f) shown).
次いで、全面に保３１９としてのＣＶＤ−３ｉ０２膜１
４を堆積した後、９００℃の熱処理を施した（同図（Ｑ
）図示）、、この後、常法に従ってＣＶＤ−８ｉ０２１
１１１４４Ｃ］：ｚタクトホール（図示せず）を開口し
、ＡＱ膜の蒸着、パターニングにより前記ソース、ドレ
インの配置１１１２．１３とコンタクトホールを通して
接続するへ２配線を形成してｎチャンネルＭＯ８半導体
装置を製造した。Next, a CVD-3i02 film 1 as a coating 319 is applied to the entire surface.
After depositing 4, heat treatment was performed at 900℃ (see figure (Q)
), , After this, CVD-8i021 according to the usual method.
11144C]: A z tact hole (not shown) is opened, and an AQ film is deposited and patterned to form two wirings connected to the source and drain arrangement 1112.13 through the contact hole to form an n-channel MO8 semiconductor device. Manufactured.
しかして、本発明によればコンタクトホール９が開口さ
れたＣＶＤ−８ｉ０２膜８上に薄い第１のの多結晶シリ
コンＷＡｉｏを堆積した後、リンを少なくとも前記コン
タクトホール９内の多結晶シリコン層１０部分を通して
基板１表面にイオン注入することによって、基板１と第
１の多結晶シリコン層１０の界面の自然酸化膜を破壊で
きる。その結果、該第１の多結晶シリコン層１０上に、
更に第２の多結晶シリコン層１１を堆積して目的とする
厚さの配線材料層とした後、これら第１及び第２の多結
晶シリコン層１０．１１をパターニングすることにより
、高温熱処理（９５０℃以上）を施さずに、ｎ・型のソ
ース、ドレイン領域６、 １７とコンタクトへホー
ル９を通して良好にオーミック接続さ札た多結晶シリコ
ンからなる配線１２．１３を形成できる。According to the present invention, after depositing a thin first polycrystalline silicon WAio on the CVD-8i02 film 8 in which the contact hole 9 has been opened, phosphorus is added to at least the polycrystalline silicon layer 10 in the contact hole 9. By implanting ions into the surface of the substrate 1 through the portion, the natural oxide film at the interface between the substrate 1 and the first polycrystalline silicon layer 10 can be destroyed. As a result, on the first polycrystalline silicon layer 10,
Furthermore, after depositing a second polycrystalline silicon layer 11 to obtain a wiring material layer with a desired thickness, the first and second polycrystalline silicon layers 10 and 11 are patterned to undergo high-temperature heat treatment (950°C). Wires 12 and 13 made of polycrystalline silicon with good ohmic connection can be formed through the holes 9 to the n-type source and drain regions 6 and 17 and the contacts without applying any heat (over 10°C).
事実１本実施例の半導体装置において、ゲート電極５に
閾値電圧以上の電圧を印加し、かつドレイン領域７にＯ
〜ＩＯＶの電圧を印加した時のトレイン、ソース領域７
．６間の電流１ｏｓを調べたところ、第２図に示すＶ−
１特性図を得た。また、本実施例のようにコンタクトホ
ール内の配線となる多結晶シリコン模と基板の界面にリ
ンのイオン注入を行なわない以外、実施例と同様な方法
により製造されたｎチャンネルＭＯ８半導体装置につい
て、同様にドレイン、ソースｆｒ４域間の電流１ｏｓを
調ぺたところ、第３図に示すＶ−Ｉ特性図を（ｑた。こ
の第２図及び第３図より明らかな如く、本実施例で製造
されたＭＯ８半導体装置は、ドレイン領域への電圧印加
がなされると、電流がリニアに流れる。これに対し、従
来のＭＯ８Ｏ８半導体装置、トレイン領域への印加電圧
が６ｖ以上にならなければ電流が流れない。これは、ド
レイン、ソース領域と多結晶シリコンからなる配線との
コンタクト部に自然酸化膜が存在し、６Ｖ以上の電圧を
印加した時、該自然配化膜が電圧破壊されて電流が流れ
るからである。Fact 1 In the semiconductor device of this embodiment, a voltage equal to or higher than the threshold voltage is applied to the gate electrode 5, and O2 is applied to the drain region 7.
Train and source region 7 when applying a voltage of ~IOV
．． When we investigated the current 1os between 6 and 6, we found that V-
1 characteristic diagram was obtained. Further, regarding an n-channel MO8 semiconductor device manufactured by the same method as in the example except that phosphorus ion implantation was not performed at the interface between the polycrystalline silicon pattern and the substrate, which will be the wiring in the contact hole, as in this example, Similarly, when the current 1os between the drain and source fr4 regions was investigated, the V-I characteristic diagram shown in Fig. 3 was obtained (q).As is clear from Figs. In the conventional MO8O8 semiconductor device, current flows linearly when voltage is applied to the drain region.On the other hand, in the conventional MO8O8 semiconductor device, current does not flow unless the voltage applied to the train region exceeds 6V. This is because a natural oxide film exists in the contact area between the drain and source regions and the wiring made of polycrystalline silicon, and when a voltage of 6V or more is applied, the natural oxide film is destroyed by the voltage and current flows. It is.
また、上述したようにコンタクトホール９が開口された
ＣＶＤ−８ｉ０２膜８上に薄い第１のの多結晶シリコン
層１０を堆積した後、リンを少なくとも前記コンタクト
ホール９内の多結晶シリコン層１０部分を通して基板１
表面にイオン注入することによって、低い加速電圧で基
板１と第１の多結晶シリコン層１０の界面の自然配化膜
を破壊できる。その結果、自然酸化膜を破壊するための
イオン注入において、ソース、ドレイン領域ｉ域６．７
の接合が所期目的の深さより伸びることなく、浅いソー
ス・ドレイン領域を確保できる。なお、リンの代わりに
ＳｉやＡｒをイオン注入して第１の多結晶シリコン層と
ソース、ドレイン領域との界面に生成された自然酸化膜
を破壊する場合は、低い加速電圧でイオン注入できるた
め、ソース、トレイン領域の接合への欠陥の発生を防止
でき、接合リークを阻止できる。Further, after depositing a thin first polycrystalline silicon layer 10 on the CVD-8i02 film 8 in which the contact hole 9 has been opened as described above, phosphorus is added to at least the portion of the polycrystalline silicon layer 10 in the contact hole 9. Through board 1
By implanting ions into the surface, the naturally aligned film at the interface between the substrate 1 and the first polycrystalline silicon layer 10 can be destroyed with a low acceleration voltage. As a result, in the ion implantation to destroy the natural oxide film, the source and drain region i region 6.7
Shallow source/drain regions can be secured without the junction extending beyond the intended depth. Note that when ion-implanting Si or Ar instead of phosphorus to destroy the natural oxide film formed at the interface between the first polycrystalline silicon layer and the source and drain regions, the ions can be implanted at a low acceleration voltage. , the occurrence of defects in the junctions of the source and train regions can be prevented, and junction leakage can be prevented.
従って、高集積度で、高速動作が可能なｎチャンネルＭ
ｏＳ半導体装置をｉけることができる。Therefore, n-channel M with high integration and high speed operation is possible.
OS semiconductor devices can be installed.
なお、上記実施例では、ｎチャンネルＭＯ８半導体の製
造に適用した例について説明したが、ｐチャンネルＭＯ
８半導体装置及び相ｍζＭＯ８半導体装胃の製造にも同
様に適用できる。この場合、ｐチャンネルＭＯ８半導体
装置を製造する際には、第１の多結晶シリコン層を通し
て基板にイオン注入する不純物としては、ボロン等のｐ
型不純物を使用することが必要である。また、相補型Ｍ
Ｏ８半導体装置を製造する際には、各トランジスタのソ
ース、ドレイン領域と同一導電型の不純物を使用するか
、もしくは３ｉやＡｒを使用することが必要である。In addition, in the above embodiment, an example was explained in which it was applied to the manufacture of an n-channel MO8 semiconductor, but a p-channel MO8 semiconductor
The present invention is similarly applicable to the production of 8 semiconductor devices and phase mζ MO8 semiconductor packages. In this case, when manufacturing a p-channel MO8 semiconductor device, impurities such as boron are ion-implanted into the substrate through the first polycrystalline silicon layer.
It is necessary to use type impurities. Also, complementary type M
When manufacturing an O8 semiconductor device, it is necessary to use impurities of the same conductivity type as the source and drain regions of each transistor, or to use 3i or Ar.
上記実施例では、多結晶シリコンからなる配線をソース
、ドレイン領域と接続する場合について説明したが、基
板バイアスを与えるための該基板と同一導電型の拡散領
域との接続にも同様に適用できる。In the above embodiment, a case has been described in which wiring made of polycrystalline silicon is connected to source and drain regions, but the invention can be similarly applied to connection to a diffusion region of the same conductivity type as the substrate for applying a substrate bias.
以上詳述した如く、本発明によればシャロー化に伴う低
温プロセスを適用した場合でもソース、ドレイン領域と
多結晶シリコンからなる配線とを良好にオーミック接続
し得る高集積度で高速動作が可能な半導体装置製造方法
を提供できる。As detailed above, according to the present invention, even when applying a low-temperature process associated with shallowing, it is possible to perform high-speed operation with a high degree of integration that allows good ohmic connection between the source and drain regions and wiring made of polycrystalline silicon. A semiconductor device manufacturing method can be provided.
第１図（ａ）〜（Ｑ）は本発明の実施例におけるｎチャ
ンネルＭＯ８半導体ルーの製造工程を示す断面図、第２
図は本実施例のｎチャンネルＭ、Ｏ８半導体装置におけ
るＶｏ−１ｏｓの関係を示す特性図、第３図は従来のｎ
チャンネルＭＯ８半導体装置におけるＶｏ−Ｉｎｓの関
係を示す特性図である。
１・・・ｐ型シリコン基板、２・・・フィールド酸化膜
、４・・・ゲート酸化膜、５・・・ゲート電極、６・・
・ｎ４″型ソース領域、７・・・ｎ１型ドレイン領域、
８・−・ＣＶＤ−８ｉ ０２ ＩＩＩ、 ９・・・コン
タクトホール、１０・・・第１の多結晶シリコン層、１
１・・・第２の多結晶シリコン層、１２・・・多結晶シ
リコンからなるソース １配線、１３・・・多
結晶シリコンからなるドレイン配線。
第２図
ドレイン上方（Ｖ）
第３図
）−シイシ生、ＦＬ（Ｖ）1(a) to 1(Q) are cross-sectional views showing the manufacturing process of an n-channel MO8 semiconductor loop in an embodiment of the present invention;
The figure is a characteristic diagram showing the relationship between Vo-1os in the n-channel M and O8 semiconductor device of this embodiment, and FIG.
FIG. 3 is a characteristic diagram showing the Vo-Ins relationship in a channel MO8 semiconductor device. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... Field oxide film, 4... Gate oxide film, 5... Gate electrode, 6...
- n4'' type source region, 7...n1 type drain region,
8...CVD-8i 02 III, 9... Contact hole, 10... First polycrystalline silicon layer, 1
1... Second polycrystalline silicon layer, 12... Source 1 wiring made of polycrystalline silicon, 13... Drain wiring made of polycrystalline silicon. Fig. 2 Above the drain (V) Fig. 3) - Shiishi raw, FL (V)
Claims (6)
択的に形成する工程と、この素子分離領域で分離された
基板の島領域にゲート絶縁膜を介して多結晶シリコンか
らなるゲート電極を形成する工程と、前記素子分離領域
及びゲート電極をマスクとして第２導電型の不純物を前
記島領域にドーピングして第２導電型のソース、ドレイ
ン領域形成する工程と、このゲート電極を含む全面に層
間絶縁膜を形成する工程と、前記ソース、ドレイン領域
に対応する前記層間絶縁膜にコンタクトホールを開口す
る工程と、前記層間絶縁膜上に薄い第１の多結晶シリコ
ン層を堆積し、不純物を少なくとも前記コンタクトホー
ル内の多結晶シリコン層部分を通して基板表面にイオン
注入して基板と多結晶シリコン層の界面の自然酸化膜を
劣化乃至破壊する工程と、全面に第２の多結晶シリコン
層を堆積した後、前記第１及び第２の多結晶シリコン層
をパターニングしてソース、ドレインの配線を形成する
工程とを具備したことを特徴とする半導体装置の製造方
法。(1) A step of selectively forming an element isolation region on the main surface of a semiconductor substrate of a first conductivity type, and a gate made of polycrystalline silicon placed in an island region of the substrate separated by this element isolation region via a gate insulating film. a step of forming an electrode; a step of doping impurities of a second conductivity type into the island region using the element isolation region and the gate electrode as a mask to form source and drain regions of the second conductivity type; forming an interlayer insulating film over the entire surface; opening contact holes in the interlayer insulating film corresponding to the source and drain regions; depositing a thin first polycrystalline silicon layer on the interlayer insulating film; a step of implanting impurity ions into the substrate surface through at least a portion of the polycrystalline silicon layer in the contact hole to degrade or destroy a natural oxide film at the interface between the substrate and the polycrystalline silicon layer; and a step of depositing a second polycrystalline silicon layer on the entire surface. 1. A method of manufacturing a semiconductor device, comprising the step of: depositing the first and second polycrystalline silicon layers, and then patterning the first and second polycrystalline silicon layers to form source and drain wiring.
０Åであることを特徴とする特許請求の範囲第１項記載
の半導体装置の製造方法。(2) The thickness of the first polycrystalline silicon layer is 100 to 100
2. The method of manufacturing a semiconductor device according to claim 1, wherein the thickness is 0 Å.
Ａｒの少なくとも１種を用いることを特徴とする特許請
求の範囲第１項記載の半導体装置の製造方法。(3) The method for manufacturing a semiconductor device according to claim 1, wherein at least one of P, As, B, BF_2, Si, and Ar is used as an impurity.
の界面にイオン注入する際、該界面における不純物の注
入量が１×１０＾１＾７ｃｍ＾−＾３〜１×１０＾２＾
１ｃｍ＾−＾３の範囲に設定することを特徴とする特許
請求の範囲第１項記載の半導体装置の製造方法。(4) When ion-implanting impurities into the interface between the semiconductor substrate and the first polycrystalline silicon layer, the amount of impurity implanted at the interface is 1 x 10^1^7 cm^-^3 to 1 x 10^2^
2. The method of manufacturing a semiconductor device according to claim 1, wherein the distance is set within a range of 1 cm^-^3.
ーニングする前に該第２の多結晶シリコン層上に金属膜
又は金属シリサイド膜を被覆することを特徴とする特許
請求の範囲第１項記載の半導体装置の製造方法。(5) A claim characterized in that the second polycrystalline silicon layer is coated with a metal film or a metal silicide film before the film thickness of the first and second polycrystalline silicon layers is patterned. 2. A method for manufacturing a semiconductor device according to item 1.
徴とする特許請求の範囲第１項記載の半導体装置の製造
方法。(6) The method for manufacturing a semiconductor device according to claim 1, wherein a heat treatment is performed after ion implantation of impurities.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20270984A JPS6180862A (en) | 1984-09-27 | 1984-09-27 | Manufacture of semiconductor device |
| US06/780,071 US4663825A (en) | 1984-09-27 | 1985-09-25 | Method of manufacturing semiconductor device |
| US07/047,146 US4769337A (en) | 1984-09-27 | 1987-05-08 | Method of forming selective polysilicon wiring layer to source, drain and emitter regions by implantation through polysilicon layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20270984A JPS6180862A (en) | 1984-09-27 | 1984-09-27 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6180862A true JPS6180862A (en) | 1986-04-24 |
| JPH0527975B2 JPH0527975B2 (en) | 1993-04-22 |
Family
ID=16461852
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20270984A Granted JPS6180862A (en) | 1984-09-27 | 1984-09-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6180862A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61222125A (en) * | 1985-03-27 | 1986-10-02 | Rohm Co Ltd | Manufacture of semiconductor device |
| JPS6316671A (en) * | 1986-07-08 | 1988-01-23 | Nec Corp | Manufacture of silicide gate semiconductor device |
| KR100475727B1 (en) * | 1997-07-01 | 2005-07-21 | 삼성전자주식회사 | Manufacturing method of semiconductor device with low contact resistance |
-
1984
- 1984-09-27 JP JP20270984A patent/JPS6180862A/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61222125A (en) * | 1985-03-27 | 1986-10-02 | Rohm Co Ltd | Manufacture of semiconductor device |
| JPS6316671A (en) * | 1986-07-08 | 1988-01-23 | Nec Corp | Manufacture of silicide gate semiconductor device |
| KR100475727B1 (en) * | 1997-07-01 | 2005-07-21 | 삼성전자주식회사 | Manufacturing method of semiconductor device with low contact resistance |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0527975B2 (en) | 1993-04-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |