JPS62123726A - Method for forming iii-v semiconductor high resistance layer - Google Patents

Abstract

PURPOSE:To provide a P-type GaAs layer with a high resistance feature by a method wherein the P-type GaAs layer is exposed to a short duration infrared annealing using an SiOxNy layer serving as a protecting film. CONSTITUTION:An SiOxNy film 3 is deposited by CVD on the entire surface of a P-type GaAs layer 2 installed on a semi-insulating GaAs substrate 1. After a process wherein the SiOxNy film 3 is removed from a square region with a photoresist 4 serving as a mask, the photoresist 4 is removed, and then a three-second infrared annealing is accomplished at 950 deg.C for the development of the remaining portion covered by the SiOxNy of the P-type GaAs layer 2 into a high resistance GaAs layer 5. After the annealing, the SiOxNy is removed, a 150nm-thick AuZn/Ni electrode 6 is built by evaporation and converted into an alloy at a temperature of 420 deg.C to serve as a P-type ohmic electrode in the square region. In this way, a P-type GaAs layer may be augmented in resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming a complete high resistance layer of an m-v group semiconductor.

[Conventional technology]

In recent years, with the aim of increasing the speed of semiconductor integrated circuits, GaA, which uses gallium arsenide (abbreviated as GaAs) semiconductor in the active layer, has been developed.
s Integrated circuits are being actively developed.

Field effect transistors are generally used as the basic elements of GaAs integrated circuits. As the active layer of a field effect transistor, a 7'Cn type layer formed by an epitaxial method or an ion implantation method is widely used.
In recent years, complementary circuits have been attracting attention in GaAs integrated circuits for the purpose of lowering power consumption (Sake et al., Proceedings of the 45th Annual Conference of the Japan Society of Applied Physics, p. 551). In complementary circuits, it is necessary to form a p-type operation layer on the same substrate with good controllability in addition to the conventional n-type operation layer. A well-known method for separating a p-type layer formed on the same substrate into several electrically insulated conductive regions is to use mesa etching as shown in the cross-sectional structure diagram in Figure 2. It is being In the mesa etching method, a portion of the p-type trench conductive layer is selectively removed using an etching solution or an etching gas to electrically insulate two conductive regions.

[Problem that the invention seeks to solve]

The mesa etching method described above as a method for insulation separation of a conductive layer has the advantage that it is easy to perform and insulation separation can be performed reliably. However, the separation groove formed by etching significantly deteriorates the flatness of the semiconductor substrate, and therefore has the drawback that it is easy to cause a complete disconnection of the electrode wiring. Therefore, it is not preferable to use the mesa etching separation method as a manufacturing process for large-scale integrated circuits from the viewpoint of circuit yield. An object of the present invention is to provide a method for insulating and separating a p-type trench conductor layer without impairing the flatness of a semiconductor substrate.

[Elaborate means to solve problems]

According to the present invention, after covering the surface of the p-type conductive III-V group semiconductor substrate with a silicon oxynitride film, short-time infrared annealing is performed.
A method for forming a group V semiconductor high resistance layer is obtained.

[Effect]

The present invention is based on the principle that the semiconductor has a high resistance by compensating for the shallow acceptor levels 1 to 1 in a p-type semiconductor with a deep electric potential.

-Be, Mg, Zn, etc. are known as acceptor impurities in -V group semiconductors, but all of these impurities form shallow acceptor levels and release free holes into the valence band, resulting in p-type Shows groove conductivity. Here, when a deep electron trap is introduced into this p-type conductive layer from the outside, the fC electrons captured in the electron trap fall to the shallow acceptor level, which prevents free holes from being released into the valence band. It will be done. Now, the shallow acceptor level concentration iN, the deep electron trap concentration t, and the free hole concentration p￥1p expressed in NDD.
=NA-NDD. Therefore, NDDwon
If a larger amount than A is introduced, it becomes pro and the resistance of the semiconductor increases.

As a deep electron trap in a GaAs semiconductor, EL2 has an activation energy of about 0.8 eV from the bottom of the conduction band.
Level is well known. Although there are still many unknowns about the identity of this EL2 level, its concentration often changes with heat treatment. Figure 3 After depositing various silicon oxynitride (S + 0xNy) protective films on the surface of a strong n-type GaAs substrate containing the FiEL2 level,
This figure shows the dependence of the EL2 concentration on the refractive index of the protective film when short-time infrared annealing is performed at 0° C. for 3 seconds. When annealing is performed using the entire 8r0xNy protective film with a refractive index of 1.7 to 1.8, the generation of trap gL2 is maximized. From this result, S s 0x for p-type GaAs
By performing short-time infrared annealing using a Ny protective film, it is possible to increase the resistance of the p-type GaAs layer.

〔Example〕

One embodiment of the present invention will be described below in Figures 1 (a) to (f).
) will be explained using the cross-sectional structure figure and sound. Surface orientation <100>L
E C (Liquid Encapsulated)
Czochralski method undoped semi-insulating GaA
MOCVD (Metalorganic
Chemical Vapor Depositio
n) Mg-added mold GaAs with a thickness of 1 μm using the method
p = I X10'7l-3) Layer 2 is epitaxially grown (FIG. 1(a)). Next, CV is applied to the entire surface of the GaAs substrate.
S i 0xNy with refractive index 1.75”i using D method
1100 nm of film 3 is deposited (FIG. 1(b)), and a large number of square openings of 200×200 μm2 are formed at intervals of 20 μm using photoresist 4 (FIG. 1(C)).
). 5IoxN in a square area using photoresist 4 as a mask
After removing the Y film 3, the photoresist 4 is completely removed as shown in Figure 1 (
d)) Short-time infrared annealing is performed at 950° C. and 300° C. to transform the p-type GaAs layer in the region not covered with the 5IOXNY film 3 into a high-resistance GaAs layer 5 (FIG. 1(e)).

After annealing, the gold of the S+0xNy film 3 is removed, and an AuZφi electrode 6 with a diameter of 150 mm is placed as a p-type ohmic electrode in the square area.
nm vacuum evaporated and alloyed at 420°C (Fig. 1 (
f)). The resistivity of the high-resistance GaAs layer 5 determined from the resistance measurement between the obtained square ohmic electrodes is 5 x 106 ~ l.
It was X107Ω·α. On the other hand, the resistivity of the p-type region that was not completely covered with the 8+0xNy film 3 did not change. In this manner, it has been demonstrated that the high resistance layer formed by the method of the present invention is effective as an element isolation method for GaAs devices having p-channels.

〔Effect of the invention〕

By using the method of the present invention, element isolation between GaAs devices having p-channels can be realized without impairing the surface flatness of the semiconductor substrate. Therefore, this method is promising as a manufacturing process for large-scale integrated circuits using GaAs devices.

[Brief explanation of drawings]

FIGS. 1(a) to (fl) are t-th cross-sectional views showing embodiments of the present invention in the order of steps; FIG. 2 is a diagram showing a conventional isolation method; FIG. 3 is a detailed explanation of the present invention. 1... Semi-insulating GaAs substrate 2... P-type GaAs
Layer 3...S i 0xNy film 4... Photoresist 5... High resistance GaAs layer 6... A
uZn high electrode Figure 1 N Electrode Figure 3 1.4 1.6 +, 8 2.0SiOxN,
Film refractive index

Claims (1)

[Claims] A method for forming a III-V group semiconductor high-resistance layer, which comprises covering the surface of a p-type conductive III-V group semiconductor substrate with a silicon oxynitride film and then performing short-time infrared annealing.