JPH0810705B2 - Integrated circuit device - Google Patents
Integrated circuit deviceInfo
- Publication number
- JPH0810705B2 JPH0810705B2 JP61276547A JP27654786A JPH0810705B2 JP H0810705 B2 JPH0810705 B2 JP H0810705B2 JP 61276547 A JP61276547 A JP 61276547A JP 27654786 A JP27654786 A JP 27654786A JP H0810705 B2 JPH0810705 B2 JP H0810705B2
- Authority
- JP
- Japan
- Prior art keywords
- semi
- ohmic
- active layer
- type active
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Element Separation (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半絶縁性III−Ｖ族化合物半導体基板を有
する集積回路装置に係り、特に半絶縁性GaAsを基板に用
いた大規模集積回路装置に関する。Description: TECHNICAL FIELD The present invention relates to an integrated circuit device having a semi-insulating III-V compound semiconductor substrate, and particularly to a large-scale integrated circuit using semi-insulating GaAs as a substrate. Regarding the device.
従来、半絶縁性GaAs基板２上に複数のオーミック電極
100,100´を形成する場合は、第２図に示すようにGaAs
基板を絶縁体として考え、前記オーミック電極間の電気
的分離方法としては単に半絶縁性GaAs基板上で所定の距
離をおく事によってのみなされているのが通例であっ
た。Conventionally, a plurality of ohmic electrodes are formed on the semi-insulating GaAs substrate 2.
When forming 100,100 ', as shown in Fig. 2, GaAs
It has been customary to consider the substrate as an insulator, and the electrical isolation method between the ohmic electrodes is generally regarded as merely setting a predetermined distance on the semi-insulating GaAs substrate.
上記従来技術は、半絶縁性GaAs基板上に形成したオー
ミック電極の電気的な分離については十分な配慮がなさ
れておらず、700℃〜1000℃の高温アニールによって半
絶縁性GaAs基板の極表面層（表面から厚さ10nm〜1000n
m）が変質するとオーミック電極間のリーク電流が増大
するという問題があった。The above-mentioned prior art does not give sufficient consideration to the electrical separation of the ohmic electrode formed on the semi-insulating GaAs substrate, and the high-temperature annealing at 700 ° C to 1000 ° C anneals the surface layer of the semi-insulating GaAs substrate. (Thickness from the surface 10 nm to 1000 n
When m) deteriorates, there is a problem that the leak current between the ohmic electrodes increases.
本発明の目的は、上記問題を解決し、信頼性の高い集
積回路装置を提供することにある。It is an object of the present invention to solve the above problems and provide a highly reliable integrated circuit device.
上記目的は、半絶縁性III−Ｖ族化合物半導体基板上
の問題となるオーミック電極を全てｎ型活性層上に形成
し、オーミック電極が直接半絶縁性III−Ｖ族化合物半
導体基板表面に接することがないようにすることにより
達成される。The above object is to form all the problematic ohmic electrodes on the semi-insulating III-V compound semiconductor substrate on the n-type active layer, and the ohmic electrodes are in direct contact with the surface of the semi-insulating III-V compound semiconductor substrate. It is achieved by eliminating.
半絶縁性III−Ｖ族化合物半導体基板が半絶縁性GaAs
基板の場合を例にとり本発明の作用を説明する。Semi-insulating III-V compound semiconductor substrate is semi-insulating GaAs
The operation of the present invention will be described taking the case of a substrate as an example.
半絶縁性GaAs基板は、SiO2などの表面保護膜を形成し
たのち700℃〜900℃の高温でアニールすると、その表面
層が極めて低濃度のｐ型半導体に変成すると考えられ
る。したがって、この上に直接オーミック電極を形成す
ると、このｐ型変成層を通してリーク電流が流れオーミ
ック電極間の電気的分離が悪くなる。When a semi-insulating GaAs substrate is annealed at a high temperature of 700 ° C. to 900 ° C. after forming a surface protective film such as SiO 2 , it is considered that the surface layer is transformed into a p-type semiconductor having an extremely low concentration. Therefore, if an ohmic electrode is formed directly on this, a leak current flows through this p-type metamorphic layer and the electrical isolation between the ohmic electrodes deteriorates.
一方、本発明のように、ｎ型活性層の上にオーミック
電極を形成すると、このｎ型活性層と前記ｐ型変成層の
境界にpn接合が形成され、２つのオーミック電極間には
npn接合が存在する。したがって、オーミック電極間に
電圧が印加されても、pn接合の逆バイアス効果により電
流は流れず、オーミック電極間の電気的分離は良好とな
る。On the other hand, when the ohmic electrode is formed on the n-type active layer as in the present invention, a pn junction is formed at the boundary between the n-type active layer and the p-type metamorphic layer, and between the two ohmic electrodes.
There is an npn junction. Therefore, even if a voltage is applied between the ohmic electrodes, no current flows due to the reverse bias effect of the pn junction, and the electrical isolation between the ohmic electrodes becomes good.
第１図（ａ）および第１図（ｃ）に本発明の一実施例
のオーミック電極の構造を示す。第１図（ａ）は半絶縁
性GaAs基板２の表面に低濃度ｎ型活性層３を形成し、そ
の上に前記低濃度ｎ型活性層３より面積が小さいAuGe/N
i/Auからなるオーミック電極101および101′を形成した
ものである。この場合、前記オーミック電極101および1
01′は半絶縁性GaAs基板とは直接接触していない。1 (a) and 1 (c) show the structure of an ohmic electrode according to an embodiment of the present invention. FIG. 1A shows a low-concentration n-type active layer 3 formed on the surface of a semi-insulating GaAs substrate 2, and an AuGe / N having a smaller area than the low-concentration n-type active layer 3 is formed thereon.
The ohmic electrodes 101 and 101 'made of i / Au are formed. In this case, the ohmic electrodes 101 and 1
01 'is not in direct contact with the semi-insulating GaAs substrate.
第１図（ｃ）は高濃度ｎ型活性層５の面積をオーミッ
ク電極103および103′より大きくとり、前記オーミック
電極が直接に半絶縁性GaAs基板２に接触しないようにし
たものである。In FIG. 1 (c), the area of the high-concentration n-type active layer 5 is larger than that of the ohmic electrodes 103 and 103 'so that the ohmic electrode does not come into direct contact with the semi-insulating GaAs substrate 2.
また、比較例を第１図（ｂ）に示す。第１図（ｂ）は
半絶縁性GaAs基板２の表面に高農度ｎ型活性層４を形成
し、その上に前記高濃度ｎ型活性層４より面積が広いAu
Ge/Ni/Auからなるオーミック電極102および102′を形成
したものである。この場合、前記オーミック電極102お
よび102′は半絶縁性GaAs基板２と高濃度ｎ型活性層４
の両方に直接に接触している。A comparative example is shown in FIG. FIG. 1B shows a high-intensity n-type active layer 4 formed on the surface of a semi-insulating GaAs substrate 2, and an Au having a larger area than the high-concentration n-type active layer 4 is formed thereon.
The ohmic electrodes 102 and 102 'made of Ge / Ni / Au are formed. In this case, the ohmic electrodes 102 and 102 'are the semi-insulating GaAs substrate 2 and the high concentration n-type active layer 4.
Are in direct contact with both.
第１図（ａ），第１図（ｂ）および第１図（ｃ）の素
子の形成方法を第３図（ａ）乃至第３図（ｄ）に示す。
まず、第３図（ａ）の如く、半絶縁性GaAs基板２の上
に、プラズマ気相化学成長法でSiO2膜７を堆積したのち
ホトレジスト８を塗布し、所定の部分に開口部を設け
る。次に、第３図（ｂ）に示すごとく、イオン打込み法
により、Siイオン９を打込む。次に、第３図（ｃ）に示
すごとく、ホトレジスト８を除去したのち、プラズマ気
相化学成長法によりSiO2膜を堆積した後、H2中でアニー
ルを行ないイオン打込み層3,4,5を活性化する。次に、
第３図（ｄ）に示すごとく、AuGe/Ni/Auからなるオーミ
ック電極を形成し、N2中でアロイを行なう。以上によっ
て第１図（ａ），第１図（ｂ）および第１図（ｃ）に示
す素子が形成される。FIGS. 3 (a) to 3 (d) show a method of forming the elements shown in FIGS. 1 (a), 1 (b) and 1 (c).
First, as shown in FIG. 3A, a SiO 2 film 7 is deposited on the semi-insulating GaAs substrate 2 by plasma vapor phase chemical growth method, and then a photoresist 8 is applied to form an opening at a predetermined portion. . Next, as shown in FIG. 3 (b), Si ions 9 are implanted by the ion implantation method. Next, as shown in FIG. 3 (c), after removing the photoresist 8, a SiO 2 film is deposited by the plasma chemical vapor deposition method and then annealed in H 2 to carry out ion implantation layers 3, 4, 5, 5. Activate. next,
As shown in FIG. 3D, an ohmic electrode made of AuGe / Ni / Au is formed and alloyed in N 2 . As described above, the elements shown in FIGS. 1A, 1B and 1C are formed.
第１図（ａ），第１図（ｂ），第１図（ｃ）および従
来例（第２図）の各素子についてのオーミック電極間の
電流−電圧特性を第４図に示す。第１図（ａ），第１図
（ｂ），第１図（ｃ）および従来例（第２図）の各オー
ミック電極間の電流−電圧特性はそれぞれ曲線10,11,1
2,13に対応している。曲線13に示すごとく、オーミック
電極が直接半絶縁性GaAs基板上に形成された従来例にお
いては、印加電圧約1V以上で急激に電流が流れ始め、オ
ーミック電極間の電気的分離が極めて良くないことがわ
かる。また、曲線10,12に示すごとく、オーミック電極
がｎ型活性層上に形成されている本発明の実施例の場合
は、電流が流れにくく、オーミック電極間の電気的分離
が良好である。また、ｎ型活性層の濃度が高くなるほど
電気的分離特性が良好になることもわかる。高濃度活性
層の上に形成されたオーミック電極間の電気的分離は電
圧80V以上まで良好である。また、第１図（ｂ）の比較
例では、オーミック電極が部分的に半絶縁性GaAs基板に
接触しているため、曲線11に示すごとく、従来例の場合
（曲線13）とほとんど変わらず、オーミック電極間の電
気的分離特性は悪い。FIG. 4 shows the current-voltage characteristics between the ohmic electrodes for the elements of FIGS. 1 (a), 1 (b), 1 (c) and the conventional example (FIG. 2). The current-voltage characteristics between the ohmic electrodes in FIGS. 1 (a), 1 (b), 1 (c) and the conventional example (FIG. 2) are shown by curves 10, 11, 1 respectively.
It corresponds to 2,13. As shown by the curve 13, in the conventional example in which the ohmic electrode was directly formed on the semi-insulating GaAs substrate, the current suddenly started to flow at an applied voltage of about 1 V or more, and the electrical isolation between the ohmic electrodes was extremely poor. I understand. Further, as shown by the curves 10 and 12, in the case of the embodiment of the present invention in which the ohmic electrode is formed on the n-type active layer, it is difficult for current to flow, and the electrical isolation between the ohmic electrodes is good. It can also be seen that the higher the concentration of the n-type active layer, the better the electrical isolation characteristics. The electrical isolation between the ohmic electrodes formed on the high concentration active layer is good up to a voltage of 80V or higher. Further, in the comparative example of FIG. 1 (b), since the ohmic electrode is partially in contact with the semi-insulating GaAs substrate, there is almost no difference from the case of the conventional example (curve 13) as shown by the curve 11. The electrical isolation characteristics between ohmic electrodes are poor.
以上の実験結果により、半絶縁性GaAs基板の上に複数
のオーミック電極を形成する場合は、各オーミック電極
を、それぞれ分離されたｎ型活性層の上に形成し、オー
ミック電極が直接半絶縁性GaAs基板に接触しないように
する必要があるといえる。From the above experimental results, when a plurality of ohmic electrodes are formed on a semi-insulating GaAs substrate, each ohmic electrode is formed on a separate n-type active layer, and the ohmic electrodes are directly semi-insulating. It can be said that it is necessary to avoid contact with the GaAs substrate.
本発明によれば、半絶縁性GaAs基板上に形成するオー
ミックで電極をｎ型活性層の上に配置することにより、
得に工程数を増やすことなくオーミック電極間の電気的
分離を行なうことができ、容易にGaAs高集積回路装置が
実現できる。According to the present invention, by arranging the electrode on the n-type active layer by ohmic formation on the semi-insulating GaAs substrate,
Electrical isolation between ohmic electrodes can be performed without increasing the number of steps, and a GaAs highly integrated circuit device can be easily realized.
第１図は本発明の一実施例および比較例のオーミック電
極周辺の断面図、第２図は従来のオーミック電極周辺の
断面図、第３図は第１図のオーミック電極の形成工程
図、第４図は第１図のオーミック電極の電流−電圧特性
を示す図である。 ２……半絶縁性GaAs基板、３……低濃度ｎ型活性層、4,
5……高濃度ｎ型活性層、10,12……本発明の一実施例の
オーミック電極間の電流−電圧特性曲線、11……比較例
のオーミック電極間の電流−電圧特性曲線、13……従来
例のオーミック電極間の電流−電圧特性曲線、100,10
0′,101,101′,102,102′,103,103′……オーミック電
極。FIG. 1 is a sectional view around an ohmic electrode according to one embodiment and a comparative example of the present invention, FIG. 2 is a sectional view around a conventional ohmic electrode, and FIG. 3 is a process drawing of the ohmic electrode in FIG. FIG. 4 is a diagram showing current-voltage characteristics of the ohmic electrode of FIG. 2 ... Semi-insulating GaAs substrate, 3 ... Low concentration n-type active layer, 4,
5: high-concentration n-type active layer, 10, 12 ... current-voltage characteristic curve between ohmic electrodes of one embodiment of the present invention, 11 ... current-voltage characteristic curve between ohmic electrodes of a comparative example, 13 ... ... Current-voltage characteristic curve between ohmic electrodes in the conventional example, 100, 10
0 ', 101,101', 102,102 ', 103,103' ... Ohmic electrode.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 29/812 Ｈ０１Ｌ 29/46 Ｂ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical indication H01L 29/812 H01L 29/46 B
Claims (2)
該半絶縁性III−Ｖ族化合物半導体基板上に形成された
複数個のオーミック電極を有する集積回路装置におい
て、上記複数個のオーミック電極の少なくとも２つは上
記半絶縁性III−Ｖ族化合物半導体基板上に形成された
ｎ型活性層の上に形成され、かつ、上記半絶縁性III−
Ｖ族化合物半導体基板および上記ｎ型活性層のうち上記
ｎ型活性層のみに接して形成されており、上記少なくと
も２つのオーミック電極はオーミック接触部と該オーミ
ック接触部と平面方向で接続しているオーミック接触部
以外の部分とで構成されており、上記オーミック接触部
は上記オーミック電極と上記ｎ型活性層との間に電流を
流すことを役目とし、上記オーミック接触部以外の部分
はそれ自体の中に電流を流すことを役目としていること
を特徴とする集積回路装置。1. A semi-insulating III-V compound semiconductor substrate,
In an integrated circuit device having a plurality of ohmic electrodes formed on the semi-insulating III-V compound semiconductor substrate, at least two of the plurality of ohmic electrodes are the semi-insulating III-V compound semiconductor substrate. The semi-insulating layer III- formed on the n-type active layer formed above and
It is formed in contact with only the n-type active layer of the V-group compound semiconductor substrate and the n-type active layer, and the at least two ohmic electrodes are connected to the ohmic contact portion in the plane direction. The ohmic contact portion serves to pass a current between the ohmic electrode and the n-type active layer, and the portion other than the ohmic contact portion is its own. An integrated circuit device characterized in that it has a role of flowing an electric current therein.
は半絶縁性GaAs基板である特許請求の範囲第１項記載の
集積回路装置。2. The integrated circuit device according to claim 1, wherein the semi-insulating III-V compound semiconductor substrate is a semi-insulating GaAs substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61276547A JPH0810705B2 (en) | 1986-11-21 | 1986-11-21 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61276547A JPH0810705B2 (en) | 1986-11-21 | 1986-11-21 | Integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63131578A JPS63131578A (en) | 1988-06-03 |
| JPH0810705B2 true JPH0810705B2 (en) | 1996-01-31 |
Family
ID=17571003
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61276547A Expired - Fee Related JPH0810705B2 (en) | 1986-11-21 | 1986-11-21 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0810705B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2776360B2 (en) * | 1996-02-28 | 1998-07-16 | 日本電気株式会社 | Method of manufacturing thin film transistor array substrate |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59147465A (en) * | 1983-02-10 | 1984-08-23 | Sony Corp | Manufacture of schottky-barrier-gate type field-effect transistor |
| JPS61222263A (en) * | 1985-03-28 | 1986-10-02 | Toshiba Corp | Manufacture of fifld effect transistor |
-
1986
- 1986-11-21 JP JP61276547A patent/JPH0810705B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63131578A (en) | 1988-06-03 |
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| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |