JPH0618280B2 - Schottky barrier semiconductor device - Google Patents

Description

The present invention relates to a Schottky barrier semiconductor device.

2. Description of the Related Art Schottky barrier diodes are widely used in high-frequency rectifier circuits and the like by taking advantage of good high-speed response (high-speed switching characteristics) and low power loss. However, in the Schottky barrier diode, a phenomenon in which the peripheral breakdown voltage (breakdown voltage in the peripheral portion of the Schottky barrier) is lower than the bulk breakdown voltage (breakdown voltage in the central portion of the Schottky barrier) is observed, and thus a high breakdown voltage is obtained. Is difficult.

A Schottky barrier diode provided with a guard ring region is known as a method for solving the above problem. According to the high breakdown voltage structure including the guard ring region, the pn junction formed by the guard ring region bears the peripheral breakdown voltage of the Schottky barrier based on the barrier electrode, and the peripheral breakdown voltage of the Schottky barrier can be improved. Therefore, it is possible to increase the breakdown voltage of the Schottky barrier diode in combination with the field plate structure. However, when a large current flows in the forward direction, the injection of minority carriers from the guard ring region to the semiconductor region increases. Therefore, when the forward operation is switched to the reverse operation, the switch is not completely switched off until this minority carrier is reduced. That is, a response delay occurs in the switching operation, and the fast response, which is an advantage of the Schottky barrier diode, is diminished.

A Schottky barrier diode shown in FIG. 7 is conceivable as a high breakdown voltage replacement structure including a guard ring region that solves the deterioration in high-speed response. In the illustrated Schottky barrier diode, the barrier electrode (24) is formed on the upper surface of the semiconductor substrate (21) including the n ^{+ type} region (21a) and the n type region (21b). An insulating layer (11) is formed on the outer periphery of the barrier electrode (24) and on the upper surface of the n-type region (21b) not covered by the barrier electrode (24). In addition, the barrier electrode (2
4) and electrodes (12) for external connection are formed on the upper surfaces of the insulating layer (11). A guard ring region (22) composed of a p ^{+ -type} region is formed at a portion below the boundary portion between the barrier electrode (24) and the insulating layer (11) in the n-type region (21b). Further, inside the guard ring region (22), an n ^{+ -type} region (23) is provided adjacent to the barrier electrode (24) and the lower surface of the insulating layer (11). An ohmic electrode (25) is formed on the lower surface of the n ^{+ type} region (21a).

According to this structure, since the passage cross-sectional area of the forward current flowing through the guard ring region (22) is narrowed, the injection amount of minority carriers can be reduced. Therefore, the high speed responsiveness is not significantly reduced. However, n ^{+ type} region (23)
As a result, the n ^{+ type} region (23) is an emitter, the guard ring region (22) is a base, and the n type region (21b) and the n ^{+ type} region (21a) are collectors in the Schottky barrier diode of FIG. Then an npn transistor structure is formed. That is, the Schottky barrier diode of FIG. 7 has the barrier electrode (24) and the semiconductor substrate (21).
And a pn junction diode based on the guard ring region (22) and the semiconductor substrate (21), and an npn transistor. Therefore, the illustrated Schottky barrier diode can be equivalently regarded as a Schottky barrier composite in which these diodes and transistors are electrically connected in parallel.

Therefore, when a reverse voltage is applied between the electrodes (24) and (25), the npn transistor described above operates and a relatively large leakage current is generated in the Schottky barrier composite, which may cause a decrease in breakdown voltage. is there. Further, before the Schottky barrier diode breaks down, the npn transistor structure often suffers punch-through breakdown, failing to obtain a high breakdown voltage. The punch-through breakdown is a breakdown that occurs when the depletion layer extending from the n-type region (21b) to the guard ring region (22) reaches the n ^{+ -type} region (23). Guard ring area (22) to prevent punch-through breakdown.
Must be deeply formed to increase the base width of the npn transistor structure. However, in this case, before the Schottky barrier diode breaks down,
There is a drawback that reach-through breakdown is likely to occur. In the reach through breakdown, the depletion layer extending from the guard ring region (22) to the n-type region (21b) is n.
^This is a breakdown that occurs when the ⁺ -shaped region (21a) is reached. To prevent reach-through breakdown, n
The thickness of the shaped region (21b) may be increased, but in this case, the forward voltage is increased and the power loss is increased.

Therefore, an object of the present invention is to provide a Schottky barrier semiconductor device that solves the above problems and can reliably achieve a high breakdown voltage without deteriorating high-speed response.

Means for Solving the Problems A Schottky barrier semiconductor device according to the present invention includes a barrier electrode formed on a semiconductor region of one conductivity type and generating a Schottky barrier between the semiconductor region and a barrier electrode adjacent to the barrier electrode and the semiconductor region. And a guard ring region formed of a semiconductor region having a conductivity type opposite to that of the semiconductor region formed so as to surround the Schottky barrier. The guard ring region includes a semi-insulating semiconductor region formed by partially implanting ions into the guard ring region. The semi-insulating semiconductor region reduces the forward current path cross-sectional area within the guard ring region.

In the present application, by selectively converting the inner region of the guard ring region into the semi-insulating semiconductor region, it is possible to achieve a high breakdown voltage of the Schottky barrier semiconductor device without deteriorating the high speed response. That is, in the present application, the PN junction formed between the guard ring region and the semiconductor region bears the peripheral breakdown voltage of the Schottky barrier, and the peripheral breakdown voltage of the Schottky barrier can be improved. At the same time, carrier injection between the semi-insulating semiconductor region and the semiconductor region does not substantially occur, so that high-speed operation is not limited by carrier accumulation.
In addition, the semi-insulating semiconductor region reduces the cross-sectional area of the forward current path in the guard ring region, resulting in excellent high-speed response. Further, according to the present application, since the parasitic transistor is not formed, there is an advantage that the withstand voltage is high and the leakage current is small.

Embodiments Embodiments of the present invention will be described below with reference to FIGS.

FIG. 1 shows a Schottky barrier diode as an embodiment according to the present invention. Further, FIG. 2 is a sectional view of the diode chip in each manufacturing process of this Schottky barrier diode. To form this Schottky barrier diode, first, the semiconductor substrate (1) shown in FIG. 2 (a) is prepared. The semiconductor substrate (1) has an n ^{+ type} region (1a) made of GaAs (gallium arsenide) and an n type region (1b) made of GaAs formed thereon by epitaxial growth. The n ^{+ -type} region (1a) has a thickness of about 300 μm and an impurity concentration of 2 × 10 ¹⁸ cm ⁻³ , and the n-type region (1b) has a thickness of about 15 μm and an impurity concentration of 2 × 10 ¹⁵ cm ⁻³ .

Next, as shown in FIG. 2B, a silicon oxide film (2) as a mask is formed on the upper surface of the semiconductor substrate (1) by plasma CVD (Chemical Vapor Deposition). An opening (3) is formed at a predetermined position of the silicon oxide film (2).
Are provided by photoetching. Then the opening (3)
Through, Zn (zinc) is diffused in the n-type region (1b) to form ap ^{+ -type} region. This p ^{+ type} region acts as a guard ring region (4) and contributes to the improvement of the peripheral breakdown voltage of the Schottky barrier diode. The guard ring region (4) has a depth of about 3 μm and a surface concentration of about 5 × 10.
^{It is 18} cm ^-3 . Since the guard ring region (4) is formed by diffusion, it is formed so as to be wider in the lateral direction than the opening (3).

Then, as shown in FIG. 2 (c), ionized He
Are accelerated to lead to the upper surface of the semiconductor substrate (1) and injected into the guard ring region (4) through the opening (3) in the silicon oxide film (2). Thus, by implanting He (helium) ions into the guard ring region (4), a part of the guard ring region (4) can be converted into the semi-insulating semiconductor region (5). That is, in the guard ring region (4) where He ions are implanted, the semiconductor region close to an insulator having a resistivity of about 10 ⁷ to 10 ⁹ Ω · cm, that is, a semi-insulating semiconductor, because the GaAs crystal is disturbed. It becomes the area (5). Note that the notation of “semi-insulating semiconductor region” contradicts the terms “semi-insulating” and “semiconductor”, but as used in this specification as a general term, “consisting of semiconductor materials and A high resistance region having a semi-insulating property ".

In this example, the silicon oxide film (2) was used as a mask for ion implantation. He ions are not implanted into the portion of the semiconductor substrate (1) covered with the silicon oxide film (2). The mask for forming the guard ring region (4) and the mask for forming the semi-insulating semiconductor region (5) may be different masks, but in the point that high positional accuracy is obtained, as in this embodiment, It is desirable to use the same mask. Since He ions are implanted in a direction substantially perpendicular to the surface of the semiconductor substrate (1), the semi-insulating semiconductor region (5) is formed in the same region as the opening (3) in plan view. . Therefore, the semi-insulating semiconductor region (5) is formed in a substantially concentric shape with the guard ring region (4) inside the guard ring region (4) in plan view. Further, as is clear from FIG. 2 (c), the semi-insulating semiconductor region (5)
Is embedded in the semiconductor substrate (1) so that the upper surface is exposed to the upper surface of the semiconductor substrate (1) and the area other than the upper surface is surrounded by the guard ring region (4). The depth of the semi-insulating semiconductor region (5) is about 2 μm.

Next, as shown in FIG. 2D, the silicon oxide film (2) is removed by etching, and a Ti (titanium) layer (6) and Al (aluminum) are formed on the upper surface of the semiconductor substrate (1).
Layers (7) are successively formed by vacuum evaporation. Ti layer (6)
The layer thickness is 50 Å (0.005 μm), which is extremely thin. Al
The layer thickness of the layer (7) is about 2 μm. On the bottom surface of the semiconductor substrate (1), an Au (gold) -Ge (germanium) alloy and Au are continuously vacuum-deposited to form an ohmic electrode (8).

Subsequently, as shown in FIG. 2 (e), a part of the Al layer (7) is removed by photoetching, and the Al layer (7) is made to correspond to the region where the Schottky barrier to be the main forward current path is to be formed. 7a) remains. The outer peripheral portion of the Ti layer (6) is also removed by photoetching, so that the Ti layer (6a) located under the Al layer (7a) and the Ti layer (6b) adjacent to and surrounding the Ti layer (6a). ) And remain.
Since the Al layer (7a) and the Ti layer (6a) are both metal layers that generate a Schottky barrier with the GaAs semiconductor,
A barrier electrode (9) is formed by combining the Al layer (7a) and the Ti layer (6a) therebelow.

Next, heat treatment is performed in air at 275 ° C. for 15 minutes. As a result, the Ti layer (6b) not covered with the Al layer (7a) as shown in FIG. 2 (f) is oxidized to become the titanium oxide layer (10). The Ti layer (6a) coated on the Al layer (7a) is not oxidized. Titanium oxide layer (10) is T
The i-thick layer (6b) has a slightly larger layer thickness and is a semi-insulating high resistance layer having a sheet resistance of about 100 MΩ / □.

Note that the titanium oxide layer (10) also forms a Schottky barrier with the semiconductor substrate (1) similarly to the barrier electrode (9). However, the sheet resistance of the barrier electrode (9) is 1Ω /
□ or less, and the titanium oxide layer (10) has an incomparably higher sheet resistance than the barrier electrode (9). Therefore, the forward current mainly flows through the Ti layer (6a) and the Al layer (7a), and hardly flows through the titanium oxide layer (10). Therefore, in this specification, the Ti oxide layer (10) is excluded and the Ti layer (6a) and the Al layer (7a) are excluded.
The electrode made of is a barrier electrode (9).

The guard ring region (4) is adjacent to the lower surfaces of both the barrier electrode (9) and the titanium oxide layer (10) as shown in FIG. It is formed over the lower part of the layer (10). Further, the guard ring region (4) is formed in an annular shape along the peripheral portion of the barrier electrode (9) as shown in FIG. As a result, the guard ring region (4) and the n-type semiconductor region (1
The pn junction based on b) and the Schottky barrier based on the barrier electrode (9) are continuous.

As shown in FIG. 2 (f), the semi-insulating semiconductor region (5) is formed in the guard ring region (4) so as to be adjacent to the lower surfaces of both the barrier electrode (9) and the titanium oxide layer (10). It is located almost in the center. Further, as shown in FIG. 3, the semi-insulating semiconductor region (5) is formed in a ring shape along the peripheral portion of the barrier electrode (9).

Subsequently, as shown in FIG. 1, an insulating layer (11) made of a silicon oxide film is formed on the upper surfaces of the barrier electrode (9) and the titanium oxide layer (10) by a plasma CVD method. Then, Ti and Au are continuously vacuum-deposited on the upper surface of the barrier electrode (9) to form an electrode (12) for connecting an external terminal. The above completes the Schottky barrier diode chip for electric power.

When a reverse voltage having a negative potential on the barrier electrode (9) side and a positive potential on the ohmic electrode (8) side is applied to the Schottky barrier diode of the present embodiment, the barrier electrode (9)
Schottky barrier and titanium oxide thin layer (1
A depletion layer extends from each of the Schottky barriers based on 0). In addition, the guard ring region (4) and the n-type region (1
The depletion layer also extends from the pn junction based on b). The above three depletion layers are continuously integrated to obtain a good depletion layer for relaxing electric field concentration. At this time, since the pn junction formed at the interface between the guard ring region (4) and the n-type region (1b) bears the peripheral breakdown voltage of the Schottky barrier based on the barrier electrode (9) as in the conventional example, the Schottky barrier The peripheral breakdown voltage can be improved. Further, since the semi-insulating semiconductor region (5) formed in the guard ring region (4) is a region which can be almost regarded as an insulator, carrier injection from the semi-insulating semiconductor region (5) and the semi-insulating semiconductor region are performed. Substantially no carrier injection into (5) occurs. Therefore, the conventional transistor structure is not formed around the Schottky barrier diode composed of the semiconductor substrate (1) and the barrier electrode (9). Therefore, the Schottky barrier diode of this embodiment has a high breakdown voltage and a small leakage current.

Next, consider the case where a forward voltage is applied to the Schottky barrier diode of this embodiment. In the Schottky barrier diode of this example, since the semi-insulating semiconductor region (5) is formed in the guard ring region (4), the cross-sectional area of the forward current of the guard ring region (4) is narrowed. There is. Therefore, the injection amount of minority carriers from the guard ring region (4) to the n-type region (1b) can be reduced, and high-speed response can be achieved at a high level.

Even if an insulating material such as a silicon oxide film is formed instead of the semi-insulating semiconductor region (5), the guard ring region (4) is formed.
The cross-sectional area of the forward current can be narrowed, and the effect of reducing the injection of minority carriers can be obtained. However, if a region made of a material different from that of the guard ring region (4) is formed, mechanical strain occurs in the guard ring region (4) near the region, which is not preferable. The semi-insulating semiconductor region (5) can also be formed by irradiating the guard ring region (4) with an electron beam. However, in order to satisfactorily and easily form the high-resistance semi-insulating semiconductor region (5), ion implantation is preferable.

Modifications The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the spirit thereof. For example, as shown in FIG. 4 as the second embodiment, the semi-insulating semiconductor region (5) may be completely buried in the guard ring region (4) without being exposed from the semiconductor substrate (1). When forming the semi-insulating semiconductor region (5), it is possible to perform multiple ion implantations by changing the accelerating voltage. If the voltage of the ion implantation at this time is adjusted, the semi-insulating semiconductor region ( 5)
Can be appropriately formed to a desired depth as shown in FIGS.

Further, as in the third embodiment of the present invention shown in FIG. 5, a cross section including the semi-insulating semiconductor region (5) and the guard ring region (4) is formed by reactive ion etching (RIE) in FIG. The Schottky barrier diode may be cut to form a mesa-shaped Schottky barrier diode.

Further, after removing the silicon oxide film (2) on the outer peripheral side from the opening (3) after the step of FIG. 2 (b), the step shown in FIG. A semi-insulating semiconductor region (5) may be formed outside the guard ring region (4) as in the fourth embodiment of the invention. Also in this case, the end of the semi-insulating semiconductor region (5) on the Schottky barrier side is located inside the vicinity of the edge of the barrier electrode (9) in a plan view, and the semi-insulating semiconductor region (5) is also located. The guard ring region (4) is provided on the Schottky barrier side end of (1). As in the embodiment and this embodiment, the Schottky barrier side (element center side) is left from the opening (3) of the silicon oxide film (2) which is the selective diffusion mask for forming the guard ring region (4). That is, it is preferable to perform the ion implantation by the so-called self-alignment method, because the remaining width of the guard ring region (4) can be formed extremely small and accurately. In other embodiments, the remaining width of the guard ring region (4) located on the Schottky barrier side of the semi-insulating semiconductor region (5) can be accurately determined by this method.

The titanium oxide layer (10) is preferable in terms of excellent adhesion to the semiconductor region, surface stabilization effect, and influence on the semiconductor surface due to the field plate structure. But,
The substance is not limited to this as long as it is a substance that forms a Schottky barrier with the n-type region (1b). For example Ti layer (6)
And titanium oxide layer (10) instead of Ta, respectively.
A (tantalum) thin layer and a tantalum oxide layer may be provided. Further, the thickness of the titanium oxide layer (10) is selected to be 10 to 1000Å, preferably 20 to 300Å, in order to minimize stress generation. Further, the titanium oxide layer (10) is a Schottky barrier type field plate and contributes significantly to the high breakdown voltage, but without forming this, the high breakdown voltage effect as the guard ring is exhibited. .

The present invention also relates to GaAs, AlGaAs (aluminum arsenide.
It is suitable for a semiconductor device using a III-V group compound semiconductor such as gallium), GaP (gallium phosphide), InP (indium phosphide), but a semiconductor device using another compound semiconductor or Si (silicon). It is also effective.

EFFECTS OF THE INVENTION As described above, according to the present invention, it is possible to provide a Schottky barrier semiconductor device having excellent high-speed response and high withstand voltage.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of a Schottky barrier diode showing an embodiment of the present invention, FIG. 2 is a manufacturing process drawing of this Schottky barrier diode, and FIG. 3 is a plan view of the Schottky barrier diode of the embodiment. FIG. 4 is a sectional view showing a second embodiment of the present invention, FIG. 5 is a sectional view showing a third embodiment of the present invention, and FIG. 6 is a sectional view showing a fourth embodiment of the present invention. FIG. 7 shows a sectional view of a conventional Schottky barrier diode. (1b) ... n-type region (semiconductor region), (4) ... guard ring region, (5) ... semi-insulating semiconductor region, (9)
...... Barrier electrode,

Claims (1)

[Claims] 1. A barrier electrode formed on a semiconductor region of one conductivity type and generating a Schottky barrier with the semiconductor region; and a barrier electrode adjacent to the barrier electrode and the semiconductor region and surrounding the Schottky barrier. A Schottky barrier semiconductor device having a guard ring region formed of a semiconductor region having a conductivity type opposite to that of the semiconductor region formed as described above, wherein the guard ring region is formed by partially ion-implanting the guard ring region. Schottky barrier semiconductor device, comprising: a semi-insulating semiconductor region which is formed, and wherein the semi-insulating semiconductor region reduces a forward current passage cross-sectional area in the guard ring region.