JP3344542B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a high withstand voltage, and more particularly to a semiconductor device using an SOI (silicon on insulator) substrate.

[0002]

2. Description of the Related Art Recently, IGBTs have been used as power control elements.
(Insulated Gate Bipolar Transistor) is attracting attention. This IGBT is a bipolar transistor using an insulated gate, has a high output, and has the convenience of voltage driving.

FIG. 8 is a sectional view schematically showing the structure of this type of IGBT. In this IGBT, a buried oxide film 2 and an n-type base layer 3 are sequentially formed on a silicon substrate 1. An n-type buffer layer 4 is selectively formed on the surface of the n-type base layer 3 so as not to reach the buried oxide film 2.
On the surface of the type buffer layer 4, a p-type drain layer 5 as a p-type emitter layer is selectively formed. A drain electrode 6 is formed on the p-type drain layer 5.

Similarly, in n-type base layer 3, p-type base layer 7 is selectively formed so as not to reach buried oxide film 2 from its surface. An n-type source layer 8 is selectively formed on the surface of the p-type base layer 7.

On a part of the p-type base layer 3 and a part of the n-type source layer 8, a common source electrode 9 is selectively formed. An insulating film 10 is formed on each layer between the source electrode 9 and the drain electrode 6. Insulating film 1
The gate electrode 11 is formed on a region of 0 that is in contact with the p-type base layer 7. Further, a low resistance p + for obtaining a good contact is provided at the lower center of the source electrode 9.
A mold contact layer 12 is formed.

When a positive voltage is applied to the gate electrode 11, electrons appear on the surface of the p-type base layer 7 immediately below the gate in proportion to the positive voltage, and the surface of the p-type base layer 7 is inverted to an electron region. I do. This inversion region becomes a channel, and short-circuits the n-type source layer 8 and the n-type base layer 3.

Here, when a positive voltage is applied to the drain electrode 6 and a negative voltage is applied to the source electrode 9, electrons are supplied from the source electrode 9, and from the n-type source layer 8 through the channel to the n-type. It is injected into the base layer 3. As a result, holes are injected from the p-type drain layer 5 into the n-type base layer 3 via the n-type buffer layer 4. Due to the injection of holes, in the n-type base layer 3, conduction modulation in which electrons and holes coexist at a high density and at substantially the same density so as to cancel each other's charges occurs, the on-resistance is reduced, and the conduction state is established. Become. Therefore, electrons of the n-type base layer 3 flow to the drain electrode 6 via the p-type drain layer 5, and holes of the n-type base layer 3
Flows to the source electrode 9 via.

[0008]

However, in the IGBT as described above, the injection of holes serving as minority carriers into the n-type base layer 3 causes conduction modulation to lower the on-resistance, so that the gate is turned off. Even if the injection of electrons is stopped, a current flows through the element while the accumulated holes are discharged, so that there is a problem that the switching speed is lower than that of the MOSFET.

From the viewpoint of improving the switching characteristics, it is necessary to lower the impurity concentration of the p-type drain layer 5 to lower the injection efficiency, and to reduce the impurity concentration of the p-type drain layer 5 with a sharp distribution in the depth direction. It is necessary to create

For example, as shown in FIG. 9 showing the impurity concentration distribution in the AA 'cross section of FIG. 8, when the impurity distribution of the p-type drain layer 5 is gentle, the n-type buffer layer 4 having a predetermined impurity concentration is formed. Need to be thicker to get
This is because if the n-type buffer layer 4 is made thicker, the thickness of the n-type base layer 3 becomes relatively thinner, which causes a problem that the breakdown voltage and current density of the element are reduced.

However, when the p-type drain layer 5 is formed, the surface concentration of the p-type drain layer 5 must be considerably higher than the impurity concentration of the n-type buffer layer 4 by the method of implanting and diffusing impurities by ion implantation. Yes, thin p
It is difficult to form the mold drain layer 5. The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device that can realize excellent switching characteristics without lowering a withstand voltage or the like.

[0012]

According to a first aspect of the present invention, there is provided a semiconductor substrate, an insulating layer formed on the semiconductor substrate, a first conductivity type base layer formed on the insulating layer, A second conductivity type drain layer made of polycrystal selectively formed on the first conductivity type base layer; a drain electrode provided on the second conductivity type drain layer; And the second conductive type base layer selectively formed on the second conductive type base layer and the second conductive type base layer so as not to contact the first conductive type base layer.
A first conductivity type source layer selectively formed on the conductivity type base layer; a source electrode provided on the first conductivity type source layer and the second conductivity type base layer; and the first conductivity type source layer And a gate electrode formed on the second conductive type base layer sandwiched between the first conductive type base layer and a gate insulating film via a gate insulating film.

According to a second aspect of the present invention, there is provided a semiconductor substrate, an insulating layer formed on the semiconductor substrate, a first conductivity type base layer formed on the insulating layer,
A second conductivity type drain layer selectively formed by epitaxial growth on the conductivity type base layer; a drain electrode provided on the second conductivity type drain layer; and a second conductivity type drain layer selectively formed on the first conductivity type base layer. The formed second conductive type base layer and the second conductive type base layer are arranged so as not to be in contact with the first conductive type base layer.
A first conductivity type source layer selectively formed on the conductivity type base layer; a source electrode provided on the first conductivity type source layer and the second conductivity type base layer; and the first conductivity type source layer And a gate electrode formed on the second conductive type base layer sandwiched between the first conductive type base layer and a gate insulating film via a gate insulating film. (Operation) Therefore, in the invention corresponding to claim 1, by taking the above means, the second conductivity type drain layer is formed on the first conductivity type base layer, so that the second conductivity type drain layer is formed. Is formed, and the thickness of the first conductivity type base layer can be relatively thickened, so that the withstand voltage and the like are not reduced, and the impurity concentration of the second conductivity type drain layer is reduced to reduce holes. By controlling the injection efficiency, excellent switching characteristics can be realized.

According to a second aspect of the present invention, the second conductivity type drain layer is formed by epitaxial growth. In addition to the action corresponding to the first aspect, the impurity concentration can be controlled with high precision. It can be expected that the switching characteristics will be realized.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a sectional view schematically showing a configuration of an IGBT according to a first embodiment of the present invention. This IGBT uses an SOI substrate, and a buried oxide film 22 and a silicon n-type base layer 23 are sequentially formed on a silicon substrate 21.

An n-type buffer layer 24 is formed on the surface of the n-type base layer 23, and a p-type drain layer 25 as a p-type emitter layer is formed on the n-type buffer layer 24. On the p-type drain layer 25, a drain electrode 26 is formed.

On the surface of the n-type base layer 23, a p-type base layer 27 is selectively formed, and on the surface of the p-type base layer 27, an n-type source layer 28 is selectively formed. Further, a common source electrode 29 is selectively formed on a part of the p-type base layer 27 and on the n-type source layer 28.

An insulating film 30 is formed on each layer between the source electrode 29 and the drain electrode 26. Insulating film 3
A gate electrode 31 is formed on a region of 0 that is in contact with the p-type base layer 27. Further, the source electrode 29
A low-resistance p @ + -type contact layer 32 for obtaining a good contact is formed in the lower central portion.

Here, in the p-type drain layer 25, after the n-buffer layer 24 is formed by ion implantation and diffusion of phosphorus in the LOCOS opening corresponding to the position of the drain electrode 26, a gate insulating film is formed by gate oxidation. When the n-type buffer layer 24 is exposed by removing a part thereof,
Polycrystalline silicon is deposited on the n-type buffer layer 24 by a CVD method or the like, and boron is ion-implanted and annealed to the polycrystalline silicon. The gate electrode 31 can also be formed with the deposition of the polycrystalline silicon. Alternatively, they can be deposited separately.

Next, the operation of the IGBT configured as described above will be described. In the IGBT according to the present embodiment, since p-type drain layer 25 is formed by depositing polycrystalline silicon, p-type drain layer 25 is formed as shown in FIG. The interface of the drain layer 25 can be made steep. Thereby, the n-type buffer layer 24 can be formed shallowly, that is, the n-type base layer 23 can be formed relatively thick, so that the withstand voltage of the element can be improved and the current density can be improved.

Further, as the p-type drain layer 25, by controlling the amount of boron ions implanted after polycrystalline silicon is deposited, the impurity concentration is reduced, and the efficiency of carrier (hole) injection during operation is improved. Can be lowered. That is, the switching speed is improved by reducing the amount of holes injected during operation to reduce the amount of holes accumulated in the n-type base layer 23 and shortening the time for discharging holes when the switch is turned off. Can be.

For example, the dose amount of the n-type buffer layer 24 is 1
× 10 ¹⁴ cm ^-2 , dose of p-type drain layer 25 1 × 1
FIG. 3 shows a current-voltage characteristic of the IGBT according to the present embodiment when it is set to 0 ¹⁴ cm ⁻² , and FIG. 4 shows a turn-off characteristic. As shown, good results were obtained with a turn-off time t _{off of} about 300 ns. In this case,
The ratio of the hole current to the total current is suppressed to about 30%.

As described above, according to the first embodiment, the p-type drain layer 25 is formed on the n-type buffer layer 24. Can be realized at the same time, so that excellent switching characteristics can be realized without lowering the withstand voltage and the like. (Second Embodiment) Next, an IGBT according to a second embodiment of the present invention will be described.

FIG. 5 is a cross-sectional view schematically showing the structure of the IGBT. The same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof will be omitted. Only different parts will be described here. .

That is, the IGBT according to the present embodiment
Is a modification of the first embodiment. Specifically, FIG.
As shown in FIG. 7, a single crystal p-type drain layer 25a formed by selective epitaxial growth is provided instead of the p-type drain layer 25 formed by depositing polycrystalline silicon.

Here, the p-type drain layer 25a has substantially the same impurity concentration distribution in the depth direction as that of FIG.
It can be formed by an OCVD (metal organic chemical vapor deposition) method or an MBE (molecular beam epitaxy) method. Thereby, the IGBT according to the present embodiment also has the same impurity concentration distribution in the depth direction as FIG.

With the structure described above, the IGBT according to the present embodiment can obtain the same effects as those of the first embodiment, and furthermore, the IGBT can be formed by epitaxial growth.
Since the impurity concentration of the mold drain layer 25a can be controlled with high precision, the carrier injection efficiency can be further precisely controlled. (Third Embodiment) Next, an IGBT according to a third embodiment of the present invention will be described.

FIG. 6 is a cross-sectional view schematically showing the configuration of the IGBT. The same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof will be omitted. Only different parts will be described here. .

That is, the IGBT according to the present embodiment
Is a modified configuration of the first embodiment. Specifically, FIG.
As shown in FIG.
The region of the + -type contact layer 32 is extended to the region where the n-type source layer 28 was located, and a part of the p-type base layer 27 and p +
An n + -type emitter layer 33 formed by depositing polycrystalline silicon on a part of the
9 is provided.

With the above structure, the IGBT according to the present embodiment can obtain the same effects as those of the first embodiment, and can further improve the latch-up resistance. (Fourth Embodiment) Next, an IGBT according to a fourth embodiment of the present invention will be described.

FIG. 7 is a cross-sectional view schematically showing the structure of the IGBT. The same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof will be omitted. Only different parts will be described here. .

That is, the IGBT according to the present embodiment
Is a modification of the first embodiment. Specifically, FIG.
As shown in the figure, while n-type buffer layer 24 is omitted,
On the n-type base layer 23, between the n-type base layer 23 and the p-type drain layer 25, there is provided an n-type buffer layer 34 formed by depositing polycrystalline silicon.

With the above-described structure, the IGBT according to the present embodiment can obtain the same effect as that of the first embodiment, and further, does not need to reduce the thickness of the n-type base layer 23. Therefore, the breakdown voltage can be improved.

The IGBT has an n-type buffer layer 3
Since polycrystalline silicon 4 is used, the switching speed can be further increased due to a decrease in carrier lifetime. (Other Embodiments) In each of the above embodiments, the case where the first conductivity type is n-type and the second conductivity type is p-type has been described. However, the present invention is not limited to this. However, the present invention can be implemented in the same manner to obtain the same effect.
In addition, the present invention can be implemented with various modifications without departing from the scope of the invention.

[0035]

As described above, according to the first aspect of the present invention, a steep interface of the p-type drain layer is formed, and the thickness of the n-type base layer can be relatively increased. By controlling the hole injection efficiency by lowering the impurity concentration of the p-type drain layer without performing the above, a semiconductor device that can realize excellent switching characteristics can be provided.

According to the second aspect of the present invention, since the drain layer of the second conductivity type is formed by epitaxial growth, in addition to the effect of the first aspect, the impurity concentration can be controlled with high precision, so that more excellent switching can be achieved. A semiconductor device that can be expected to achieve characteristics can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view schematically showing a configuration of an IGBT according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an impurity concentration distribution along a depth direction immediately below a p-type drain layer of the IGBT according to the embodiment.

FIG. 3 is a diagram showing current-voltage characteristics in the embodiment.

FIG. 4 is a diagram showing turn-off characteristics in the embodiment.

FIG. 5 is a sectional view schematically showing a configuration of an IGBT according to a second embodiment of the present invention.

FIG. 6 is a sectional view schematically showing a configuration of an IGBT according to a third embodiment of the present invention.

FIG. 7 is a sectional view schematically showing a configuration of an IGBT according to a fourth embodiment of the present invention.

FIG. 8 is a cross-sectional view schematically showing a configuration of a conventional IGBT.

FIG. 9 is a diagram showing an impurity concentration distribution along a depth direction immediately below a p-type drain layer of a conventional IGBT.

[Explanation of symbols]

 Reference Signs List 21 silicon substrate 22 buried oxide film 23 n-type base layer 24 n-type buffer layer 25, 25a p-type drain layer 26 drain electrode 27 p-type base layer 28 n-type source layer 29 source electrode 30 ... insulating film 31 ... gate electrode 32 ... p + -type contact layer 33 ... n + -type emitter layer 34 ... n-type buffer layer

──────────────────────────────────────────────────続 き Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 29/786 H01L 21/336

Claims (2)

(57) [Claims] A semiconductor substrate; an insulating layer formed on the semiconductor substrate; a first conductive type base layer formed on the insulating layer; and selectively formed on the first conductive type base layer. A second conductivity type drain layer made of polycrystal, a drain electrode provided on the second conductivity type drain layer, and a second conductivity type base layer selectively formed on the first conductivity type base layer A first conductivity type source layer selectively formed on the second conductivity type base layer so as not to contact the first conductivity type base layer; and the first conductivity type source layer and the second conductivity type base. And a gate electrode formed on the second conductivity type base layer sandwiched between the first conductivity type source layer and the first conductivity type base layer via a gate insulating film A semiconductor device comprising: 2. A semiconductor substrate, an insulating layer formed on the semiconductor substrate, a first conductive type base layer formed on the insulating layer, and a first conductive type base layer formed on the first conductive type base layer by epitaxial growth. A second conductivity type drain layer formed selectively, a drain electrode provided on the second conductivity type drain layer, and a second conductivity type base layer selectively formed on the first conductivity type base layer. A first conductivity type source layer selectively formed on the second conductivity type base layer so as not to contact the first conductivity type base layer; and the first conductivity type source layer and the second conductivity type base layer. A gate electrode formed on the second conductive type base layer interposed between the first conductive type source layer and the first conductive type base layer via a gate insulating film; A semiconductor device comprising: