JPH10117000A - Schottky barrier semiconductor device and fabrication thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure a high breakdown strength low voltage operation by forming a buried layer in a working region from the boundary of a heavily doped semiconductor substrate and a lightly doped semiconductor substrate to the surface side of a semiconductor layer thereby forming the semiconductor layer thin at a working layer and thick at a guard ring part. SOLUTION: An n<-> type semiconductor layer 2 having impurity concentration on the order of 1×10<15> and serving as a working layer is formed on an n<+> type silicon semiconductor substrate 1 having impurity concentration on the order of 1×10<19> and an n<+> type buried layer 6 having impurity concentration on the order of 1×10<20> is formed at the joint of the semiconductor substrate 1 and the semiconductor layer 2 up to the vicinity of the surface thereof. Since a metal layer 3 forming a Schottky barrier is provided on a p<+> type region serving as a guard ring 4 on the surface of the semiconductor layer 2 at the outer circumferential part of the buried layer 6, high breakdown strength and low operating voltage are realized and reliability is enhanced significantly without requiring an etching on the surface of the semiconductor layer 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a Schottky barrier semiconductor device in which a metal layer for forming a Schottky barrier is provided on a semiconductor layer serving as an operation layer on a semiconductor substrate, and a method of manufacturing the same. More specifically, the present invention relates to a Schottky barrier semiconductor device in which a forward voltage drop is reduced while maintaining a high withstand voltage of a reverse characteristic, and a method of manufacturing the same.

[0002]

2. Description of the Related Art A Schottky barrier diode (hereinafter, referred to as a Schottky barrier diode)
SBDs) are widely used in high frequency rectifier circuits because of their high switching characteristics and low forward loss. A conventional SBD has a structure as shown in FIG. 6, for example.

That is, in FIG. 6, reference numeral 1 denotes an n ⁺ type semiconductor substrate made of, for example, silicon or the like, and 2 denotes an n ⁻ type epitaxially grown on the semiconductor substrate 1, for example, n ^−.
A semiconductor layer 3 serving as a mold operation layer, a metal layer 3 made of molybdenum (Mo) or the like, and forming a Schottky barrier;
Is a guard ring formed by diffusing a p-type dopant on the surface side of the semiconductor layer 2 near the outer periphery of the metal layer 3. 5
Is an insulating film formed on the surface of the semiconductor layer 2 by a thermal oxidation method or a CVD method, for example, made of SiO ₂ or the like.

The guard ring 4 has a phenomenon that the withstand voltage, which is the reverse characteristic at the periphery of the metal layer 3 forming the Schottky barrier, becomes smaller than that at the center, and in order to improve the withstand voltage at the periphery. Is formed. That is, by providing the guard ring 4, the withstand voltage in the periphery of the Schottky barrier is governed by the pn junction of the guard ring 4, and the distance d between the guard ring 4 and the n ⁺ type semiconductor substrate 1 is increased. _The breakdown voltage can be increased by increasing ₁ .

However, in order to increase the breakdown voltage, if the thickness of the n ⁻ type semiconductor layer 2 is increased to increase d ₁ , SB
The thickness d ₂ of the semiconductor layer 2 in the D operation region also increases, and the operation resistance increases. As a result, the drop of the forward voltage becomes large, and the characteristics of the SBD are reduced.

To solve this problem, the surface of the semiconductor layer 2 on which the metal layer 3 is provided is etched as shown in the cross-sectional view of FIG. Is formed, and the metal layer 3 is provided in the concave portion, so that the bonding surface between the n-type semiconductor layer 2 and the metal layer 3 is lower than the surface of the guard ring 4 and SB
The thickness d ₂ of the operation region of D is reduced. In FIG. 7, reference numeral 1 denotes an n ⁺ -type semiconductor substrate, 4 denotes a guard ring as a p-type region, and 5 denotes an insulating film.

[0007]

A contact surface of a metal layer forming a Schottky barrier is formed around the SBD provided with a conventional guard ring in order to increase the breakdown voltage and reduce the forward voltage drop. The method of lowering the height of the guard ring from the surface has the following problem as disclosed in Japanese Patent Application Laid-Open No. H4-65876. That is, since the n-type layer and the p-type layer have different etching rates, a step is likely to occur at the boundary with the guard ring. In addition, in a window opening portion for etching, since over-etching is performed below the insulating film, a step is easily generated between the insulating film and the semiconductor layer. As a result, there is a problem that the step coverage of the metal layer or the electrode film formed on the surface is poor and the step is broken to lower the withstand voltage or to short-circuit with the upper electrode metal.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and has a large reverse breakdown voltage withstand voltage without forming a concave portion by etching on the surface of a semiconductor layer on which a metal layer is provided. It is an object of the present invention to provide a Schottky barrier semiconductor device having a small directional voltage drop and a method for manufacturing the same.

[0009]

A Schottky barrier semiconductor device according to the present invention comprises a semiconductor substrate of a first conductivity type and a semiconductor of a first conductivity type formed on the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate. A layer, a buried layer of a first conductivity type provided from the boundary between the semiconductor layer and the semiconductor substrate to near the surface of the semiconductor layer and having a higher impurity concentration than the semiconductor layer, and an outer peripheral portion of the buried layer A second conductive type guard ring formed on the surface side of the semiconductor layer, and a metal layer forming a Schottky barrier provided on the surface of the semiconductor layer on the buried layer so as to cover the guard ring. It consists of

[0010] With this structure, the semiconductor layer in the operation region below the metal layer forming the Schottky barrier has a low impurity concentration on the surface side, and the Schottky barrier is sufficiently formed together with the metal layer while forming the Schottky barrier. The layer is very thin and the lower side is a buried layer with a high impurity concentration,
The operating resistance can be sufficiently reduced. On the other hand, in the guard ring portion, since the buried layer is not formed, a semiconductor layer having a low impurity concentration is ensured to have a sufficient thickness under the guard ring, and the depletion layer is sufficiently widened to maintain a high withstand voltage. it can.

According to a second aspect of the present invention, there is provided a Schottky barrier semiconductor device, comprising: a first conductivity type semiconductor substrate; and a first conductivity type semiconductor layer formed on the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate. Forming a guard ring of the second conductivity type formed on the outer peripheral portion of the semiconductor layer on the surface side of the semiconductor layer; and forming a Schottky barrier provided on the surface of the semiconductor layer so as to cover the guard ring. In the region where the Schottky barrier is formed, a region having an impurity concentration higher than the impurity concentration of the semiconductor substrate from the impurity concentration of the semiconductor layer is formed in the region where the Schottky barrier is formed from the surface of the semiconductor layer toward the back surface of the semiconductor substrate. Having an impurity concentration distribution region that reaches the impurity concentration of the semiconductor substrate through
In the guard ring forming portion, the impurity concentration distribution from the lower surface of the guard ring toward the rear surface of the semiconductor substrate is the same as the impurity concentration of the semiconductor substrate while maintaining the impurity concentration of the semiconductor layer.

The method of manufacturing a Schottky barrier semiconductor device according to the present invention comprises the steps of: (a) forming a first conductive type semiconductor substrate in one region;
A semiconductor layer of the first conductivity type is grown after the impurity of the conductivity type is introduced, and (b) a guard ring is formed by introducing an impurity of the second conductivity type on the surface of the semiconductor layer around the impurity introduction region. At the same time, the buried layer is formed by diffusing the introduced first conductivity type impurity into the semiconductor layer, and (c) forming a Schottky barrier on the surface of the semiconductor layer so as to cover a part of the guard ring. It is characterized in that a metal layer is provided.

[0013]

Next, a Schottky barrier semiconductor device of the present invention and a method of manufacturing the same will be described with reference to the drawings.

FIG. 1 shows a Schottky barrier semiconductor according to the present invention.
FIG. 2 is an explanatory cross-sectional view of an SBD that is an embodiment of the device. Figure
In 1, 1, for example, the impurity concentration is 1 × 10¹⁹degree
N ⁺Mold silicon, the thickness is, for example, 200-
A semiconductor substrate of about 250 μm, on which an operation layer is formed
The impurity concentration is, for example, 1 × 10^FifteenDegree n^-Mold semiconductor
The layer 2 is formed to a thickness of, for example, about 5 μm, and
In the region, the semiconductor layer is formed at the junction between the semiconductor substrate 1 and the semiconductor layer 2.
2 has an impurity concentration of, for example, 1 × 10²⁰About
Degree n⁺A mold buried layer 6 is formed. Embedded layer 6 is half
Impurities introduced into the surface of the conductive substrate 1 are semiconductive in the diffusion process.
It is formed by rising to the surface side of the body layer 2 and operates
In the region, the impurity concentration is n^-Thickness of semiconductor layer 2 of mold
D_TwoIs about 1 μm and the other part is a semiconductor substrate
1 is composed of a semiconductor layer having a high impurity concentration up to the back surface.
You. The rising height of the buried layer 6 is determined by the diffusion coefficient of the impurity.
And the diffusion time can be controlled precisely,
The thickness d of the remaining semiconductor layer 2_TwoIs precisely controlled at will.

In the outer peripheral portion of the buried layer 6, a p ⁺ -type region serving as a guard ring 4 is provided at a depth of about 2 μm on the surface of the semiconductor layer 2 so as to cover the guard ring 4. A metal layer 3 that forms a Schottky barrier (Schottky junction) with a semiconductor layer such as molybdenum (Mo) or titanium (Ti) is provided on the surface of the layer 2. Since the buried layer 6 is not formed in the part of the guard ring 4, the thickness of the semiconductor layer 2 having a low impurity concentration remains under the guard ring 4, and in the above-described example, the guard ring 4 and n ⁺ The distance d ₁ from the mold semiconductor substrate 1 is about 3 μm. Incidentally, it is formed to be approximately equal intervals to as the distance d ₁ between the burying layer 6 and the guard ring 4. Metal layer 3
An electrode made of Ni, Au or the like is formed on the upper surface and on the back surface of the semiconductor substrate 1 (both are not shown). Reference numeral 5 denotes an insulating film.

As described above, the surface of the semiconductor layer 2 in the operation region where the metal layer 3 is in contact and the guard ring 4 surrounding the semiconductor layer 2 are flat, and in the operation region, the embedded layer 6 is formed. , with the thickness d ₂ of the low impurity concentration semiconductor layer 2 is very thin, are formed regions of rather higher impurity concentration than the semiconductor substrate 1 is not buried layer 6 in 4 parts of the guard ring, The feature of the present invention is that the semiconductor layer 2 having a low impurity concentration in contact with the guard ring 4 has a sufficient thickness d ₁ .

The operation area (position shown by A in FIG. 1) of this configuration and the area where the guard ring 4 is formed (FIG. 1)
2 (a) and 2 (b) schematically show the distribution of the impurity concentration from the front surface of the semiconductor layer 2 to the back surface of the semiconductor substrate 1 at the position (B). That is, FIG.
(A) is a distribution diagram of the impurity concentration in the operation region (the position indicated by A in FIG. 1). The impurity concentration in the initial semiconductor layer 2 from the surface side of the semiconductor layer 2 to about 1 μm is about 1 × 10 ^15. Concentration, then the impurity concentration increases and the peak is 1
^At about × 10 ²⁰ , the impurity concentration of the semiconductor substrate 1 becomes slightly lower thereafter and becomes about 1 × 10 ¹⁹ . On the other hand, as shown in FIG. 2B, the portion of the guard ring 4 for ensuring the withstand voltage is a p ⁺ -type region having a depth of about 2 μm from the surface, and then has an impurity concentration of about 1 × 10 ^15. Is continued for about 3 μm, and thereafter, the impurity concentration of the semiconductor substrate 1 is about 1 × 10 ¹⁹ . As described above, the Schottky barrier semiconductor device of the present invention is also characterized in that a region having a higher impurity concentration than the semiconductor substrate 1 is formed between the semiconductor layer 2 and the semiconductor layer 2 having a low impurity concentration in the operation layer. However, if a region higher than the impurity concentration of the semiconductor layer 2 is formed by the formation of the buried layer 6, the operating resistance can be reduced and a semiconductor Schottky barrier semiconductor device with high characteristics can be obtained.

The above-mentioned buried layer 6 may not be formed over the entire area of the operation region, but may be provided by being divided into two or more as shown in FIG. That is, since the current is drawn to the buried layer 6 having a small resistance and flows, even if the buried layer 6 is formed separately, the operating resistance is hardly increased unless the interval is extremely wide. Thus, a Schottky barrier semiconductor device having a low operating voltage is obtained. In FIG. 4, the other reference numerals are those in FIG.
The same parts as those described above are shown, and the description thereof is omitted.

Next, the reason why the Schottky barrier semiconductor device of the present invention operates with a low operating resistance and has a high withstand voltage will be described. In the Schottky barrier semiconductor device of the present invention, by forming the buried layer 6 having a high impurity concentration, the thickness d _{2 of the} low-concentration impurity semiconductor layer required to form the Schottky barrier is formed to be as small as possible. Since the other portion of the operation region has a high impurity concentration, the operation resistance is reduced. That is, unless the impurity concentration of the semiconductor layer in contact with the metal layer is low, the Schottky barrier is not formed and an ohmic contact is formed. However, the impurity concentration of only the semiconductor layer in a portion necessary for forming the Schottky barrier is reduced. Since the impurity concentration of the underlying semiconductor layer is increased, the operating resistance can be sufficiently reduced.

On the other hand, the guard ring 4 is provided to improve the breakdown voltage at the peripheral portion of the Schottky junction as described above, and the breakdown voltage at the peripheral portion is regulated by the pn junction. The breakdown voltage of the pn junction increases as the depletion layer formed at the junction increases. The depletion layer is formed wider as the impurity concentration of the semiconductor layer is lower. In the present invention, the buried layer 6 is formed at the pn junction where the depletion layer is formed.
Is not formed, the thickness d ₂ of the semiconductor layer 2 having a low impurity concentration is sufficient, and the depletion layer of the pn junction can be sufficiently widened to maintain a high breakdown voltage. If the semiconductor layer 2 is formed as thick as about 10 μm, a high withstand voltage of about 400 to 600 V can be obtained.

According to the present invention, since the semiconductor layer in the operation region is not thinned by etching, a step at the boundary with the guard ring and a window opening for etching generated due to the etching. There is no step between the insulating film and the semiconductor layer due to over-etching below the insulating film in the step. As a result, the metal layer 3 formed on this surface
Also, there is no problem that the step coverage is poor due to poor step coverage of the electrode film, the breakdown voltage is reduced, and the electrode metal on the upper portion is short-circuited. Therefore, the withstand voltage can be sufficiently improved without causing a problem due to the etching, and the operating resistance in the operating region can be kept low.

Next, a method of manufacturing the Schottky barrier semiconductor device will be described with reference to FIG.

First, as shown in FIG. 3A, a protective film such as SiO ₂ is formed on the surface of a semiconductor substrate 1 having a high impurity concentration of about 1 × 10 ¹⁹ and a thickness of about 500 μm. The mask 11 is formed by performing patterning so that a portion where a region is formed is opened. Then 900-1
An n-type impurity such as phosphorus is diffused at about 100 ° C. for about 0.5 to 2 hours to form a high-concentration impurity region 12 having a high impurity concentration of about 1 × 10 ¹⁶ to 1 × 10 ²¹ . The formation of the high concentration impurity region 12 may be performed by ion implantation.

Next, as shown in FIG. 3B, the specific resistance is 0.1 to 10 Ω · c over the entire surface of the semiconductor substrate 1.
m (impurity concentration is about 1 × 10 ¹⁴ to 1 × 10 ¹⁶ ) n ⁻
The type semiconductor layer 2 is deposited by epitaxial growth of about 1 to 5 μm.

Thereafter, as shown in FIG. 3C, a mask 13 having an opening in the outer peripheral portion of the operation region is formed by a thermal oxidation method or the like, and a p-type impurity such as boron is removed at, for example, about 1180 ° C. The guard ring 4 is formed by thermal diffusion for about 5 hours. At this time, the n-type impurity in the high impurity region 12 rises to the n ⁻ -type semiconductor layer 2 to form the buried layer 6.

Next, as shown in FIG. 3D, the surface of the semiconductor layer 2 is covered with M
A metal layer 3 for forming a Schottky barrier such as o (molybdenum) or Ti (titanium) is formed by vacuum deposition or the like, and the back surface of the semiconductor substrate 1 is polished and thinned. Au or Ni
An SBD chip is formed by evaporating an electrode material such as this and dicing it into each chip. Reference numeral 5 denotes an insulating film.

That is, according to the manufacturing method of the present invention, only the impurity of the same conductivity type is introduced in advance in the state of the semiconductor substrate 1 and the impurity concentration of the operation region is not required after that without any special process. The semiconductor layer having a low impurity concentration can be made thin, and the semiconductor layer having a low impurity concentration can be formed thick in the guard ring 4 portion. As a result, a Schottky barrier semiconductor device having a high withstand voltage and a low operating voltage can be obtained.

The forward voltage-current characteristic of the SBD of the present invention manufactured by this method is indicated by P in FIG. 5 as compared with the voltage-current characteristic Q of the conventional SBD having the structure shown in FIG. At the same current density of 1 × 10 ² A / cm ² , the forward voltage was 0.5 V in the prior art, but 0.4 V in the present invention.
It can be seen that the operating voltage can be extremely reduced.
That is, a high withstand voltage can be obtained, a forward operating voltage can be reduced, and high current characteristics can be obtained.

[0029]

According to the present invention, the buried layer is formed from the boundary between the semiconductor substrate having a high impurity concentration and the semiconductor layer having a low impurity concentration to the surface side of the semiconductor layer in the operation region. A semiconductor layer having a low impurity concentration in a layer can be controlled to be very thin. On the other hand, in the guard ring portion, a semiconductor layer having no buried layer and having a low impurity concentration can be formed thick. As a result, a Schottky barrier semiconductor device having a high withstand voltage and a low operating voltage can be obtained. Moreover, since there is no need to etch the surface of the semiconductor layer,
The problem of coverage of the metal layer due to the step does not occur, and the reliability is greatly improved.

[Brief description of the drawings]

FIG. 1 is an explanatory cross-sectional view of one embodiment of a Schottky barrier semiconductor device of the present invention.

FIG. 2 is a diagram showing an impurity concentration distribution of the Schottky barrier semiconductor device of FIG. 1;

FIG. 3 is a diagram illustrating a manufacturing process of the Schottky barrier semiconductor device of FIG. 1;

FIG. 4 is a diagram showing another example of the structure of the Schottky barrier semiconductor device of the present invention.

5 is a diagram showing voltage-current characteristics of the Schottky barrier semiconductor device of FIG.

FIG. 6 is an explanatory sectional view of a conventional Schottky barrier semiconductor device.

FIG. 7 is an explanatory sectional view of another structure of a conventional Schottky barrier semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 semiconductor layer 3 metal layer 4 guard ring 6 buried layer

Claims (3)

[Claims] 1. A semiconductor substrate of a first conductivity type, a semiconductor layer of a first conductivity type formed on the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate, and a boundary between the semiconductor layer and the semiconductor substrate A buried layer of a first conductivity type having a higher impurity concentration than the semiconductor layer provided from the first conductive type to the vicinity of the surface of the semiconductor layer; A Schottky barrier semiconductor device, comprising: a guard ring of a mold type; and a metal layer forming a Schottky barrier provided on the surface of the semiconductor layer on the buried layer so as to cover the guard ring. 2. A semiconductor substrate of a first conductivity type, a semiconductor layer of a first conductivity type formed on the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate, and a semiconductor layer formed at an outer peripheral portion of the semiconductor layer. A second conductive type guard ring formed on the front surface side, and a metal layer forming a Schottky barrier provided on the surface of the semiconductor layer so as to cover the guard ring, the region forming the Schottky barrier In the region from the front surface of the semiconductor layer to the back surface of the semiconductor substrate, a region having an impurity concentration distribution ranging from the impurity concentration of the semiconductor layer to the impurity concentration of the semiconductor substrate through a region having an impurity concentration higher than the impurity concentration of the semiconductor substrate. Wherein the semiconductive layer is formed in the guard ring forming portion from the lower surface of the guard ring toward the rear surface of the semiconductor substrate while maintaining the impurity concentration of the semiconductor layer. A Schottky barrier semiconductor device having an impurity concentration distribution that reaches the impurity concentration of the body substrate. 3. A method according to claim 1, wherein: (a) a first conductivity type impurity is introduced into one region of the first conductivity type semiconductor substrate, and then a first conductivity type semiconductor layer is grown; and (b) an outer periphery of the impurity introduction region. Forming a guard ring by introducing a second conductivity type impurity into the surface of the semiconductor layer, and forming a buried layer by diffusing the introduced first conductivity type impurity into the semiconductor layer; A method of manufacturing a Schottky barrier semiconductor device, comprising: providing a metal layer for forming a Schottky barrier on a surface of the semiconductor layer so as to cover a part of a guard ring.