JPH0260060B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a new method for controlling the K value and threshold voltage of a compound semiconductor field effect transistor.

Microelectronics has become the foundation of modern industrial progress and has had a major impact on social life. Currently, silicon (Si) semiconductor devices are the mainstay of microelectronics, and integrated circuit devices using bipolar transistor elements and MOS field effect transistor elements are making great progress.

Furthermore, in order to achieve improvements in operating speed that exceed the limits based on the physical properties of silicon, semiconductor devices using compound semiconductors such as gallium arsenide (GaAs), whose carrier mobility is much higher than that of silicon, have been developed.

As a transistor using a compound semiconductor,
Field effect transistors, particularly shot-barrier field effect transistors, have been developed in advance because of their simple manufacturing process, and efforts are being made to put these devices to practical use in integrated circuit devices.

[Conventional technology]

Schottky barrier field effect transistors (hereinafter abbreviated as MES FETs) are currently made of compound semiconductors.
In particular, there are many examples in which GaAs is used as the semiconductor material, and an example of its structure is shown in the schematic side sectional view of FIG.

In the conventional example shown in the figure, an n-type channel layer 12 is formed on a semi-insulating GaAs substrate 11, for example, by ion implantation or by a GaAs epitaxial growth layer doped with impurities.
A gate electrode 13 is disposed on the shaped channel layer 12 and in contact therewith.

Impurities are introduced by an ion implantation method using the gate electrode 13 as a mask to form n ⁺ type source and drain regions 14 with a higher impurity concentration than the n type channel layer 12, and an insulating film 15 is deposited. , n ⁺ type source and drain regions 14 are provided with source and drain electrodes 16 in ohmic contact with them.

When configuring an integrated circuit device using the MES FET as described above, the main parameters that define the device characteristics required are the threshold voltage V _th and the K value, which is a voltage-independent factor of the transconductance g _n or g _n . (K=εμW _g /2aL _g ; a is the depth of the channel layer, ε is the dielectric constant of the channel layer, μ is the carrier mobility, W _g is the gate width, and L _g is the gate length)
There is.

In the conventional example, the threshold voltage V _th and the K value are controlled by controlling the n-type channel layer 12 depending on the ion implantation conditions.
This is carried out by selecting the depth a and the carrier concentration.

For higher speed and higher integration of integrated circuit devices
As the miniaturization of MES FET elements progresses and their gate lengths are shortened, the range of fluctuations in characteristics such as threshold voltage V _th and K value from the expected values gradually increases, and this fluctuation also occurs in MOS semiconductors. It depends on the direction of the gate with respect to the crystal zone axis of the substrate.

The cause of this so-called short channel effect is
Attention has been focused on the penetration of highly concentrated impurities introduced into the source and drain regions 14 into the channel layer 12 and the effect of piezoelectric polarization produced in the semiconductor substrate mainly by the insulating film 15.

Changes in characteristics due to this piezoelectric polarization are caused by MES FET
Insulating film 1 provided in contact with the semiconductor substrate of the element
5. Due to the stress exerted on the semiconductor substrate by the gate electrode 13, etc., piezoelectric polarization having a unique polarity in the gate direction with respect to the crystal zone axis is generated in the compound semiconductor substrate, and the distribution of carriers in the channel layer 12 changes, resulting in shot torque. It is believed that because the depletion layer expands and contracts, the threshold voltage V _th fluctuates in different directions corresponding to the gate direction with respect to the crystal zone axis of the compound semiconductor substrate.

(e.g. PMAsbeck et al.; IEEE
Transactionson Electron Devices, Vol.ED−
31, No. 10, Oct. 1984) Similarly, the K value also fluctuates due to changes in the depth a of the channel layer due to charges generated by piezoelectric polarization.

[Problem that the invention seeks to solve]

The above-described variations in the characteristics of the MES FET element, such as threshold voltage and K value, impede the perfect operation of semiconductor circuits that use it, and greatly restrict progress in miniaturization and higher integration of elements in compound semiconductor integrated circuit devices. do.

However, conventional manufacturing methods do not have effective means for controlling these characteristics after ion implantation of the channel layer, and there is a strong demand for means for correcting these characteristics during the manufacturing process.

[Means for solving problems]

The above problem can be solved by providing an insulating film on a compound semiconductor substrate on which a field effect transistor element is formed.
This problem is solved by the method of manufacturing a semiconductor device according to the present invention, which controls piezoelectric polarization in the compound semiconductor substrate by stress exerted by the insulating film and corrects at least one of the K value and the threshold voltage of the field effect transistor element.

[Effect]

In connection with the above-mentioned variation in characteristics of compound semiconductor field effect transistors due to piezoelectric polarization, the present inventors have investigated, for example, the stress generated in the GaAs compound semiconductor substrate, the material and thickness of the insulating film, the crystal plane of the semiconductor substrate,
The correlation between the crystal zone axis and the state of piezoelectric polarization due to this stress, the K value of a field effect transistor, the threshold voltage, and the state of piezoelectric polarization was studied, and a correlation as illustrated in FIG. 1, for example, was obtained.

The figure shows an n-type channel layer formed on the (100) plane of a GaAs single crystal using the energy of silicon (Si) ions.
59keV, dose 0.9×10 ¹² cm ^-2 or 1.8×10 ¹² cm ^-2
formed by implantation of MES FET L _g =0.6μ
A gate electrode with m, W _g = 20 μm is provided using tungsten silicide (WSi) with the gate width direction in the [011] and [011] directions, and a silicon dioxide (SiO ₂ ) film is deposited on it to a thickness of 0. Represents the threshold voltage V _th and K value when formed at ~1200 nm, 〇 is the [011] direction with a dose of 0.9 × 10 ¹² cm ^-2 , and ● is the [011] direction with a dose of 1.8 × 10 ¹² cm ^-2 , △ is the [001] direction with a dose of 0.9×10 ¹² cm ^-2 ▲ is the thickness of the SiO ₂ film shown in the figure for the case of the [011] direction with a dose of 1.8×10 ¹² cm ^-2 The threshold voltage V _th and K value at the time are shown.

From the same figure, when the gate width direction is [011] direction, comparing the dose amount of 0.9×10 ¹² cm ^-2 and 1.8×10 ¹² cm ^-2 , for example, when the thickness of the SiO ₂ film is 0 mm. ,
The K value increases by 0.6 mA/V ² and the threshold voltage V _th changes by about 0.9 V, while the dose amount is 0.9×10 ¹² cm ^-2
It is known that if a SiO ₂ film is deposited from 0 nm to 1200 nm, the amount of change in the threshold voltage V _th will be a little less than 0.6 V, and the increase in the K value will be doubled to about 1.5 mA/V ² . In this way, for example, it is possible to greatly increase the K value depending on the thickness of the SiO ₂ film, and by selecting the K value within a wide range, it is possible to keep the threshold voltage V _th within a narrow variation range. be.

The SiO ₂ film applies tensile stress to the channel layer, and when the gate width direction is in the [011] direction, there is an effective positive charge on the channel layer, and when the gate width direction is in the [011] direction, there is an effective charge on the channel layer. A negative charge is generated in the insulating film, producing the above effect. However, if silicon nitride (Si ₃ N ₄ ), for example, is used as the insulating film, compressive stress is applied to the channel layer, and the piezoelectric polarization becomes the opposite polarity. A similar correlation can be obtained by reversing the gate width direction of FIG.

Furthermore, for example, if silicon nitride oxide (SiN _x O _y ) with selected compositions x and y is used as the insulating film material, or if insulating films with different compositions are stacked, the strength of piezoelectric polarization, and therefore the K value and The degree of freedom in controlling the amount of correction of the threshold voltage V _th increases.

〔Example〕

The present invention will be specifically explained below using examples.
FIG. 2 is a schematic side sectional view showing the process order of an embodiment of the present invention relating to a GaAs MES FET.

Refer to Figure 2a. For example, Si is ion-implanted into the semi-insulating GaAs substrate 1 at an energy of 59 keV and a dose of about 0.9×10 ¹² cm ^-2 , and aluminum nitride (AIN) is implanted onto the surface of the substrate 1.
A protective film (not shown) is provided, and activation heat treatment is performed at a temperature of 850°C for about 10 minutes, for example.
An n-type channel layer 2 having an impurity concentration of approximately 1.5×10 ¹⁷ cm ⁻³ is formed.

For example, W ₅ Si ₃ is deposited to a thickness of about 400 nm on one surface of the GaAs substrate by sputtering or the like, and this is patterned to form the gate electrode 3 . In this embodiment, the gate length is approximately 0.6 μm.

For example, on the substrate 1 using the gate electrode 3 as a mask,
Si at energy 175keV, dose 1.7×10 ¹³ cm
Ion implantation is performed at a temperature of about ^-2 , for example at a temperature of 750°C for a period of time.
After performing activation heat treatment for about 15 minutes, the n ⁺ type source and drain regions 4 with an impurity concentration of about 1×10 ¹⁸ cm ^-3 were formed.
form.

See Figure 2b. For example, plasma chemical vapor deposition (P-CVD)
A SiO ₂ film 5 is deposited on the substrate 1 and the gate electrode 3 to a thickness of about 300 nm, for example.

Openings are formed in the SiO ₂ film 5 on the n ⁺ type source and drain regions 4, and the source and
A drain electrode 6 is formed.

See Figure 2c K value and threshold voltage of the formed MES FET element
V _th is measured, the difference in SiO ₂ film thickness required to realize the target value is determined based on the data shown in FIG. 1, etc., and the SiO ₂ film 7 is deposited by this film thickness difference.
In the above embodiment, _the SiO ₂ film 5 is first formed as thin as, for example, 300 nm, and the SiO ₂ film 7 is added after the characteristics are measured. may be etched.

Further, in the embodiment described above, the same material is used for forming the insulating films twice, but insulating films having different compositions may be stacked.

Although the above explanation is directed to GaAs MES FETs, the effects of the present invention can also be obtained when using compound semiconductor materials other than GaAs, such as indium phosphide (InP), indium gallium arsenide (InGaAs), etc. . Furthermore, similar effects can be obtained by the method of the present invention for pn junction gate type and insulated gate type field effect transistors, high electron mobility field effect transistors with heterojunctions, and the like.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to easily and accurately correct the K value and threshold voltage of a compound semiconductor field effect transistor. This improves the characteristics of field effect transistors,
A great effect can be obtained on the practical application of compound semiconductor integrated circuit devices.

[Brief explanation of drawings]

Fig. 1 is a diagram showing an example of the correlation between K value and threshold voltage using parameters such as insulating film thickness of MES FET, Fig. 2 is a schematic side sectional view of the process order showing an embodiment of the present invention related to MES FET, Figure 3 is a schematic side sectional view showing a conventional example of an MES FET. In the figure, 1 is a semi-insulating GaAs substrate, 2 is an n-type channel layer, 3 is a gate electrode made of W ₅ Si ₃ , 4 is an n ⁺ type source and drain region, 5 is the first SiO ₂ film, and 6 is the The source and drain electrodes, 7, indicate the second SiO ₂ film.

Claims (1)

[Claims] 1. An insulating film is provided on a compound semiconductor substrate on which a field effect transistor element is formed, and piezoelectric polarization within the compound semiconductor substrate is controlled by stress exerted by the insulating film, and the K value and threshold voltage of the field effect transistor element are controlled. A method for manufacturing a semiconductor device, comprising correcting at least one of the following.