JPS635571A - Compound semiconductor device - Google Patents
Compound semiconductor deviceInfo
- Publication number
- JPS635571A JPS635571A JP15038986A JP15038986A JPS635571A JP S635571 A JPS635571 A JP S635571A JP 15038986 A JP15038986 A JP 15038986A JP 15038986 A JP15038986 A JP 15038986A JP S635571 A JPS635571 A JP S635571A
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- compound semiconductor
- gaas
- stress
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 150000001875 compounds Chemical class 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 14
- 230000001681 protective effect Effects 0.000 abstract description 4
- 230000005669 field effect Effects 0.000 abstract description 3
- 229910018885 Pt—Au Inorganic materials 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000010408 film Substances 0.000 description 19
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 12
- 238000005468 ion implantation Methods 0.000 description 4
- 238000000137 annealing Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical group [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は化合物半導体装置に関する。[Detailed description of the invention] (Industrial application field) The present invention relates to a compound semiconductor device.
（従来の技術）
化合物半導体装置例えば砒化ガリウム（ＧａＡｓ）を用
いたショットキ障壁型電界効果トランジスタ（以下ＭＥ
ＳＦＥＴと称す）として、第３図に示すような構造が知
られている。図において１′は耐熱性ゲート電極、２ａ
’はソース電極、２６”はドレイン電極、３′はＧａＡ
ｓ動作層（ｎ層）、４′は高濃度不純物層（ｎ十層）、
５′は半絶縁性ＧａＡｓ基板、６′は保護膜、７′は第
２層金属である。(Prior art) Compound semiconductor devices such as Schottky barrier field effect transistors (hereinafter referred to as ME) using gallium arsenide (GaAs)
A structure as shown in FIG. 3 is known as an SFET. In the figure, 1' is a heat-resistant gate electrode, 2a
' is the source electrode, 26'' is the drain electrode, 3' is GaA
s operating layer (n layer), 4' is a high concentration impurity layer (n0 layer),
5' is a semi-insulating GaAs substrate, 6' is a protective film, and 7' is a second layer metal.
現在、このようなＭＥＳＦＥＴを用いた高速の集積回路
が製作されている。Currently, high-speed integrated circuits using such MESFETs are being manufactured.
（発明が解決しようとする問題点）
ＧａＡｓＭＥＳＦＥＴを製作した場合、現状では所望の
ＦＥＴのしきい値電圧を得ることが困難であり、従って
ＦＥＴまたはＦＥＴを用いた集積回路の歩留まりが極め
て低い問題がある。しきい値電圧を決定する動作層（ｎ
層）の形成はイオン注入法が良く用いられているが、Ｇ
ａＡｓ半絶縁性基板の特性もしくはイオン注入後のアニ
ール条件等にばらつきがあるためと考えられているが、
実際には、まだその原因は不明である。(Problems to be Solved by the Invention) When GaAs MESFETs are manufactured, it is currently difficult to obtain a desired threshold voltage of the FETs, and as a result, the yield of FETs or integrated circuits using FETs is extremely low. be. The operating layer (n
Although ion implantation is often used to form G
This is thought to be due to variations in the characteristics of the aAs semi-insulating substrate or the annealing conditions after ion implantation.
Actually, the cause is still unknown.
本発明の目的は、上記の問題点に鑑み、化合物半導体電
界効果トランジスタのしきい値電圧を所望の値に制御す
る化合物半導体装置を提供することにある。SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a compound semiconductor device that controls the threshold voltage of a compound semiconductor field effect transistor to a desired value.
（問題点を解決するための手段）
本発明の化合物半導体装置は化合物半導体基板の一表面
に、化合物半導体装置を有する該基板の他表面に応力を
有する絶縁膜あるいは金属膜が設けられてなることを特
徴とする化合物半導体装置で構成される。(Means for Solving the Problems) A compound semiconductor device of the present invention is provided with an insulating film or a metal film having stress on one surface of a compound semiconductor substrate and the other surface of the substrate having the compound semiconductor device. It is composed of a compound semiconductor device characterized by:
（作用）
本発明は基板の裏面に応力を有する金属膜を被着して基
板を曲げた場合、ＧａＡｓＭＥＳＦＥＴのしきい値電圧
ｖＴが基板の曲率またはそり量に比例して変化するとい
う発見に基づいたものである。第２図はその実験結果で
、基板のそり量とそりが加わることによるｖＴの変化と
の関係を示している。ＧａＡｓのようにせん亜鉛鉱構造
では結晶に歪みが加えられると分極が誘起され、その分
極により電荷が発生することが知られている。本発明の
ように基板をそらせた場合、ＧａＡｓ基板上に形成され
たゲート電極膜、絶縁膜またはオーミック電極のエツジ
部を中心にＧａＡｓ基板内に歪みが発生するか、または
これらの電極膜または絶縁膜の応力によって生じている
歪みが変化すると予想される。従ってその歪みに応じて
動作層に電荷の増減が生じるためｖＴが変化すると考え
られる。(Function) The present invention is based on the discovery that when a metal film having stress is applied to the back surface of a substrate and the substrate is bent, the threshold voltage vT of a GaAs MESFET changes in proportion to the curvature or warpage of the substrate. It is something that FIG. 2 shows the experimental results, showing the relationship between the amount of warpage of the substrate and the change in vT due to the addition of warp. It is known that in a zincite structure such as GaAs, polarization is induced when strain is applied to the crystal, and electric charges are generated due to the polarization. When the substrate is deflected as in the present invention, distortion may occur within the GaAs substrate centering around the edges of the gate electrode film, insulating film, or ohmic electrode formed on the GaAs substrate, or distortion may occur in the GaAs substrate around the edges of the gate electrode film, insulating film, or ohmic electrode formed on the GaAs substrate, or these electrode films or insulating films may be distorted. It is expected that the strain caused by the stress in the film will change. Therefore, it is considered that vT changes because the charge increases or decreases in the active layer in accordance with the strain.
（実施例）
次に、本発明の一実施例について図面を参照して説明す
る。(Example) Next, an example of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｅ）は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図である。FIGS. 1A to 1E are cross-sectional views of a semiconductor chip shown in order of steps for explaining an embodiment of the present invention.
先ず、第１図（ａ）に示すように、ＧａＡｓ半絶縁性基
板５の表面にＳｉイオンを５０ＫｅＶ、２ Ｘ １０１
０１２ａ”の条件でイオン注入１、さらにＡｓ圧圧器囲
気中８００°Ｃ２２０分間のアニールを行いＧａＡｓ動
作層３を形成する。First, as shown in FIG. 1(a), Si ions were applied to the surface of a GaAs semi-insulating substrate 5 at 50 KeV and 2×101
The GaAs active layer 3 is formed by ion implantation 1 under the conditions of 012a'' and then annealing at 800° C. for 220 minutes in the atmosphere of an As pressurizer.
次に、第１図（ｂ）に示すように、動作層３を覆うよう
に半絶縁性基板５上にタングステンシリサイド（ＷＳｉ
）をスパッタ法を用いて０．５ｐｍの膜厚に堆積した後
、通常のホトリソグラフィ法と四フッ化炭素を用いたド
ライエツチング法とによってＷＳｉの膜を所定の形にパ
ターニングし、ショットキゲート１を形成する。Next, as shown in FIG. 1(b), tungsten silicide (WSi) is placed on the semi-insulating substrate 5 so as to cover the active layer 3.
) was deposited to a thickness of 0.5 pm using a sputtering method, and then the WSi film was patterned into a predetermined shape by ordinary photolithography and dry etching using carbon tetrafluoride. form.
続いて、第１図（ｅ）に示すように、ショットキゲート
１をマスクにして、Ｓｉイオンを１５０ＫｅＶ。Next, as shown in FIG. 1(e), using the Schottky gate 1 as a mask, Si ions were heated at 150 KeV.
５×１０１３ｃｍ−３の条件でイオン注入１、更にＡｓ
圧圧器囲気中７５０°Ｃ２２０分間のアニールを行いｎ
中層４ａ、４ｂを形成する。Ion implantation 1 under the condition of 5 x 1013 cm-3, and then As
Annealed at 750°C for 220 minutes in the atmosphere of a pressure vessel.
Middle layers 4a and 4b are formed.
続いて、第１図（ｄ）に示すようにＡｕＧｅ−Ｎｉの金
属層からなるソース電極２ａ及びドレイン電極２ｂを形
成した後、保護膜として５ｉ０２膜６を形成した後、ゲ
ート電極１、ソース電極２ａ、ドレイン電極２ｂ上にＴ
ｉ−Ｐｔ−Ａｕからなる第２層金属膜７を形成する。Subsequently, as shown in FIG. 1(d), a source electrode 2a and a drain electrode 2b made of a metal layer of AuGe-Ni are formed, and then a 5i02 film 6 is formed as a protective film. 2a, T on the drain electrode 2b
A second layer metal film 7 made of i-Pt-Au is formed.
ここで、このＭＥＳＦＥＴのしきい値電圧ｖＴを測定し
た結果、所望のｖＴと５０ｍＶのずれがあることがわか
った。そこで第１図（ｅ）に示すようにこのＧａＡｓ基
板の裏面に２ Ｘ １０１Ｏｄｙｎ／ｃｍ２の膜応力を
有するＷ膜を２ｐｍ全面蒸着し、所望のｖＴに調節した
。Here, as a result of measuring the threshold voltage vT of this MESFET, it was found that there was a deviation of 50 mV from the desired vT. Therefore, as shown in FIG. 1(e), a 2 pm thick W film having a film stress of 2 x 101 Odyn/cm2 was deposited on the entire surface of the back surface of this GaAs substrate, and the desired vT was adjusted.
（発明の効果）
以上説明したように、本発明はＭＥＳＦＥＴを有する半
導体基板の裏面に応力を有する薄膜を形成することによ
り、ＭＥＳＦＥＴのしきい値電圧の値を所定の値に制御
することができる効果がある。(Effects of the Invention) As explained above, the present invention can control the threshold voltage value of the MESFET to a predetermined value by forming a thin film having stress on the back surface of the semiconductor substrate having the MESFET. effective.
第１図（ａ）〜（ｅ）は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図、第２図は本
発明の一実施例を説明するためのしきい値電圧の変化一
基板のそり量の関係を示した図、第３図は従来のＭＥＳ
ＦＥＴの一例の断面図である。
１．１′・・・ショットキゲート、 ２ａ、２ａ’・・
・ソース電極、２ｂ、２ｂ’・・・ドレイン電極、
３，３′・・・動作層、４ａ、４ａ’、４ｂ、４ｂ’・
ｎ＋層、 ５・・・半絶縁性基板、６・・・保護膜
、 ７・・・第２層金属膜、第 １
図
３動作層
一ノ
４ａ ３ ４ｂ
第 １ 図
第 ２ 図
基板のそり量（μｍ）FIGS. 1(a) to (e) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention, and FIG. 2 is a threshold value for explaining an embodiment of the present invention. A diagram showing the relationship between voltage change and substrate warpage, Figure 3 is a conventional MES
FIG. 2 is a cross-sectional view of an example of an FET. 1.1'... Schottky gate, 2a, 2a'...
・Source electrode, 2b, 2b'... drain electrode,
3, 3'... Operating layer, 4a, 4a', 4b, 4b'.
n+ layer, 5... Semi-insulating substrate, 6... Protective film, 7... Second layer metal film, first
Figure 3 Operating layer 4a 3 4b Figure 1 Figure 2 Amount of warp of substrate (μm)
Claims (1)
る該基板の他表面に応力を有する絶縁膜あるいは金属膜
が設けられてなることを特徴とする化合物半導体装置。1. A compound semiconductor device, comprising: a compound semiconductor substrate, and an insulating film or a metal film having stress on the other surface of the substrate having a compound semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15038986A JPS635571A (en) | 1986-06-25 | 1986-06-25 | Compound semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15038986A JPS635571A (en) | 1986-06-25 | 1986-06-25 | Compound semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS635571A true JPS635571A (en) | 1988-01-11 |
Family
ID=15495923
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15038986A Pending JPS635571A (en) | 1986-06-25 | 1986-06-25 | Compound semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS635571A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6181671A (en) * | 1984-09-28 | 1986-04-25 | Fujitsu Ltd | Compound semiconductor device |
| JPS61123187A (en) * | 1984-11-09 | 1986-06-11 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1986
- 1986-06-25 JP JP15038986A patent/JPS635571A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6181671A (en) * | 1984-09-28 | 1986-04-25 | Fujitsu Ltd | Compound semiconductor device |
| JPS61123187A (en) * | 1984-11-09 | 1986-06-11 | Fujitsu Ltd | Manufacture of semiconductor device |
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