JPS61123187A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the characteristics of a FET b forming an insulating film onto a compound semiconductor base body, to which a FET element is shaped, controlling piezoelectric polarization in the base body by stress from the insulating film and correcting the K value of the FET element and at least one of threshold voltage. CONSTITUTION:Si ions are implanted to a semi-insulating GaAs substrate 1, and activated and thermally treated to form an N type channel layer 2, and a gate electrode 3 is shaped. Si ions are implanted while using the gate electrode 3 as a mask, and activated and thermally treated to form N<+> type source-drain regions 4. An SiO2 film 5 is applied to the substrate 1 and the gate electrode 3, openings are shaped onto the regions 4, and source-drain electrodes 6 are formed. The K value of a FET element shaped and threshold voltage are measured, a difference between SiO2 film thickness required for realizing a target value is obtained, and an SiO2 film 7 is deposited only by the difference between the film thickness. Accordingly, the K value and threshold voltage are corrected easily, thus improving the characteristics of a FET.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a new method for controlling the voltage value and threshold voltage of a compound semiconductor field effect transistor.

Microelectronics has become the foundation of modern industrial progress and has had a major impact on social life. Currently, the mainstay of microelectronics is silicon (Si) semiconductor devices, including bipolar transistor elements and
Integrated circuit devices using 'lOs field effect transistor elements are making great progress.

Furthermore, in order to improve operating speed beyond the limits based on the physical properties of silicon, semiconductor devices using compound semiconductors such as gallium arsenide (GaAs), which have carrier mobility that is warmer and higher than that of silicon, have been developed.

Among transistors using compound semiconductors, field effect transistors, especially Schottky barrier field effect transistors, are being developed first due to their simple manufacturing process, and efforts are being made to put these devices to practical use in integrated circuit devices. or are overlapped.

[Conventional technology]

Schottky barrier field effect transistor (MES)
(abbreviated as FET) is currently a compound semiconductor, especially GaA
In many cases, s is a semiconductor material, and an example of its structure is shown in the schematic side sectional view of FIG.

In the conventional example shown in the figure, n is injected into a semi-insulating GaAs substrate 11 by, for example, ion implantation or by an impurity-doped GaAs epitaxial growth layer.
An n-type channel layer 12 is formed, and this n-type channel layer 12
A gate electrode 13 in Schottky contact is disposed thereon.

Impurities are introduced by an ion implantation method using this gate electrode 13 as a mask, and a diamond-shaped source and drain region 14 having a higher impurity concentration than the n-type channel layer 12 is formed.
Source and drain electrodes 16 are coated with an insulating film 15 and are in ohmic contact with the male-shaped source and drain regions 14.
will be placed.

When configuring an integrated circuit device using the above-mentioned MES PUT as an element, the main parameters that define the element characteristics required are the threshold voltage Vth and the transconductance g1 or g, which are voltage-independent factors.
K=εμWg/2aL9; a is the depth of the channel layer, ε
is the dielectric constant of the channel layer, μ is the carrier mobility, Wg is the gate width, and L9 is the gate length).

In the conventional example, the threshold voltage and its value are controlled by selecting the depth a of the n-type channel layer 12 and the carrier concentration depending on the ion implantation conditions.

MESFET for higher speed and higher integration of integrated circuit devices
As device miniaturization progresses and gate lengths are shortened, the range of variation in characteristics such as threshold voltage and value from expected values gradually increases, and this variation
s It depends on the direction of the gate with respect to the crystal zone axis of the semiconductor substrate.

As causes of this so-called short channel effect, attention has been focused on the penetration of highly concentrated impurities introduced into the source and drain regions 14 into the channel layer 12 and the effect of piezoelectric polarization mainly caused in the semiconductor substrate by the insulating film 15.

This variation in characteristics due to piezoelectric polarization is caused by stress exerted on the semiconductor substrate by the insulating film 15, gate electrode 13, etc. provided in contact with the semiconductor substrate of the MES FET element, which causes the compound semiconductor substrate to have an inherent characteristic in the gate direction with respect to its crystal zone axis. Piezoelectric polarization occurs, and the distribution of carriers in the channel layer 12 changes, causing the Schottky depletion layer to expand and contract. is thought to change.

(P, M, 85 Beck et al.; I
EEE Transactionson Electr
on Devices, Vol. HD-31, No.
lO+Oct.

1984) Similarly, the value also fluctuates due to changes in the depth a of the channel layer due to charges generated by piezoelectric polarization.

[Problem that the invention seeks to solve]

The above-described variations in the characteristics of the MES FET element, such as threshold voltage and K value, impede the perfect operation of semiconductor circuits that use it, and lead to miniaturization of elements in compound semiconductor integrated circuit devices.
This greatly limits progress in areas such as higher integration.

However, conventional manufacturing methods do not have effective means for controlling these characteristics after ion implantation of the channel layer, and there is a strong demand for means for correcting these characteristics during the manufacturing process.

[Means for solving problems]

The above problem is solved by providing an insulating film on a compound semiconductor substrate on which a field effect transistor element is formed, and controlling the piezoelectric polarization within the compound semiconductor substrate by the stress exerted by the insulating film. This problem is solved by a method for manufacturing a semiconductor device according to the present invention, which corrects at least one of the voltage value and the threshold voltage.

[For production]

In connection with the above-mentioned variation in characteristics of compound semiconductor field effect transistors due to piezoelectric polarization, the present inventors have, for example,
The stress generated in the aAs compound semiconductor substrate, the material and thickness of the insulating film, the crystal plane of the semiconductor substrate, the crystal zone axis and the state of piezoelectric polarization due to this stress, the value of field effect transistor, the threshold voltage, and the state of piezoelectric polarization, etc. The correlation was studied and a correlation as illustrated in FIG. 1, for example, was obtained.

The figure shows an n-type channel layer formed on the (100) plane of a GaAs single crystal with a silicon (Si) ion energy of 59 keV.
, dose amount 0.9X10"cm-" or 1.8X1
0' formed by the i main character of "Cm-", MES F
HT glue, =Q, 5μ+n, W.

=20-, the gate width direction is (QITI and (011) direction), and the gate electrode is made of tungsten silicide (-
5i), and silicon dioxide (Si
O□) represents the threshold voltage (■) and value when the film is formed to a thickness of 0 to 1200 nm, ○ indicates the (OII) direction at a dose of 0.9X10"elm-", . indicates a dose of 1.8X10" The value -2 (OL direction, △ is the C0IL direction with a dose of 0.9X10"cm-"), and Mu is the (01) direction with a dose of 1.8X10Izca+-"
For the case of direction 1), the values of the threshold voltage V and V when the 5i01 film has the thickness shown in the figure are shown.

From the figure, when the gate width direction is the (OII) direction,
Dose I (1,9XlO"cm-" and 1.8X101
For example, if the thickness of the SiO2 film is θ
side, the K value increases by approximately 0.6＠＾/vz, the threshold voltage v
1. The change in 1 is approximately 0.9■, while the dose amount is 0.
．． If a 5ifh film is deposited from 0 to 1200 am with 9X10' (J -), the amount of change in threshold voltage is 0
．． At just under 6 V, the value increases by more than double, to approximately 1.5 mA/V.”
It is known that

In this way, for example, it is possible to greatly increase K(ii) depending on the thickness of the 5i(h film, and it is also possible to keep the threshold voltage Vth within a narrow range of variation by selecting the value within a wide range. It is.

The 5in2 film applies tensile stress to the channel layer, and when the gate width direction is in the (OH) direction, there is an effective positive charge on the channel layer, and when the gate width direction is in the (Oll) direction, there is an effective charge on the channel layer. The above effect appears by generating a negative charge, but if the insulating film is made of silicon nitride (SiJ), for example,
If n) is used, compressive stress is applied to the channel layer, and the piezoelectric polarization becomes opposite polarity, and a similar correlation in which the gate width direction of FIG. 1 is reversed is obtained.

Furthermore, for example, if silicon nitride oxide (SiNXOy) with selected compositions x and y is used as the insulating film material, or if insulating films with different compositions are stacked, the strength of piezoelectric polarization, and therefore the value and threshold voltage V, can be increased. The degree of freedom to control the amount of correction is increased by 1o.
do.

〔Example〕

The present invention will be specifically explained below using examples.

FIG. 2 is a schematic side sectional view showing the process order of an embodiment of the present invention relating to a GaAs MES FET.

Fig. 2+a) Refer to semi-insulating GaAs substrate l, for example, Si is applied to it at an energy of 5
Aluminum nitride (AIN
) or the like (not shown), for example, at a temperature of 8.
Activation heat treatment was performed at 50'C for about 10 minutes.
An n-type channel layer 2 having an impurity concentration of about 1.5×10"ca-" is formed.

For example, Ws is deposited on one surface of the GaAs substrate by sputtering or the like.
A gate electrode 3 is formed by depositing Siz to a thickness of about 400 om and patterning it. In this embodiment, the gate length is approximately 0.6 tna.

Using the gate electrode 3 as a mask, for example, Si is applied to the substrate 1 at an energy of 175 keV and a dose of 1.7×10”cm.
-2, for example, at a temperature of 750°C for 1 hour.
Activation heat treatment is performed for about 5 minutes, and the impurity concentration is reduced to 1×1.
0111c7I+-3 round shaped source, F rain fi
Form i-region 4.

Referring to FIG. 2(b), a SiO□ film 5 is deposited on the substrate 1 and the gate electrode 3 to a thickness of, for example, about 3 QOnm, by, for example, a plasma chemical vapor deposition method (P-CVD method).

Openings are formed in the SiO□ film 5 above the ♂-type source and drain regions 4, and gold germanium/gold (AuG
The source and drain electrodes 6 are formed using e.g. □ Figure 2 (see C1) Value and threshold voltage VLh of the formed MES PET element
SiO□ required to measure and achieve the target value
The difference in film thickness is determined based on the data shown in FIG. 1, etc., and the 5iOz film 7 is deposited by the difference in film thickness. In the above embodiment, the SiO□ film 5 is first formed as thin as, for example, 300 nm, and the SiO2 film 7 is added after measuring the characteristics. It may be shown.

Further, in the embodiment described above, the same material is used for forming the insulating films twice, but insulating films having different compositions may be stacked.

Although the above description is directed to GaAs MES FETs, similar effects can be obtained by the method of the present invention using other compound semiconductor materials, or with junction type and old S type field effect transistors.

(Effects of the Invention) As explained above, according to the present invention, it becomes possible to easily and accurately correct the value and threshold voltage of a compound semiconductor field effect transistor.Thereby, the characteristics of the field effect transistor are improved. , a great effect can be obtained on the practical application of compound semiconductor integrated circuit devices.

[Brief explanation of drawings]

Figure 1 is a diagram showing an example of the correlation between values and threshold voltage using parameters such as the insulation film thickness of MES FET, and Figure 2 is a diagram showing an example of the correlation between MES
FIG. 3 is a schematic side sectional view showing the process order of an embodiment of the present invention relating to an FET, and FIG. 3 is a schematic side sectional view showing a conventional example of a MUS FET. In the figure, 1 is a semi-insulating GaAs substrate, 2 is an n-type channel layer, 3 is a gate electrode made of -5Si3, 4 is an n+ type source and drain region, 5 is the first 5iOz film, 6 is the source and drain electrode , 7 indicates the second SiO2 film. τS, °sa agent Patent attorney Hiroshi Matsuoka Department i=-,:f3 に 1 "Nee ≠ ZS Figure 3 Procedural amendment voluntarily) 1. Indication of the case 1959 Patent Order No. 236054 3, Person making amendment 4, agent address: 1015-5 Kamiodanaka, Nakahara-ku, Yozaki City, Kanagawa Prefecture;
1) Page 10, line 20 to page 11, line 3 of the specification of the present application contain compound semiconductor materials other than GaAs, such as indium* (InP) and indium gallium arsenide (InP).
The effects of the present invention can also be obtained when using materials such as GaAs). Furthermore, similar effects can be obtained by the method of the present invention for pn junction gate type and insulated gate type field effect transistors, high electron mobility field effect transistors with heterojunctions, and the like. ”Representative Patent Attorney Hiroshi Matsuoka Department 1. ．． .

Claims (1)

[Claims] An insulating film is provided on the compound semiconductor substrate on which the field effect transistor element is formed, and the piezoelectric polarization within the compound semiconductor substrate is controlled by the stress exerted by the insulating film, and the value and threshold voltage of the field effect transistor element are controlled. A method of manufacturing a semiconductor device, comprising correcting at least one of the following.