JPS63281473A - Field-effect semiconductor device and manufacture thereof - Google Patents
Field-effect semiconductor device and manufacture thereofInfo
- Publication number
- JPS63281473A JPS63281473A JP11782487A JP11782487A JPS63281473A JP S63281473 A JPS63281473 A JP S63281473A JP 11782487 A JP11782487 A JP 11782487A JP 11782487 A JP11782487 A JP 11782487A JP S63281473 A JPS63281473 A JP S63281473A
- Authority
- JP
- Japan
- Prior art keywords
- concentration impurity
- gate electrode
- impurity layer
- layer
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 230000005669 field effect Effects 0.000 title claims description 8
- 239000012535 impurity Substances 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 16
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 12
- 230000000694 effects Effects 0.000 abstract description 9
- 229910052681 coesite Inorganic materials 0.000 abstract description 8
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 8
- 230000003071 parasitic effect Effects 0.000 abstract description 8
- 239000000377 silicon dioxide Substances 0.000 abstract description 8
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 8
- 229910052682 stishovite Inorganic materials 0.000 abstract description 8
- 229910052905 tridymite Inorganic materials 0.000 abstract description 8
- 230000001681 protective effect Effects 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 2
- 238000005468 ion implantation Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- KWLSQQRRSAWBOQ-UHFFFAOYSA-N dipotassioarsanylpotassium Chemical compound [K][As]([K])[K] KWLSQQRRSAWBOQ-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電界効果型半導体装置及びその製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect semiconductor device and a method for manufacturing the same.
半導体装置９例えば砒化カリウム（ＧａＡｓ）を用いた
ショットキ障壁型電界効果トランジスタ（以下、ＭＥＳ
ＦＥＴと称す）として、第３図に示すような構造のもの
が知られている。第３図において、１は耐熱性のケート
電極、２ａはソース電極、２ｂはトレイン電極、３はＧ
ａＡｓからなる動作層、４ｂは高濃度不純物半導体結晶
層（以下高濃度不純物層という）、５はＳｉＯ□膜、６
は半絶縁性のＧ ａ Ａ ｓ基板である。Semiconductor device 9 For example, a Schottky barrier field effect transistor (hereinafter referred to as MES) using potassium arsenide (GaAs)
A structure shown in FIG. 3 is known as an FET (FET). In Figure 3, 1 is a heat-resistant gate electrode, 2a is a source electrode, 2b is a train electrode, and 3 is a G
an active layer made of aAs, 4b a high concentration impurity semiconductor crystal layer (hereinafter referred to as a high concentration impurity layer), 5 a SiO□ film, 6
is a semi-insulating GaAs substrate.
この構造を有するＭＥＳＦＥＴにおいては、高濃度不純
物層４ｂの存在により、ソース、ドレインの直列寄生抵
抗か低減され、高い相互コンダクタンス、低いオン抵抗
が得られ、ＦＥＴの高速動作が可能となる。現在このよ
うなＦＥＴもしくはＦＥＴを用いた集積回路が製作され
ている。In the MESFET having this structure, the presence of the heavily doped impurity layer 4b reduces the series parasitic resistance of the source and drain, resulting in high mutual conductance and low on-resistance, allowing the FET to operate at high speed. Currently, such FETs or integrated circuits using FETs are being manufactured.
上述のＧａＡｓ ＭＥＳＦＥＴを製作する場合、高濃
度不純物層４ｂは、ゲート電極及びゲート電極の側面に
形成された絶縁材からなる側壁をマスクとした選択成長
によって形成される。側壁は高濃度不純物層４ｂとケー
ト電極１が接触しケート電極の耐圧が減少するのを防ぐ
ために設けである。しかし、側壁を設けたことにより、
側壁下に高抵抗の領域が生じるため、ソース、トレイン
の寄生抵抗か十分低減されない。When manufacturing the above-mentioned GaAs MESFET, the high concentration impurity layer 4b is formed by selective growth using the gate electrode and the sidewalls made of an insulating material formed on the side surfaces of the gate electrode as masks. The side walls are provided to prevent the high concentration impurity layer 4b and the gate electrode 1 from coming into contact with each other and reducing the withstand voltage of the gate electrode. However, by providing side walls,
Since a high resistance region is generated under the sidewall, the parasitic resistance of the source and train cannot be sufficiently reduced.
また、高濃度不純物層４ｂの濃度を低くすると、ゲート
電極と高濃度不純物層が接触した場合のゲート耐圧の劣
化を防ぐことができ、側壁を用いずにＦＥＴを製作する
ことが可能となる。しかしながら、高濃度不純物層４ｂ
のシート抵抗が増加するため、この場合も寄生抵抗を十
分に低減することができなくなる。Further, by lowering the concentration of the high concentration impurity layer 4b, it is possible to prevent the gate breakdown voltage from deteriorating when the gate electrode and the high concentration impurity layer come into contact with each other, and it becomes possible to manufacture an FET without using sidewalls. However, the high concentration impurity layer 4b
Since the sheet resistance increases, the parasitic resistance cannot be sufficiently reduced in this case as well.
さらに、第４図に示ずように側壁下の領域の抵抗を低減
させるため、高濃度不純物層４ｂを形成する前にケート
電ｉ１のみをマスクとしてイオン注入を行ないＧａＡｓ
基板６に高濃度不純物層９を形成する方法がある。しが
しながら、このようにイオン注入を行った場合は短チヤ
ネル効果が顕著になり、短いゲート長のＦＥＴを製作す
る際に、しきい値電圧の制御が困難となる問題がある。Furthermore, as shown in FIG. 4, in order to reduce the resistance in the region under the sidewall, ions are implanted using only the gate electrode i1 as a mask before forming the high concentration impurity layer 4b.
There is a method of forming a high concentration impurity layer 9 on the substrate 6. However, when ion implantation is performed in this manner, the short channel effect becomes significant, and there is a problem in that it becomes difficult to control the threshold voltage when manufacturing an FET with a short gate length.
本発明の目的は、短チヤネル効果の増大を生しさせるこ
となくソース、ドレインの直列寄生抵抗を低減した電界
効果型半導体装置及びその製造方法を提供することにあ
る。SUMMARY OF THE INVENTION An object of the present invention is to provide a field effect semiconductor device and a method for manufacturing the same in which the series parasitic resistance of the source and drain is reduced without increasing the short channel effect.
第１の発明の電界効果型半導体装置は、半絶縁性半導体
基板に形成された一導電型半導体動作層と、前記半導体
動作層上に形成されたゲート電極と、前記ゲート電極の
側面に接して形成された一導電型低濃度不純物層と、前
記ゲート電極と所定間隔をおいて前記低濃度不純物層上
に設けられた一導電型高濃度不純物層とを含んで構成さ
れる。A field effect semiconductor device according to a first aspect of the invention includes a semiconductor active layer of one conductivity type formed on a semi-insulating semiconductor substrate, a gate electrode formed on the semiconductor active layer, and a semiconductor active layer in contact with a side surface of the gate electrode. The semiconductor device includes a low concentration impurity layer of one conductivity type and a high concentration impurity layer of one conductivity type provided on the low concentration impurity layer at a predetermined distance from the gate electrode.
第２の発明の電界効果型半導体装置の製造方法は、半絶
縁性半導体基板に一導電型半導体動作層を形成する工程
と、前記半導体動作層上にゲート電極を形成する工程と
、前記ゲート電極をマスクとし前記半導体動作層上のソ
ース・ドレイン領域に一導電型低濃度不純物層を形成す
る工程と、前記低濃度不純物層上でかつ前記ゲート電極
の側面に絶縁膜からなる側壁を形成する工程と、前記ケ
ート電極と側壁とをマスクとし前記低濃度不純物層上に
一導電型高濃度不純物層を形成する工程とを含んて構成
される。A method for manufacturing a field effect semiconductor device according to a second aspect of the invention includes the steps of: forming a semiconductor active layer of one conductivity type on a semi-insulating semiconductor substrate; forming a gate electrode on the semiconductor active layer; and forming a gate electrode on the semiconductor active layer. a step of forming a low concentration impurity layer of one conductivity type in the source/drain region on the semiconductor active layer using as a mask, and a step of forming a sidewall made of an insulating film on the low concentration impurity layer and on the side surface of the gate electrode. and forming a high concentration impurity layer of one conductivity type on the low concentration impurity layer using the gate electrode and the sidewall as a mask.
本発明は、ソース・トレインを低濃度不純物層＝５−
と高濃度不純物層からなる２つの選択成長層を用いて形
成する。二とにより、直列寄生抵抗の著しい低減を可能
とするものである。In the present invention, the source train is formed using two selectively grown layers consisting of a low concentration impurity layer (5-) and a high concentration impurity layer. 2, it is possible to significantly reduce the series parasitic resistance.
高濃度不純物層によりソース、トレイン領域の □シー
ト抵抗は低減され、また側壁下には、動作層のほか低濃
度不純物層が導入されているため、寄生抵抗の増加が従
来に比べ抑制される。特に、エンハンスメント型ＦＥＴ
においては、動作層の抵抗が大てあり、低濃度不純物層
導入による抵抗の低減効果は大きい。The high-concentration impurity layer reduces the sheet resistance of the source and train regions, and since a low-concentration impurity layer is introduced under the sidewalls in addition to the active layer, increases in parasitic resistance are suppressed compared to conventional devices. In particular, enhancement type FET
In this case, the resistance of the active layer is large, and the effect of reducing the resistance by introducing a low concentration impurity layer is large.
また、本発明ではソース・ドレインにイオン注入層を用
いていないため、短チヤネル効果の増大は生しない。Further, in the present invention, since no ion implantation layer is used for the source/drain, the short channel effect does not increase.
以下に、本発明の実施例について図面を参照して説明す
る。第１図（ａ）〜（ｄ）は本発明の一実施例を説明す
るために工程順に示した半導体チップの断面図である。Embodiments of the present invention will be described below with reference to the drawings. FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.
まず第１図（ａ）に示ずように、半絶縁性のＧ ａ Ａ
ｓ基板６上にＳｉイオンを５０ ｋ ｅ Ｖ 。First, as shown in FIG. 1(a), a semi-insulating G a A
Si ions are applied to the s-substrate 6 at 50 keV.
ドーズｊＬ２×１０１２ｃｍ−２の条件で選択的にイオ
ン注入し、ＣＶＤ Ｓ ｉ Ｏ２膜を保護膜として８
００°Ｃｌ２Ｏ分間の熱処理を行いＧ ａ Ａ ｓから
なる動作層３を形成した。次に保護膜を除去した後、ス
パッタ法を用いてタングステンシリサイド（ＷＳｌ）を
ＧａＡｓ動作層３及びＧａＡｓ基板６上全面に０．５μ
ｍの厚さに堆積した後、四フッ化炭素を用いたトライエ
ツチング法でＷＳｌを加工し、ゲート電極１を形成した
。Ions were selectively implanted at a dose of jL2 x 1012 cm-2, and a CVD SiO2 film was used as a protective film.
A heat treatment was performed for 00°CCl2O minutes to form an active layer 3 made of GaAs. Next, after removing the protective film, tungsten silicide (WSl) is applied to the entire surface of the GaAs active layer 3 and the GaAs substrate 6 to a thickness of 0.5 μm using a sputtering method.
After being deposited to a thickness of m, WSL was processed by a tri-etching method using carbon tetrafluoride to form a gate electrode 1.
次に、第１図（ｂ）に示すようにＧａＡｓ基板６の所定
部分にＳｉＯ□膜７を形成した後、ゲート電極１及び５
ｉ０２Ｊｌ（７をマスクとして、ソース・ドレイン領域
に不純物濃度が２ Ｘ １０１７ｃｍ−３である低濃度
不純物層４ａをＭＯＣＶＤ法を用い７００℃で膜厚０，
１５μｍ選択成長することにより形成した。Next, as shown in FIG. 1(b), after forming a SiO□ film 7 on a predetermined portion of the GaAs substrate 6, the gate electrodes 1 and 5
Using i02Jl (7) as a mask, a low concentration impurity layer 4a with an impurity concentration of 2 x 1017 cm-3 was formed in the source/drain region using the MOCVD method at 700°C with a film thickness of 0,
It was formed by selective growth of 15 μm.
次に５ｉ０２膜７を除去した後、第１図（ｃ）に示すよ
うに、ＣＶＤ法によりＳ ｉ ０２膜を全面に０．３μ
ｍの膜厚で被着した後、レジスト膜をマスクとしてＣＦ
４を用いた異方性エツチングでＳｉＯ２膜を加工し、ゲ
ート電極１の側面のみにＳｉＯ□膜５を残した。次にこ
のレジスト膜を除去した後、ゲート電極１ 、 Ｓ ｉ
０２膜５及び５ｉ０２膜８をマスクとして２×１０１
８ｃｍ−３のＳｉを含む高濃度不純物層をＭＯＣＶＤ法
て膜厚０．３μｍ！！択成長した。Next, after removing the 5i02 film 7, as shown in FIG.
After depositing a film with a thickness of m, CF was applied using the resist film as a mask.
The SiO 2 film was processed by anisotropic etching using 4, leaving the SiO□ film 5 only on the side surfaces of the gate electrode 1. Next, after removing this resist film, the gate electrode 1, Si
02 film 5 and 5i02 film 8 as a mask 2×101
A highly concentrated impurity layer containing 8cm-3 of Si was formed by MOCVD to a film thickness of 0.3μm! ! I grew up selectively.
最後に第１図（ｄ）に示すように、高濃度不純物層上に
ＡｕＧｅ系のソース、トレイン電極を形成し、ＰＥＴの
製作を完了した。Finally, as shown in FIG. 1(d), AuGe-based source and train electrodes were formed on the high concentration impurity layer, completing the fabrication of the PET.
上述のＦＥＴのほか、従来の第３図、第４図に示されて
いるＦＥＴも製作した。第３図のＦ Ｅ ’ｒでは高濃
度不純物層４ｂは濃度か２×１０１８ｃｍ−３膜厚０．
３μｍである。また、第４図のＦＥＴではイオン注入に
よる高濃度不純物層は５０ｋｅＶ。In addition to the above-mentioned FET, conventional FETs shown in FIGS. 3 and 4 were also manufactured. In F E'r of FIG. 3, the high concentration impurity layer 4b has a concentration of 2×10 18 cm −3 and a film thickness of 0.
It is 3 μm. Further, in the FET shown in FIG. 4, the high concentration impurity layer formed by ion implantation has a voltage of 50 keV.
７ Ｘ １０１２ｃｍ−２の条件で注入した後、ＳｉＮ
を保護膜として７５０℃、２０分の熱処理を行うことに
より形成した。After implantation under the conditions of 7 x 1012 cm-2, SiN
A protective film was formed by heat treatment at 750° C. for 20 minutes.
これらのＦＥＴを１００個づつ選び、相互コンダクタン
スｇｍとしきい値電圧Ｖ。のゲート長依存性を調べた結
果を第２図に示す。第２図より本実施例によるＦＥＴが
従来のＦＥＴに比べて短チヤネル効果を抑えつつ高いｇ
ｍを有していることが明らかになった。Select 100 of these FETs and calculate their mutual conductance gm and threshold voltage V. Figure 2 shows the results of investigating the gate length dependence of . Figure 2 shows that the FET according to this embodiment has a higher g while suppressing the short channel effect than the conventional FET.
It became clear that it has m.
上記の実施例では不純物層をＭＯＣＶＤ法を用いて選択
成長を行ったが、他にＬＰＥ、ＭＢＥ等の成長方法を用
いても本発明の趣旨を逸脱するものではない。In the above embodiment, the impurity layer was selectively grown using MOCVD, but other growth methods such as LPE and MBE may be used without departing from the spirit of the present invention.
以上説明したように本発明は、ソース・ドレインを低濃
度不純物層と高濃度不純物層の２種類の選択成長層を用
いて形成することにより短チヤネル効果を増大させずに
直列寄生抵抗の低減した電界効果型半導体装置か得られ
る。As explained above, the present invention reduces the series parasitic resistance without increasing the short channel effect by forming the source/drain using two types of selectively grown layers: a low concentration impurity layer and a high concentration impurity layer. A field effect semiconductor device can be obtained.
第１図（ａ）〜 （ｄ）は本発明の一実施例を説明する
ための工程順に示した半導体チップの断面図、第２図は
実施例と従来例のＦＥＴ特性を示した図、第３図及び第
４図は従来のＭＥＳＦＥＴの断面図である。
１・・・ゲート電極、２ａ・・・ソース電極、２ｂ・・
・ドレイン電極、３・・・動作層、４ａ・・・低濃度不
純物層、４ｂ・・・高濃度不純物層、５・・・５ｉＯｚ
膜、６・・・ＧａＡｓ基板、７，８・・・５ｉ０２膜、
９・・・高濃度不純物層。
鱈Ｚ図
ケ゛−戚、Ｉｇ）を沁1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in the order of steps to explain an embodiment of the present invention, FIG. 2 is a diagram showing FET characteristics of the embodiment and a conventional example, and FIG. 3 and 4 are cross-sectional views of conventional MESFETs. 1... Gate electrode, 2a... Source electrode, 2b...
- Drain electrode, 3... Operating layer, 4a... Low concentration impurity layer, 4b... High concentration impurity layer, 5... 5iOz
film, 6...GaAs substrate, 7,8...5i02 film,
9...High concentration impurity layer. Cod Z map (Ig)
Claims (2)
動作層と、前記半導体動作層上に形成されたゲート電極
と、前記ゲート電極の側面に接して形成された一導電型
低濃度不純物層と、前記ゲート電極と所定間隔をおいて
前記低濃度不純物層上に設けられた一導電型高濃度不純
物層とを含むことを特徴とする電界効果型半導体装置。(1) A semiconductor active layer of one conductivity type formed on a semi-insulating semiconductor substrate, a gate electrode formed on the semiconductor active layer, and a low concentration impurity of one conductivity type formed in contact with a side surface of the gate electrode. and a high concentration impurity layer of one conductivity type provided on the low concentration impurity layer at a predetermined distance from the gate electrode.
成する工程と、前記半導体動作層上にゲート電極を形成
する工程と、前記ゲート電極をマスクとし前記半導体動
作層上のソース・ドレイン領域に一導電型低濃度不純物
層を形成する工程と、前記低濃度不純物層上でかつ前記
ゲート電極の側面に絶縁膜からなる側壁を形成する工程
と、前記ゲート電極と側壁とをマスクとし前記低濃度不
純物層上に一導電型高濃度不純物層を形成する工程とを
含むことを特徴とする電界効果型半導体装置の製造方法
。(2) A step of forming a semiconductor active layer of one conductivity type on a semi-insulating semiconductor substrate, a step of forming a gate electrode on the semiconductor active layer, and a step of forming a source/drain layer on the semiconductor active layer using the gate electrode as a mask. forming a low concentration impurity layer of one conductivity type in the region, forming a side wall made of an insulating film on the low concentration impurity layer and on the side surface of the gate electrode, and using the gate electrode and the side wall as a mask. A method for manufacturing a field effect semiconductor device, comprising the step of forming a high concentration impurity layer of one conductivity type on the low concentration impurity layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62117824A JPH081910B2 (en) | 1987-05-13 | 1987-05-13 | Field effect type semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62117824A JPH081910B2 (en) | 1987-05-13 | 1987-05-13 | Field effect type semiconductor device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63281473A true JPS63281473A (en) | 1988-11-17 |
| JPH081910B2 JPH081910B2 (en) | 1996-01-10 |
Family
ID=14721156
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62117824A Expired - Lifetime JPH081910B2 (en) | 1987-05-13 | 1987-05-13 | Field effect type semiconductor device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH081910B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS642370A (en) * | 1987-06-24 | 1989-01-06 | Nec Corp | Field-effect type semiconductor device and manufacture thereof |
| JPH05326561A (en) * | 1992-05-22 | 1993-12-10 | Nec Corp | Manufacture of field effect transistor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59207669A (en) * | 1983-05-10 | 1984-11-24 | Mitsubishi Electric Corp | Manufacture of field effect transistor |
| JPS60165764A (en) * | 1984-02-08 | 1985-08-28 | Nec Corp | Manufacture of compound semiconductor device |
-
1987
- 1987-05-13 JP JP62117824A patent/JPH081910B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59207669A (en) * | 1983-05-10 | 1984-11-24 | Mitsubishi Electric Corp | Manufacture of field effect transistor |
| JPS60165764A (en) * | 1984-02-08 | 1985-08-28 | Nec Corp | Manufacture of compound semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS642370A (en) * | 1987-06-24 | 1989-01-06 | Nec Corp | Field-effect type semiconductor device and manufacture thereof |
| JPH05326561A (en) * | 1992-05-22 | 1993-12-10 | Nec Corp | Manufacture of field effect transistor |
| US5298445A (en) * | 1992-05-22 | 1994-03-29 | Nec Corporation | Method for fabricating a field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH081910B2 (en) | 1996-01-10 |
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