JPS60116178A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To accurately perform the recess of an E-mode FET element and D- mode FET element and the formation of gate electrodes in the same steps by providing the gate electrodes of the E-mode FET element on an electron supply layer. CONSTITUTION:A polygonal line E is E-mode, a polygonal line D is D-mode in the state of the gate electrode forming region. There is large etching speed difference between GaAs and AlGaAs, at the time when the D-mode side etching arrives at AlGaAs electron supply layer 12, the etching is advanced in the layer 12 in the depth substantially equal to the thickness of an AlGaAs semiconductor layer 14 at the E-mode side, and the following main etchings are advanced at the depth of this difference at the equal velocity in both regions. When the thickness of the layer 14 is grown equally to the difference of the distance intended between the gate electrode and the channel layer of both mode, thereby simultaneously completing the recess formation of the E mode and D-mode by itself.

Description

Detailed description of the invention (a) Technical field of the invention Great invention The present invention relates to a semiconductor device that can be implemented with precision and a method for manufacturing the same.

(b) Background of the Technology Aiming to further improve the performance of electronic dividers and the like, efforts are being made to increase the speed and reduce power consumption of semi-coupled devices. For this purpose, gallium arsenide (QaA) has significantly higher carrier mobility than silicon (Sl), which is currently the mainstream.
Many transistors using compound semiconductors such as s) have been proposed. Field-effect transistors (hereinafter abbreviated as FETs) are currently the mainstream transistors using compound semiconductors because their manufacturing process is 101 times simpler than that of bihole transistors.5.
``Nyottokey barrier type in the office''-' ET is often used.

These conventional I ('LIλ1゛j Si or Ga
In a semiconductor device made of Ag or the like, carriers move within a semiconductor space due to the presence of impurity ions. During this movement, carriers are scattered by lattice vibrations WJ+ and impurity ions, but if the temperature is lowered to reduce the probability of scattering due to lattice vibrations, the probability of scattering by impurity ions increases, and carrier mobility decreases. limited by this.

In order to eliminate this impurity scattering effect, the region where impurities are added and the region where carriers move are spatially separated by a heterojunction interface, and the heterojunction electric field increases the mobility of carriers, especially at low temperatures. Even higher speeds have been realized by effect transistors (hereinafter abbreviated as heterojunction FETs).

(c) Prior Art and Problems An example of a conventional structure of an inverter constructed from heterojunction FETs is shown in FIG. 1(a). Region E in FIG. 1(a) is an enhancement mode (hereinafter abbreviated as E mode) FET element, and region E is a degreen mode (hereinafter abbreviated as D mode) FET element. The equivalent circuit shown in (b) is an E-mode FETTr1 which is a driver of an inverter circuit, and a D-mode FETTr2 which is a load element.

Each element of the heterojunction FET is made of semi-insulating GaAs substrate 1.
On top, undoped GaAs #2, an n-type aluminum gallium arsenide (A71GaAs) layer 3 having a smaller electron affinity and containing donor impurities, and nWGaAgli
44 is provided, and a part of the n-type GaAstN4 and n-type AnGaAs layer 3 is selectively removed to form an n-type A
A gate electrode 4 is provided in contact with the #GaAaNIi3, a source and drain electrode 6 is provided on the GaAsJ@4, and an insulation layer II1. A wiring 8 is formed via Y7.

Two-dimensional 1) L-son gas 2A generated near the heterojunction interface between both layers by electrons transferred from n-type AnGaAs I layer 3 (referred to as electron supply layer) to non-doped aaAs layer 2 (referred to as channel Ikuyoshi) serves as a channel, and by controlling its electron concentration with the voltage applied to the gate electrode, the impedance between the source electrode and the drain electrode is controlled.

Although the heterostructure having the structure as explained above can be controlled by the impurity level and thickness of the semiconductor layer interposed between the trapezoidal channel layer 2, the gate threshold voltage vth is different for the same semiconductor substrate. When an FET element is provided, a recess structure is used in which the semiconductor layer is selectively etched to control the thickness.

Figure 1(e) shows an n-type A heterojunction FET with the above structure.
l! FIG. 3 is a diagram showing an example of the correlation between the film thickness of GaAs J3 and the gate threshold voltage vth. The ideal value of the gate voltage in E mode is vth=o(v), and in the example of FIG. 1(c), the thickness of this gate electrode region of the n-type AA'GaAs layer 3 is t. Medium: 42.5 (nm) The thickness of this gate electrode region of the AlGaAs substrate 3 is assumed to be tl-=46.5 (nm).

In general semiconductor device manufacturing processes, dry etching is being adopted as an etching method suitable for improving pattern accuracy and streamlining the process. It is complicated and difficult to perform etching with different depths while precisely controlling the respective depths. That is, etching for recess formation and usually gate electrode formation are performed independently for E-mode FET devices and D-mode FET devices.
It is necessary to repeat the process several times. Furthermore, for either E mode or D mode FET element, for example, A
Ga using the IGaAa electron supply layer 3 as an etching stop layer
Even if the recess is formed without much difficulty by selectively etching the As layer 4, control 1 is required to stop the etching at the midpoint of the semiconductor I for the remaining FET elements of the other mode. .

In order to properly stop the etching of recess formation, a method of monitoring the current between the source and drain electrodes has often been used.

This monochrome measurement is complicated, as it is necessary to take the half substrate out of the etching apparatus, and repeating this process significantly reduces productivity.

As explained above, the initial value of the gate threshold voltage vth is a complex process and therefore tends to cause problems in ensuring accuracy.
There is a need for a structure and a manufacturing method that can easily and clearly control the process.

(d) Object of the Invention The present invention relates to a semiconductor device in which heterojunction FETs are integrated, and the recess and gate electrode formation of an E-mode F'ET element and a D-mode FET element of the semiconductor device are accurately performed in the same process. It is an object of the present invention to provide a structure of a semiconductor device and a method for manufacturing the same.

(e) Structure of the Invention The object of the present invention is to provide a semi-insulating compound semiconductor substrate with
A first semiconductor channel layer in which a two-dimensional electron gas is generated, an electron supply layer made of a second compound semiconductor, a third semiconductor layer made of a third compound semiconductor, and a third semiconductor layer made of the second compound semiconductor. a fourth semiconductor layer, the gate electrode of the depletion mode transistor element is in contact with the electron supply layer, and at a position deeper than the gate electrode by a value approximately equal to the thickness of the fourth semiconductor layer. , the foot pole of the enhancement mode transistor element is achieved by the semiconductor device provided in contact with the layer d.

In the semiconductor device having the above structure, 1 is such that at least two-dimensional electron gas is generated on the semi-insulating compound semiconductor substrate)
7. a first semiconductor channel layer made of a second compound semiconductor, an electron supply layer made of a second compound semiconductor, a third semiconductor layer made of a third compound semiconductor, and a fourth semiconductor layer made of the second compound semiconductor. The fourth semiconductor layer is removed from the surface of the semiconductor growth layer in the gate electrode formation region of the enhancement mode transistor element, and then the enhancement mode transistor element is grown.
A region for forming a gate electrode of a transistor element in a depletion mode is opened, and an etching process is performed on the four parts in which the etching rate for the second compound semiconductor is lower than the etching rate for the compound semiconductor in the front a12 beam 3, thereby forming a transistor in a depletion mode. In the gate electrode formation region of the device? f, ;:f supply layer is exposed and reaches inside the electron supply layer by a value approximately equal to the thickness of the fourth semiconductor layer in the gate electrode formation region of the enhancement mode transistor element, and simultaneously performs the etching process. The above object is achieved by a method of manufacturing a semiconductor device.

(f) Embodiments of the invention The structure of the invention described above is G a A s /A 1! Ga
An example of an As-based heterojunction FET will be explained. In this embodiment, as shown in FIG. 2(a), the semiconductor substrate, the first semiconductor channel layer (the above are not shown),
, the third semiconductor layer 13 and the fifth semiconductor layer 215 other than the above are made of GaAs, and the electron supply layer 1 and the fourth semiconductor layer 14 are made of A/xGaI-xAs, for example,
-03, and the thickness of the semiconductor layer 14 of m4 is made equal to the intended difference in distance between the gate electrode and the channel layer in E mode and D mode.

Further, as the etching process, for example, an active ion etching (hereinafter abbreviated as RIE) method using carbon dichloride difluoride ('CC72Fs) as an etchant is employed. In this RIE method using CC7?2Ft, the etching rate is 500 to 600 (
nm/mJ, AIGaAsKJj and 3 (r++m/
This shows an extremely large difference of the order of mj+E.

In the present invention, first, the fourth AlGaAs semiconductor layer 14 is selectively removed in the E-mode gate electrode formation region of the semiconductor substrate. This etching method is arbitrary, and the third GaAs semiconductor layer 13 may also be etched.

After that, the E-mode and D-mode gate electrode formation regions are processed using the RIE method using CCJ2F2, for example.
The recess is formed using an etching method that has different etching rates for GaAs and AlGaAs. When is the etching depth in this etching process?
An example of 111'l'JIII-r is shown in FIG. 2(b).

However, in the figure, the broken line E shows the state of the gate electrode formation region in E mode, and the broken line shows the state of the gate electrode formation region in D mode.
Since there is a large difference in etching speed between aAs and AlGaAs, at the time when the etching on the D mode side reaches the AAGaAs electron supply layer 12, the etching depth on the E mode side is approximately equal to the thickness of the fourth AlGaAs semiconductor layer 14. Etching has progressed only a little into AA'GaAgA4GaAs 12, and the subsequent main etching progresses at the same speed in both head regions while maintaining this difference in depth. As mentioned above, by growing the fourth AJGaAs semiconductor layer 14 to a thickness equal to the intended distance difference between the gate electrode and the channel layer for both modes, E mode and D mode can be separated. Recess formation is completed on its own at the same time.

Hereinafter, embodiments of the present invention will be explained in more detail with reference to step-by-step cross-sectional views of FIGS. 3(a) to (3).

Refer to FIG. 3(a) A non-doped GaAs channel layer 1 is formed on a semi-insulating GaAs substrate lO by a molecular beam epitaxial growth method or the like.
1 Total 11 For example, n-type AIIxGal-xAs electron supply No. 12 doped with silicon (St) to about 1 to 2 × 10 per i-3], for example, about 01 to 03 [μm].
Let x = 0.3, and set the thickness to the distance between the gate electrode and channel layer of the D-mode FET element plus the overetching during recess formation etching, and further set St to 1 to 2X10'δ. An n-type GaAs layer 13 doped to about [I-3] is grown to a thickness of, for example, about 1'00 (nm). Each of the above layers is not particularly different from the conventional one, but in this example 11I, AlxGa 5-x
The As layer 14 is supplied with electrons and has the same composition, and its thickness is the gate N41tt for E mode and D mode, and the channel layer 11.
The growth is performed with the intended value of the distance difference between the two layers, for example 4 [nm:], and the growth is performed using GaAs N 15 as a surface capture layer. This cinnabar protective layer has the effect of preventing the thickness of the A/xGa1-xAsJ scratch 14 from changing due to wafer surface treatment or the like. Note that these semiconductors 11
Although 14 and 15 are n-type in this embodiment, they may be non-doped. In addition, a two-dimensional electron gas IIA is generated near the interface between the channel layer 11 of the semiconductor substrate and the electron supply layer 12. See FIG. 3(b). Isolation between elements is performed by a method such as mesa-type etching.

Referring to FIG. 3(c), in the region where the gate electrode of the E-mode FET element is formed, as shown as 18 (GaAs layer 15 and A4GaAs layer 15 and A4GaAs layer 15 and
As, 14 is removed by etching. Any method may be applied to this etching method, and n-type GaAs
There is no problem even if the layer 13 is slightly etched.

Refer to FIG. 3(d). The surface of the semiconductor substrate is, for example, made of silicon dioxide (SiO2).
), and selectively provide openings in the source and drain/ohmic contact electrode formation regions by phosphorography, for example, gold/germanium/gold (
The ohmic contact electrode 20 is provided by depositing a metal such as AuGe/Au (AuGe/Au) and lifting it on. Note that in this embodiment, the GaAs layer 15 and the Ae
GaAg J@14K also has an aperture, but this is not necessary.

Referring to FIG. 3(e), a resist film 21 is usually provided using a positive resist, and a gate pattern 22 of an E-mode FET and a gate pattern 23 of a D-mode FET are formed by phosphorography. This portion of the 5iO1 film 19 is then etched using, for example, hydrofluoric acid (HF) to give it a shape as shown as a spacer 24 suitable for lift-off to form a gate electrode.

Then, as mentioned above, for example, R by CCA2F2
Recesses 25 in both gate formation regions are formed by IE method.

In this embodiment, the thickness of the n-type AlGaAs electron supply layer 12 is set as described above with reference to the D-mode FET element, and the etching is terminated when the predetermined etching time has elapsed.

As a result, the thickness of the gate electrode formation region of the AJGaAsit electron supply layer 12 becomes the intended value for both the D mode and the E mode.

Refer to FIG. 3(f). For example, by depositing titanium/platinum/gold (Ti/Pt/Au) or aluminum (A7) and lifting it off, the gate electrode 26 and D
The gate electrode 27 of the mode F E 'I' element is formed at the same time.

FIG. 3 (〃) A reference interlayer insulating layer 28 is deposited with K such as SiO2, an opening is formed in this layer and a wiring 29 is arranged, so that the E-mode doorway junction FET according to the present invention is used as a driver.
An inverter using a D-mode heterojunction FET as a load element is completed.

In the above embodiments, the semiconductor substrate is made of GaAs/AJGaAs.
Although the structure of the semiconductor substrate and the etchant used in the RIE method for forming the recess are CC/2F2, the structure of the semiconductor substrate, the etchant, etc. can be selected as necessary.

(g) As described in detail, according to the present invention, when E-mode and D-mode elements of a heterojunction FET having different gate threshold voltages are formed on the same semiconductor substrate, the recess that governs the gate threshold voltage is It is possible to perform the formation and subsequent gate electrode formation for both modes of devices in the same process, and the gate threshold voltage can be easily controlled with high precision.
For example, it will be possible to provide integrated circuit devices including inverter circuits, which are one of the most basic configurations in electronic circuits, with excellent productivity.

[Brief explanation of drawings]

FIG. 1(a) is a cross-sectional view showing a conventional example of an inverter configured with a heterojunction FET, FIG. 1(b) is its equivalent circuit diagram, and FIG. FIG. 2(a) is a diagram showing an example of the structure of the semiconductor layer according to the present invention, and FIG. Diagram showing the progress of etching depth, Figure 3 (a, l to (I)
) is a sectional view taken at step +11ffl of an inverter to which the present invention is applied. In the figure, a 10-digit semi-insulating GaAs substrate, 11°13
and 15 is GaAs1t'X, 12 and 14 are AA
'GaAs layer, 19 and 28 are insulating layers, 20 is an ohmic contact electrode, 251t:' recess, 26 and 27 are gate electrodes, and 29 is a wiring. $ j Figure (1)) YD. °2 °7 ・E) 'l', +7”l Aa 4 g
'Ties 寥2 Ward I (a) (Riera now〉7゛mark withdrawal period σ8 3rd hundred (α) 3rd same procedure amendment Furuyamatsu. Akira (Kashi in January 1'1 59.1'2.11 Patent Director-General of the Agency Showa Js'8'il-↑'cj'1 Sir No. λ21/-6
rD No. 3 Complementary Old "Sekiba with I + 11 ・11□,'l'il 冑 臥 1] Place God', 1 Ko 1.1 Kawasaki City 1 yen +: il/11N Chugoku 015 city area (522)?, l)' Hatake 1°dori Co., Ltd. 4
Agent II Moe IIP1N" 111. A semi-insulating compound semiconductor substrate is provided with a semiconductor channel layer on which a two-dimensional electron gas is generated, and a gate electrode of a depletion mode transistor element is located on the electron supply layer; The gate electrode of the enhancement mode transistor element is provided on the multilayer layer 1 at a position deeper than the gate electrode by a value corresponding to the thickness of the second semiconductor layer. (2) At least two semiconductor devices on a semi-insulating compound semiconductor substrate.
a second semiconductor layer made of a semiconductor channel material in which dimensional electron gas is generated, and removing the second semiconductor layer from the surface of the semiconductor growth layer at a pressure in a gate electrode formation region of an enhancement mode transistor element; In addition, in the gate electrode formation regions of enhancement mode and depletion mode transistor elements, a recess etching process [TII] is performed at the same time in which the etching rate for the electron supply layer is lower than the etching rate for the first semiconductor layer, A method for manufacturing a semiconductor device, characterized in that the etching process [IIj] is simultaneously terminated at the H-type gate of an enhancement mode transistor element. (2) Specification, page 8, No. 13
The lines to page 10, line 6 are amended as follows. ``The object of the present invention is to provide a semi-r!Pf compound semiconductor substrate with a semiconductor channel layer in which a two-dimensional particle gas is generated, an electron supply layer formed thereon, and a nuclear bomb. a first semiconductor layer formed on the supply layer and made of a different semiconductor material; and a second semiconductor layer formed on the first semiconductor layer and made of a different semiconductor material. When the gate electrode of the enhancement mode transistor element is located on the electron supply layer and at a position pressure deeper than the gate electrode by a value corresponding to the thickness of the second semiconductor layer, the gate electrode of the enhancement mode transistor element is located on the electron supply layer. This is achieved by a semiconductor device characterized in that it is located on a supply layer.In the semiconductor device having the above structure, at least two-dimensional electron gas is generated on the semi-insulating compound semiconductor substrate. a semiconductor channel layer, an electron supply layer forming a heterojunction therewith, a first semiconductor layer made of a semiconductor material different from the electron supply layer, and a second semiconductor layer made of a semiconductor material different from the first semiconductor layer. (removal of the second semiconductor layer from the surface of the semiconductor growth R in the electrode formation region);
Thereafter, the electrons (the etching rate with respect to the Ji supply layer is the first semiconductor) are formed in the gate electrode formation regions of the enhancement mode and depletion mode transistor elements. At the same time, a recess etching process is performed at a rate lower than the etching rate for 4, and the depth of the recess is equal to the thickness of the second semiconductor layer in the enhancement mode σ) in the gate electrode formation region of the transistor element. Deeper than the depletion mode, when the inside of the child supply layer (FJ), the process 1. (3) Specification of the present application Tomoki 10 Teikoku 8.
The lines to page 12, line 11 are corrected as follows. "G a, A s /A lj
G a As heterozygous F' E 'I'
Please explain as an example. In this example, Fig. 2(a)
As shown in lc, a semiconductor substrate of All 'jjE:, a semiconductor channel layer (not shown above), a semiconductor t of N<1
+* 13 and the third semiconductor layer 15 (σ)
For example, by aAs, the electron supply layer J2 and the semiconductor layer 14 are formed by AAxGa+ -xAs K, for example,
-03, and the original ζ of the second semiconductor layer 14 is made equal to the intended difference in distance between the gate electrode and the channel layer in E mode and D mode. Further, as the etching treatment, an active ion etching (hereinafter abbreviated as RIE) method using, for example, carbon dichloride difluoride (CC12Fl) as an etching agent is employed. In this RIE method using CCl 2 Ft, the etching rate is 500 to 600 (n) for GaAsK.
m/mff1), 3(r++n/
The analysis shows a large difference, about 1iH). In the present invention, first, in the E-mode gate m nucleation region of the semiconductor substrate, a second AIG a As
The semiconductor layer 14 is selectively removed. This etching method is arbitrary, and the first GaAs semiconductor layer 13 may be etched. Thereafter, recess formation is performed for the rE mode and D mode gate electrode formation regions using an etching process [τ] in which the etching speeds of GaAs and AlGaAs are different, such as the RIE method using CCl x F t. This etching place 1! An example of the time course of the etching depth at IjK is shown in FIG. 2(b). In the Kodashi diagram, fold FEE is in E mode, and fold line is in D mode.
The state of the gate electrode formation region in the AAGaAs electron supply layer 1 is shown below, and as mentioned above, there is a large difference in etching speed between GaAs and AlGaAs.
At the time when the D mode 1 lil etching reaches the 2nd layer, the E mode side is the 2nd Q) AlGaAs semiconductor layer 1.
Etching has progressed in the AlGaAs electron supply layer 12 by a depth approximately equal to the thickness of No. 4, and the subsequent main etching progresses at the same speed in both regions while maintaining this difference in depth σ. To the second A A G a A s half; As mentioned above, the gate f
By growing equal to the intended distance difference between the f1f pole and the channel 1, the recess formation in the E mode and the 1) mode is automatically completed simultaneously. ”

Claims (2)

[Claims] (1) A first semiconductor channel layer in which a two-dimensional electron gas is generated, an electron supply If1 made of a second compound semiconductor, and a third layer made of a third compound semiconductor on a semi-insulating compound semiconductor substrate. A gate electrode 75 of the debrillation mode transistor element is provided with a semiconductor layer and a fourth semiconductor scrap made of the second compound semiconductor, and is in contact with the electron supply layer, and is connected to the fourth semiconductor chip from the gate electrode. semiconductor 1
1. The thickness of the publication is so old. At a position deep by n value,
1. A semiconductor device characterized in that a gate electrode of an enhancement mode transistor element is in contact with J- and J-C. (2) An electron supply layer 1 consisting of at least a first semiconductor channel layer in which a two-dimensional electron gas is generated and a second compound semiconductor on a semi-insulating 118I compound semiconductor substrate.
A fourth semiconductor layer of 17 is sequentially grown from the second compound semiconductor to form an enhancement mode transistor. removing the fourth semiconductor layer from the surface of the semicircular growth layer in the gate electrode formation region of the element, and then etching the second compound semiconductor in the gate electrode formation region of the enhancement mode and degree mode transistor elements; A recess etching process whose speed is lower than the etching speed for the third compound semiconductor is simultaneously performed to expose the electron supply 1- in the gate electrode formation region of the degree mode transistor element, and to expose the electron supply 1- to the gate electrode formation region of the enhancement mode transistor element. In the electrode formation region, a value equal to the thickness of the fourth semiconductor layer reaches inside the electron supply layer, and the etching process is completed.
A method for producing a semiconductor device characterized by IK termination.