JP3189291B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3189291B2 JP3189291B2 JP10200291A JP10200291A JP3189291B2 JP 3189291 B2 JP3189291 B2 JP 3189291B2 JP 10200291 A JP10200291 A JP 10200291A JP 10200291 A JP10200291 A JP 10200291A JP 3189291 B2 JP3189291 B2 JP 3189291B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- plasma irradiation
- active region
- gaas substrate
- semi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000000034 method Methods 0.000 title claims description 9
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 16
- 230000001681 protective effect Effects 0.000 claims description 10
- 230000000415 inactivating effect Effects 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 229910052737 gold Inorganic materials 0.000 description 6
- 239000010410 layer Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 229910020286 SiOxNy Inorganic materials 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 150000001247 metal acetylides Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
- Formation Of Insulating Films (AREA)
- Hall/Mr Elements (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の製造方
法、特に電界効果トランジスタおよびホール素子などの
製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a field effect transistor and a Hall element.
【０００２】[0002]
【従来の技術】図６から図９は、従来法による電界効果
トランジスタ（ＦＥＴ）の工程別断面図である。2. Description of the Related Art FIGS. 6 to 9 are cross-sectional views of a conventional field effect transistor (FET) in different steps.
【０００３】まず、エピタキシャル成長により、活性領
域１１を形成した半絶縁性ＧａＡｓ基板１２にメサエッ
チングを行ない、台形状のチップを形成する（図６）。First, a semi-insulating GaAs substrate 12 having an active region 11 formed thereon is subjected to mesa etching by epitaxial growth to form a trapezoidal chip (FIG. 6).
【０００４】次に、一般に知られるフォトリソ工程を用
いて、Ａｕ：Ｇｅ，Ｎｉ，Ａｕなどからなるソース電極
１３およびドレイン電極１４を形成する（図７）。Next, a source electrode 13 and a drain electrode 14 made of Au: Ge, Ni, Au or the like are formed by using a generally known photolithography process (FIG. 7).
【０００５】その後、再度フォトリソ工程を用いて、ソ
ース電極１３およびドレイン電極１４の中央の、リセス
エッチングされた所定の位置に、Ｔｉ，Ｐｔ，Ａｕなど
からなるゲート電極１５を形成する（図８）。Thereafter, a gate electrode 15 made of Ti, Pt, Au, or the like is formed at a predetermined recess-etched position at the center of the source electrode 13 and the drain electrode 14 by using the photolithography process again (FIG. 8). .
【０００６】最後に、ＰＥＣＶＤ，光ＣＶＤ，ＥＣＲＣ
ＶＤなどを用いて、ＳｉＮｘ膜，ＳｉＯｘＮｙ膜などの
保護膜１７を形成する（図９）。Finally, PECVD, optical CVD, ECRC
A protection film 17 such as a SiNx film or a SiOxNy film is formed using VD or the like (FIG. 9).
【０００７】[0007]
【発明が解決しようとする課題】上記の従来法において
は、半絶縁性ＧａＡｓ基板の表面に炭化物や酸化物など
が残留することによりＧａＡｓ基板表面が汚染・酸化さ
れてしまい、半導体装置の特性劣化の原因となってい
る。また、上記の従来法においては、半絶縁性ＧａＡｓ
基板表面に多量の表面準位が発生しており、この表面準
位は保護膜を形成することで、ある程度軽減するが、依
然多量の準位が存在する。この多量の表面準位により、
半導体装置の高周波領域での電気的特性は、大きな影響
を受け、ひいては素子信頼性、素子特性の劣化を生じさ
せる。上記のような問題点を解消するため、保護膜を形
成する前の工程において、水素プラズマ照射を行なう方
法が、一部で提案されている。しかし、この方法による
と水素成分が保護膜中に入り、耐湿特性の劣化原因とな
り、また保護膜と半絶縁性ＧａＡｓ基板との界面に水素
成分が残留するため、この界面より水分が侵入するとい
う問題がある。In the above-described conventional method, carbides and oxides remain on the surface of the semi-insulating GaAs substrate, thereby contaminating and oxidizing the surface of the GaAs substrate, thereby deteriorating the characteristics of the semiconductor device. Is the cause. Further, in the above conventional method, semi-insulating GaAs is used.
A large number of surface levels are generated on the substrate surface. These surface levels are reduced to some extent by forming a protective film, but a large number of levels still exist. Due to this large number of surface states,
Electrical characteristics of a semiconductor device in a high-frequency region are greatly affected, which causes deterioration of element reliability and element characteristics. In order to solve the above-mentioned problems, some methods of performing hydrogen plasma irradiation in a process before forming a protective film have been proposed. However, according to this method, a hydrogen component enters the protective film and causes deterioration of the moisture resistance, and a hydrogen component remains at the interface between the protective film and the semi-insulating GaAs substrate. There's a problem.
【０００８】[0008]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、活性領域が形成された半絶縁性ＧａＡｓ基板
に、所定の電極を形成する工程と、プラズマ照射を行な
い、前記活性領域の表面を清浄化かつ不活性化するプラ
ズマ照射工程と、保護膜を形成する工程とを含む半導体
装置の製造方法において、前記プラズマ照射工程におい
て、Ｎ2プラズマ照射のみを行なうことを特徴とする。According to a method of manufacturing a semiconductor device of the present invention, a step of forming a predetermined electrode on a semi-insulating GaAs substrate on which an active region is formed, and performing plasma irradiation.
To clean and inactivate the surface of the active region.
A Zuma irradiation step, in a method of manufacturing a semiconductor device and forming a protective film, in the plasma irradiation step, characterized in that it rows only N 2 plasma irradiation.
【０００９】[0009]
【作用】本発明の半導体装置の製造方法によれば、半絶
縁性ＧａＡｓ基板を、Ｎ2プラズマ照射にて表面処理を
行なうことにより、表面に存在する汚染層，酸化層を除
去することができ、しかも表面準位を低減し、フェルミ
準位のピニングを解消するなど、表面層を不活性化する
ことができる。また本発明によれば、Ｎ2プラズマ照射
後、半絶縁性ＧａＡｓ基板表面にＮ2成分が残存してい
るが、ＧａＡｓ基板と保護膜の界面の耐湿性を悪化させ
ない。According to the method of manufacturing a semiconductor device of the present invention, a semi-insulating GaAs substrate is subjected to surface treatment by irradiating N 2 plasma, thereby removing a contaminant layer and an oxide layer present on the surface. In addition, the surface layer can be inactivated by reducing the surface level and eliminating pinning of the Fermi level. According to the present invention, the N 2 component remains on the surface of the semi-insulating GaAs substrate after the N 2 plasma irradiation, but does not deteriorate the moisture resistance at the interface between the GaAs substrate and the protective film.
【００１０】[0010]
【実施例】図１から図５は、本発明の一実施例を示す工
程別断面図である。以下これらの図を参照しつつ、本発
明の一実施例を詳述する。1 to 5 are sectional views showing steps of an embodiment of the present invention. Hereinafter, an embodiment of the present invention will be described in detail with reference to these drawings.
【００１１】まず、エピタキシャル成長により、活性領
域１を形成した半絶縁性ＧａＡｓ基板２にメサエッチン
グを行ない、台形状のチップを形成する（図１）。First, mesa etching is performed on the semi-insulating GaAs substrate 2 on which the active region 1 is formed by epitaxial growth to form a trapezoidal chip (FIG. 1).
【００１２】この上に、フォトレジストをスピンコート
し、ソース・ドレイン電極作製用フォトマスクを用いて
露光することで、ソース・ドレイン電極形成領域上のフ
ォトレジストを現像する。さらに、この上にＡｕ：Ｇ
ｅ，Ｎｉ，Ａｕを順次電子ビーム蒸着し、フォトレジス
ト上の不要なＡｕ：Ｇｅ，Ｎｉ，Ａｕをフォトレジスト
からリフトオフすることで、ソース電極３およびドレイ
ン電極４を形成する（図２）。A photoresist is spin-coated thereon and exposed using a photomask for forming source / drain electrodes, thereby developing the photoresist on the source / drain electrode formation region. In addition, Au: G
e, Ni, and Au are sequentially deposited by electron beam evaporation, and unnecessary Au: Ge, Ni, and Au on the photoresist are lifted off from the photoresist to form the source electrode 3 and the drain electrode 4 (FIG. 2).
【００１３】次に、再度フォトレジストをスピンコート
し、ゲート電極作製用フォトマスクを用いて露光するこ
とで、ゲート電極形成領域上のフォトレジストを現像す
る。その後リセスエッチングを行ない、ソース・ドレイ
ン間の電流量を調整する。次にＴｉ，Ｐｔ，Ａｕを順次
蒸着し、フォトレジスト上の不要なＴｉ，Ｐｔ，Ａｕを
フォトレジストからリフトオフすることで、ソース電極
３およびドレイン電極４の中央に、ゲート電極５を形成
する（図３）。Next, the photoresist on the gate electrode formation region is developed by spin-coating the photoresist again and exposing it using a photomask for forming a gate electrode. Thereafter, recess etching is performed to adjust the amount of current between the source and the drain. Next, Ti, Pt, and Au are sequentially deposited, and unnecessary Ti, Pt, and Au on the photoresist are lifted off from the photoresist to form a gate electrode 5 at the center of the source electrode 3 and the drain electrode 4 ( (Fig. 3).
【００１４】次に、Ｎ2プラズマ照射を行ない、活性領
域１の表面に清浄化・不活性化領域６を形成する（図
４）。このときのＮ2プラズマ照射条件の一例を以下に
示す。 Next, N 2 plasma irradiation is performed to form a cleaning / inactivating region 6 on the surface of the active region 1 (FIG. 4). An example of the N 2 plasma irradiation conditions at this time is shown below.
【００１５】このＮ2プラズマ照射の直後に、ＳｉＮｘ
膜などの保護膜７をＰＥＣＶＤ・光ＣＶＤ・ＥＣＲＣＶ
Ｄなどを用いて形成する（図５）。この保護膜７の形成
は、活性領域１の表面に形成された清浄化・不活性化領
域６が大気にさらされ、汚染されないよう真空中で行な
う。Immediately after the N 2 plasma irradiation, SiNx
PECVD, photo-CVD, ECRCV
D and the like (FIG. 5). The protection film 7 is formed in a vacuum so that the cleaning / inactivating region 6 formed on the surface of the active region 1 is not exposed to the atmosphere and is not contaminated.
【００１６】本発明の一実施例として、メサエッチング
を用いたＦＥＴの場合について述べたが、本発明はこれ
に限定されるものではなく、選択的イオン注入により、
活性領域を形成したＦＥＴにも適用が可能であり、また
ホール素子にもＦＥＴと同様、エピタキシャル成長によ
り活性領域を形成した場合および選択的イオン注入によ
り活性領域を形成した場合などに適用が可能である。As an embodiment of the present invention, the case of an FET using mesa etching has been described. However, the present invention is not limited to this.
The present invention is also applicable to a FET having an active region formed thereon, and is also applicable to a Hall element, similarly to the FET, when an active region is formed by epitaxial growth and when an active region is formed by selective ion implantation. .
【００１７】[0017]
【発明の効果】本発明の半導体装置の製造方法によれ
ば、半絶縁性ＧａＡｓ基板表面に存在する汚染層・酸化
層を除去することができ特性劣化を極力抑えることがで
きる。しかもＮ2プラズマの照射により、ＧａＡｓ基板
の表面層を不活性化することができ、半導体装置の電気
的特性が著しく向上する。このとき、窒素原子がＧａＡ
ｓ基板表面に存在しているが、水素原子のように耐湿特
性を悪化させない。According to the method of manufacturing a semiconductor device of the present invention, a contamination layer and an oxide layer existing on the surface of a semi-insulating GaAs substrate can be removed, and the deterioration of characteristics can be suppressed as much as possible. Moreover, the surface layer of the GaAs substrate can be inactivated by irradiation with N 2 plasma, and the electrical characteristics of the semiconductor device can be significantly improved. At this time, the nitrogen atom becomes GaAs
Although present on the s-substrate surface, it does not deteriorate the moisture resistance characteristics unlike hydrogen atoms.
【図１】本発明の一実施例における、台形状のチップを
形成した後の状態を示す断面図である。FIG. 1 is a cross-sectional view showing a state after a trapezoidal chip is formed in one embodiment of the present invention.
【図２】同上の一実施例における、ソース電極、および
ドレイン電極を形成した後の状態を示す断面図である。FIG. 2 is a cross-sectional view showing a state after forming a source electrode and a drain electrode in the example of the above.
【図３】同上の一実施例における、ゲート電極を形成し
た後の状態を示す断面図である。FIG. 3 is a cross-sectional view showing a state after forming a gate electrode in the example of Embodiment 1;
【図４】同上の一実施例における、Ｎ2プラズマ照射を
行なった後の状態を示す断面図である。FIG. 4 is a cross-sectional view showing a state after performing N 2 plasma irradiation in the example of the above.
【図５】同上の本発明の一実施例における、保護膜を形
成した後の状態を示す断面図である。FIG. 5 is a cross-sectional view showing a state after a protective film is formed in the embodiment of the present invention.
【図６】従来例における、台形状のチップを形成した後
の状態を示す断面図である。FIG. 6 is a cross-sectional view showing a state after a trapezoidal chip is formed in a conventional example.
【図７】同上における、ソース電極、およびドレイン電
極を形成した後の状態を示す断面図である。FIG. 7 is a cross-sectional view showing a state after forming a source electrode and a drain electrode in the above.
【図８】同上における、ゲート電極を形成した後の状態
を示す断面図である。FIG. 8 is a cross-sectional view showing a state after a gate electrode is formed in the same as above.
【図９】同上における、保護膜を形成した後の状態を示
す断面図である。FIG. 9 is a cross-sectional view showing a state after a protective film is formed in the above.
１ 活性領域 ２ 半絶縁性ＧａＡｓ基板 ３ ソース電極 ４ ドレイン電極 ５ ゲート電極 ６ 清浄化層・不活性化領域 ７ 保護膜 １１ 活性領域 １２ 半絶縁性ＧａＡｓ基板 １３ ソース電極 １４ ドレイン電極 １５ ゲート電極 １７ 保護膜 Reference Signs List 1 active region 2 semi-insulating GaAs substrate 3 source electrode 4 drain electrode 5 gate electrode 6 cleaning layer / inactive region 7 protective film 11 active region 12 semi-insulating GaAs substrate 13 source electrode 14 drain electrode 15 gate electrode 17 protection film
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/312 - 21/318 H01L 21/338 H01L 29/812 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. 7 , DB name) H01L 21/312-21/318 H01L 21/338 H01L 29/812
Claims (1)
板に、所定の電極を形成する工程と、プラズマ照射を行ない、前記活性領域の表面を清浄化か
つ不活性化するプラズマ照射工程と、 保護膜を形成する工程とを含む半導体装置の製造方法に
おいて、前記プラズマ照射 工程において、Ｎ2プラズマ照射のみ
を行なうことを特徴とする半導体装置の製造方法。1. A step of forming a predetermined electrode on a semi-insulating GaAs substrate having an active region formed thereon, and performing plasma irradiation to clean the surface of the active region.
One a plasma irradiation step of inactivating, in the method of manufacturing a semiconductor device and forming a protective film, in the plasma irradiation step, characterized in that it rows of <br/> only N 2 plasma irradiation A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10200291A JP3189291B2 (en) | 1991-04-05 | 1991-04-05 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10200291A JP3189291B2 (en) | 1991-04-05 | 1991-04-05 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04309227A JPH04309227A (en) | 1992-10-30 |
| JP3189291B2 true JP3189291B2 (en) | 2001-07-16 |
Family
ID=14315593
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10200291A Expired - Fee Related JP3189291B2 (en) | 1991-04-05 | 1991-04-05 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3189291B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5499319B2 (en) * | 2009-11-10 | 2014-05-21 | 国立大学法人 東京大学 | Semiconductor device and manufacturing method thereof |
-
1991
- 1991-04-05 JP JP10200291A patent/JP3189291B2/en not_active Expired - Fee Related
Non-Patent Citations (1)
| Title |
|---|
| Ｊｏｕｒｎａｌ ｏｆ Ａｐｐｌｉｅｄ Ｐｈｙｓｉｃｓ，１９８１年５月，第５２巻，第５号，ｐ．３５１５−３５１９ |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04309227A (en) | 1992-10-30 |
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