JP3240875B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor equipment.

[0002]

2. Description of the Related Art FIG.
aAs MODFET (Modulation Doped Field Effec
t Transistor).

In FIG. 6, reference numeral 24 denotes a semi-insulating GaAs substrate on which an intrinsic GaAs layer 25, an intrinsic InGaAs layer 26, an intrinsic AlGaAs layer 27, and an n-type AlGaAs layer 28 are sequentially laminated by an epitaxial growth method. Is formed.

In this structure, the intrinsic InGaAs layer 2
The two-dimensional electron gas 29 is generated in the region of the InGaAs layer 26 along the interface with the AlGaAs layer 27 due to the difference in electronegativity between the AlGaAs layer 27 and the intrinsic AlGaAs layer 27.

Reference numeral 30 denotes an n-type GaAs layer for reducing the electric resistance between the electrodes. The n-type GaAs layer 30 is formed on the n-type AlGaAs layer 28 by an epitaxial growth method, and a recess 33 is selectively provided thereon. Reference numeral 31 denotes an ohmic electrode, which is formed on the n-type GaAs layer 30 divided by the recess. One is a source electrode and the other is a drain electrode.

Reference numeral 32 denotes a Schottky gate electrode, which is an n-type G
formed in a recess 33 formed in the aAs layer 30;
A Schottky junction with the n-type AlGaAs layer 28 is formed.

When a negative potential is applied to the source electrode with respect to the drain electrode, electrons are transferred from the source electrode to the n-type GaAs layer 30, the n-type AlGaAs layer 28, the intrinsic AlGaAs layer 2
7. The two-dimensional electron gas 29 is supplied.

Electrons move from the source to the drain due to the electric field between the source and the drain, but the electrons concentrate in the two-dimensional electron gas 29 under the recess 33.

The electron density of the two-dimensional electron gas 29 in the region below the Schottky gate electrode 32 is modulated by the potential applied to the Schottky gate electrode 32. The current flowing between the source and drain electrodes can be controlled by this modulation action.

[0010] A protective film for preventing oxidation and contamination is provided on the surface of the semiconductor element. For this reason, GaAs MO
The DFET surface is covered with a protective film 34 made of SiN or SiO ₂ formed by a P-CVD method (chemical vapor deposition).

Particularly, in a GaAs MODFET, A
Since the lGaAs layer 28 is easily oxidized, the recess 33
It is necessary to form a protective film 34 having a sufficient thickness inside.

A capacitance 35 is generated between the Schottky gate electrode 32 and the two-dimensional electron gas 29. This capacitance is determined by the capacitance between the Schottky junction and the two-dimensional electron gas and the side wall of the Schottky gate electrode 32.
4. n-type AlGaAs layer 28, intrinsic AlGaAs layer 27
And the sum of the capacitances generated by the electric field that reaches the two-dimensional electron gas through.

FIG. 7 shows a GaAs MOD according to a conventional method.
FIG. 5 is a process sectional view of the FET formation. In FIG. 7A,
An element isolation region and an ohmic electrode 37 serving as a source electrode and a drain electrode are formed on a GaAs substrate 36 having a MODFET structure, and a heat treatment for alloying the ohmic electrode is performed. The layers are formed by coating.

As a combination of resists, PMGI (Poly-dimethyl grutaruimi) is used as the lower resist film 38.
de), and PMMA (Poly-met)
hylmethaclyrate) is used.

In a GaAs MODFET, a gate length of 0.3 μm or less is required in order to increase the transconductance gm per unit gate width. for that reason,
An electron beam or far ultraviolet light has been conventionally used for exposing the gate pattern. Reference sign 40
Exposure with an electron beam or deep ultraviolet light indicated by

In FIG. 7B, the upper resist film 39 made of PMMA is replaced with MIBK (methyl iso-butyl keton).
e), and then the lower resist film 38 made of PMGI is coated with TMAH (tetra-methyl ammonium hydroxid).
e) Develop with an aqueous solution to form a gate resist pattern 41 having an overhang shape.

In FIG. 7C, a recess 42 is provided by etching the GaAs substrate. In FIG. 7D,
The gate electrode metal is vacuum-deposited, and the Schottky gate electrode 4 is formed by a lift-off method using the resist films 38 and 39.
Form 3 Thereafter, a protective film 44 made of SiN is formed by P-CVD (plasma chemical vapor deposition).

[0018]

SUMMARY OF THE INVENTION GaAs MODFE
The minimum noise figure NFmin of T is represented by the following equation (1). The minimum noise figure NFmin indicates the magnitude of the internal noise generated inside the amplifier when the amplifier circuit is composed of a GaAs MODFET. The smaller the value, the better the low noise performance.

NFmin = 1 + KfCgs [(Rs + Rg) / gm] ^1/2 (1) In equation (1), K is a coefficient that depends on the material and shape of the device, Cgs is the capacitance between the gate and source, Rs is the source resistance, Rg is the gate resistance, and gm is the transconductance.

As is apparent from the equation (1), the minimum noise figure NFmin can be reduced by reducing the gate-source capacitance Cgs, the source resistance Rs, and the gate resistance Rg, and increasing the mutual conductance gm.

The capacitance Cgs between the gate and the source is shown in FIG.
As shown in the figure, the capacitance of the Schottky junction and the capacitance generated by the electric field from the side wall of the Schottky gate electrode 32 to the two-dimensional electron gas 29 through the SiN protective film 34 and the AlGaAs layers 28 and 27 are obtained. It is sum.

The main cause of the internal noise of the device is thermal noise generated by scattering of electrons flowing in the device and local fluctuation of the current. That is, the internal noise increases as the electric resistance increases and the current density increases.

In the vicinity of the Schottky gate electrode of the GaAs MODFET, the current is confined in the two-dimensional electron gas, so that the current density is large. Therefore, GaA
Internal noise (thermal noise) is generated in the s-MODFET in the two-dimensional electron gas near the gate.

The generated internal noise is applied to the Schottky gate electrode and amplified by the gate-source capacitance Cgs. The amount of internal noise generated is GaAs MODF
Since it is determined by the material constituting ET, it is difficult to suppress the amount of internal noise generated for a given material.

Therefore, in order to reduce the minimum noise figure NFmin, it is necessary to reduce the gate-source capacitance Cgs as much as possible to reduce the internal noise applied to the Schottky gate electrode.

The reduction in the capacitance of the Schottky junction and the increase in the transconductance gm are realized by reducing the cross-sectional width (gate length) of the gate electrode. The capacitance generated between the gate electrode and the two-dimensional electron gas from the side of the Schottky gate electrode through the SiN protective film and the AlGaAs layer indicates the relative dielectric constant of the material in the path from the gate electrode side wall to the two-dimensional electron gas. It can be reduced by reducing the size.

Here, the relative dielectric constant of the material used as the protective film is as large as 5 to 6 for SiN and about 4 for SiO _2. The capacitance is reduced, and the minimum noise figure NFmin can be reduced.

However, in the conventional device structure, if there is no protective film, the AlGaAs exposed on the bottom of the recess is oxidized and contaminated to generate a surface level, and the device characteristics change with time.

For this reason, in the conventional device structure, it is necessary to provide a protective film having a sufficient thickness in the recess structure, and it is necessary to avoid an increase in the minimum noise figure NFmin due to an increase in the capacitance Cgs between the gate and the source due to the protective film. I can't.

Further, a GaAs MODFET having a conventional structure
When the gate length is reduced, the cross-sectional area of the gate electrode decreases, and the source resistance Rs increases. As the source resistance Rs increases, the minimum noise figure NFmi becomes apparent from the equation (1).
n increases.

In the step of forming a gate electrode of a conventional GaAs MODFET, as shown in FIG. 7, a gate electrode pattern is formed as a cut pattern in a resist film.

In general, a resist residue called scum is formed at the end of the resist pattern after development. Scum deteriorates the accuracy of the pattern shape.

In order to remove the scum, the resist film after the development is adjusted to 0.05 to 0.1 μm by oxygen plasma ashing.
Is etched by the thickness of. This etching step is usually called a descum step.

The descum process has the effect of removing scum and increasing the hydrophilicity of the resist film surface so that a water-soluble etching solution can easily enter the inside of the resist pattern during wet etching.

In particular, the resist pattern is GaAs.MO.
In the case of a pattern with a fine width of 0.25 μm or less necessary for forming a gate electrode of a DFET, if the hydrophilicity of the resist film surface is not increased before wet etching, the etching solution can sufficiently enter the inside of the resist pattern. I ca n’t,
Accurate etching is not possible.

In a conventional GaAs MODFET gate formation step, a recess structure is formed by a wet etching method after a resist pattern is formed. Therefore, the descum process is an essential process in the gate formation of the conventional GaAs MODFET.

However, in the descum process, the resist pattern itself is etched at the same time as the scum is removed. When a gate pattern is formed as a cut pattern in a resist film as in the related art, the width of the resist pattern increases due to descum.

0.30 μm for GaAs MODFET
The following gate pattern needs to be formed. The etching amount of the resist by the descum is about 0.05 to 0.1 μm. The increase in the width of the resist pattern due to the descum becomes a serious problem when forming a fine gate electrode of 0.30 μm or less.

The conventional device structure and manufacturing method have the above-mentioned problems to be solved.

[0040]

[0041]

[0042]

[0043]

[Means for Solving the Problems] In order to solve the above-mentioned problems
The method of manufacturing a semiconductor device according to the first aspect of the present invention comprises
After forming a resist pattern on the substrate, an insulating film is deposited over the entire surface of the substrate, and a method of forming the pattern by removing the insulating film thereover by a lift-off method using the resist pattern, forming a resist pattern forming step A step of exposing the GaAs substrate to oxygen plasma and washing with a buffered hydrofluoric acid, a tartaric acid solution, or a citric acid solution is included between the evaporation step and the GaAs substrate.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device, after forming a resist pattern on a GaAs substrate, a SiO2 film is deposited on the entire surface of the substrate, and the resist pattern is formed by a lift-off method using the resist pattern. The method of forming a pattern of the SiO ₂ film by removing the SiO ₂ film above, exposing the GaAs substrate to oxygen plasma incineration between the resist pattern forming step and the vapor deposition step, and then performing buffering. A step of washing with hydrofluoric acid, hydrochloric acid, tartaric acid solution, or citric acid solution;

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device, after forming a resist pattern on a GaAs substrate, an SiO film is deposited on the entire surface of the substrate, and the resist pattern is formed by a lift-off method using the resist pattern. The method of forming a pattern of the SiO film by removing the SiO film on the substrate, exposing the GaAs substrate to oxygen plasma ashing between the resist pattern forming step and the vapor deposition step, and then using buffered hydrofluoric acid , Hydrochloric acid, tartaric acid solution,
Alternatively, the method includes a step of washing with a citric acid solution.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a resist pattern on a substrate;
An O ₂ film or SiO film is deposited on the entire surface of the substrate, and the SiO ₂ film or SiO film on the resist pattern is removed by a lift-off method using the resist pattern to form a pattern of the SiO ₂ film or SiO film Prior to the lift-off step, the SiO ₂ film or SiO film is treated with buffered hydrofluoric acid for 10 minutes.
And a step of etching by a thickness of 0 ° or more.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device, a gate electrode pattern is formed on a GaAs substrate using a first resist as a remaining pattern of the first resist, and the gate electrode pattern is formed by oxygen plasma ashing. After shaving the first resist pattern, the GaAs substrate is buffered with hydrofluoric acid,
Hydrochloride, was washed with tartaric acid solution or citric acid solution, and depositing a SiO2 film or a SiO film on the entire surface of the substrate, the SiO ₂ film or SiO using buffered hydrofluoric acid
After etching the film by a thickness of 100 ° or more, the first
SiO ₂ film or SiO ₂ on the resist pattern of
After removing the film by a lift-off method to form a gate electrode removal pattern made of the SiO ₂ film or the SiO film, a source / drain electrode pattern is formed by using a second resist as a second resist removal pattern. ₂ film or SiO film formed on the SiO ₂ film at the opening of the second resist pattern.
After removing the O film by etching, depositing a metal to be an ohmic electrode and forming a source / drain electrode by a lift-off method using the second resist pattern,
Using the third resist, the SiO ₂ film or SiO
A resist pattern having an opening including all the openings of the film pattern is formed, and the SiO ₂ film or Si is formed.
The GaAs is used as an etching mask with the pattern for removing the gate electrode made of an O film and the third resist pattern.
After etching the substrate to form a recess structure, a metal serving as a gate electrode is vacuum-deposited, lift-off is performed using the third resist pattern to form a gate electrode, and then a protective film is deposited on the entire surface of the substrate. .

[0048]

According to the present invention, the substrate is joined to the bottom of the depression provided in the substrate, and
By using an electrode having a structure that closes the opening of the recess and has a space between the recess and the inner surface of the recess as a Schottky gate electrode of the GaAs MODFET, the inside of the recess is formed of SiN.
Alternatively, the surface of the semiconductor element can be protected by covering the entire surface of another substrate with a protective film without covering with a protective film such as SiO ₂ .

Similarly, it is joined to the dent of the substrate provided in the opening of the insulating film attached to the substrate, closes the opening of the dent together with the insulating film, and has a space between itself and the inner surface of the dent. By using an electrode having a structure as a Schottky gate electrode of a GaAs MODFET, it is possible to protect the semiconductor element surface by covering the entire surface of another substrate with a protective film without covering the inside of the recess structure with a protective film such as SiN or SiO _2. Can be.

The two types of structures protect the inside of the recess structure from oxidation and contamination without a protective film in order to isolate the inside of the recess structure from the outside by a gate electrode or the like.

Since there is no protective film in the recess, the capacitance generated between the side surface of the gate electrode and the two-dimensional electron gas decreases,
Since the capacitance Cgs between the gate and the source can be made smaller than that of the conventional structure, the minimum noise figure NFmin can be made smaller than that of the conventional structure.

The substrate is joined to the bottom surface of the recess provided in the opening of the insulating film attached to the substrate, and covers the opening of the recess together with the insulating film, and has a space between the inner surface of the recess and In addition, by using an electrode having a structure in which the width of the upper portion is larger than the width of the junction as the Schottky gate electrode of the GaAs MODFET, the inside of the recess is made of SiN or
without covering with a protective film such as iO _2, and at the same time it is possible to protect the semiconductor device surface covering the other entire surface of the substrate with a protective film, the gate length can be shortened without reducing the cross-sectional area of the Schottky gate electrode .

Thus, when the gate length is shortened to reduce the mutual conductance gm and the capacitance Cgs between the gate and the source, the gate resistance Rg can be made smaller than that of the conventional structure, so that the minimum noise figure NFmin can be made smaller than that of the conventional structure. Can also be reduced.

After a resist pattern is formed on a GaAs substrate, an insulating film is vapor-deposited on the entire surface of the substrate, and a lift-off method is used to form an insulating film pattern. After exposure to oxygen plasma, washing with buffered hydrofluoric acid, tartaric acid solution, or citric acid solution, or
After forming a resist pattern on a GaAs substrate,
O ₂ film is deposited on the entire surface of the substrate, and Si
In the method of forming a pattern of an O ₂ film, a GaAs substrate is exposed to oxygen plasma ashing between a resist pattern forming step and a vapor deposition step, and then a buffered hydrofluoric acid, hydrochloric acid, tartaric acid solution, or citric acid solution is used. In a method of forming a resist pattern on a GaAs substrate, and then forming a resist pattern on a GaAs substrate, and then depositing a SiO film on the entire surface of the substrate and forming a pattern of the SiO film by a lift-off method, a method of forming a resist pattern between Then, after exposing the GaAs substrate to oxygen plasma ashing, the step of cleaning using a buffered hydrofluoric acid, hydrochloric acid, tartaric acid solution, or citric acid solution comprises the steps of: forming a scum generated during the formation of a resist pattern by oxygen plasma ashing; At the same time as removing the resist remaining on the resist pattern, the resist pattern is also etched.

For this reason, when the gate pattern is formed by the remaining pattern of the resist, a resist pattern having a gate length shorter than the optical or electro-optical resolution limit at the time of exposing the resist pattern by oxygen plasma ashing is used. Can be formed.

Further, a GaAs oxide film is formed on the GaAs surface by oxygen plasma. The oxide film is removed by washing with buffered hydrofluoric acid, hydrochloric acid, tartaric acid aqueous solution, or citric acid aqueous solution.

After the oxygen plasma ashing, the contaminants on the GaAs surface are present on the oxide film.
Contaminants on the GaAs surface are also removed.

By removing the contaminants and the oxide film, the adhesion between the insulating film, the SiO ₂ film, or the SiO film and the GaAs deposited after this step is improved. In addition, surface levels generated on the GaAs surface due to contaminants are eliminated. Thereby, the performance and reliability of the semiconductor device are improved.

After forming a resist pattern on the substrate,
In a method in which a SiO ₂ film or a SiO film is deposited on the entire surface of a substrate and a pattern of the SiO ₂ film or the SiO film is formed by a lift-off method, Si
O ₂ film or SiO film is formed using buffered hydrofluoric acid
By etching by the above thickness, the SiO ₂ film or the SiO film adhered to the side surface of the resist pattern can be removed.

[0060] This and the SiO ₂ film or a SiO film deposited on the resist pattern, since it can detach the SiO ₂ film or a SiO film deposited on the GaAs substrate, the SiO ₂ film or SiO on the resist pattern
The film can be easily removed by lift-off.

By this step, the SiO ₂ film or the SiO ₂ film
In order to improve the uniformity of the film thickness on the wafer surface, a planetary deposition is performed, and even if a SiO ₂ film or a SiO film is deposited on the side surface of the resist pattern, lift-off becomes possible.

A gate electrode pattern is formed on the GaAs substrate using the first resist as a remaining pattern of the resist, and after removing the first resist pattern by oxygen plasma ashing, the substrate is buffered hydrofluoric acid, hydrochloric acid, tartaric acid. After washing with aqueous solution or citric acid aqueous solution,
O ₂ or of SiO is deposited on the entire surface of the substrate, after 100Å or thicker etching of SiO ₂ or SiO using a buffer hydrofluoric acid, SiO ₂ on the first resist pattern
Alternatively, the SiO is removed by a lift-off method to remove the SiO.
After forming the open pattern of the gate electrode by ₂ or SiO film, a second SiO ₂ source and drain electrode pattern using a resist film or SiO ₂ film using the second resist pattern is formed on the SiO film Alternatively, an opening is formed in the SiO film, a metal serving as an ohmic electrode is deposited, and a source / drain electrode is formed by a lift-off method using a second resist pattern.
A resist pattern having an opening including all the openings of the SiO ₂ film or the SiO film pattern is formed using the above-mentioned resist, and the SiO ₂ film or the SiO pattern and the third resist pattern are used as an etching mask to form a resist pattern.
After etching the As substrate to form a recess structure, a metal serving as a gate electrode is vacuum-deposited, lifted off using a third resist pattern to form a gate electrode, and then a protective film made of SiN or SiO ₂ is formed. In the step of depositing over the entire surface of the substrate, the SiO ₂ film or the SiO film is not deteriorated or deformed by the heat treatment after the formation of the ohmic electrode, so that a fine gate pattern can be formed before the formation of the ohmic electrode.

As a result, there is no deterioration in the dimensional accuracy of the gate length caused by the change in the resist film thickness due to the step of the ohmic electrode. Further, since the SiO ₂ film or the SiO film can be used as a spacer at the time of lift-off of the ohmic electrode, the lift-off step of the ohmic electrode is simplified.

Further, the third resist is used to form SiO ₂
After forming a resist pattern having an opening including all the openings of the film or the SiO film pattern, etching the GaAs substrate using the SiO ₂ pattern or the SiO pattern and the third resist pattern as an etching mask to form a recess, By forming a gate electrode by vacuum-depositing a metal to be a gate electrode and lifting off using a third resist pattern to form a gate electrode, a recessed structure is formed by covering the gate electrode itself with a SiO ₂ film or a SiO film. Can be.

Thus, during the step of depositing a protective film of SiN or SiO _{2 on} the entire surface of the substrate, a structure in which the surface of the semiconductor device is covered with the protective film without forming the inside of the recess with the protective film can be formed.

[0066]

FIG. 1 shows a GaAsM according to an embodiment of the present invention.
FIG. 3 is a sectional structural view of an ODFET. In FIG. 1, reference numeral 1 denotes a semi-insulating GaAs substrate, on which an intrinsic GaAs layer 2, an intrinsic InGaAs layer 3, an intrinsic AlGaAs layer 4, and n
Type AlGaAs layers 5 are sequentially laminated and formed by molecular beam epitaxial growth. Reference numeral 6 denotes a two-dimensional electron gas, which is formed in a region along the interface with the intrinsic AlGaAs layer 4 in the intrinsic InGaAs layer 3.

Reference numeral 7 denotes an n-type GaAs layer, which is formed on the n-type AlGaAs layer 5 by molecular beam epitaxy, and further provided with a recess 10. 8 is AuGeN
Ohmic electrodes made of i / Au are formed on the n-type GaAs layer 7 divided by the recess 10.

Reference numeral 9 denotes a Schottky gate electrode, which is an n-type Ga
At the bottom of the recess 10 provided in the As layer 7, n-type A
A Schottky junction with the lGaAs layer 5 is formed. The upper part of the Schottky gate electrode 9 is wider than the Schottky junction, and the SiO ₂ layer 11 and the Schottky gate electrode 9
The inside of the recess 10 is isolated from the outside by the upper portion of the recess 10.

The upper portion of the gate electrode 9 has a large cross-sectional area, so that the gate resistance Rg is reduced and the minimum noise figure NFmin is reduced. Reference numeral 12 denotes a protective film made of SiN formed by a P-CVD method (plasma chemical vapor deposition).

This protective film 12 improves the hermeticity of the recess 10 by the Schottky gate electrode 9 and the SiO ₂ layer 11, and also protects the device surface in other parts.

However, since the inside of the recess 10 is sealed, no SiN film is formed inside the recess 10 during the P-CVD process, and the capacitance between the Schottky gate electrode 9 and the two-dimensional electron gas 6 is reduced. 13 can be made smaller than before, so that when compared with the same gate length, the capacitance Cgs between the gate and the source can be made smaller than that of the conventional structure, the minimum noise figure NFmin is smaller than that of the conventional structure, and the low noise performance A GaAs MODFET with excellent performance can be realized.

FIG. 2 is a process sectional view of one embodiment of the method of manufacturing a semiconductor device according to the present invention. In FIG. 2A, a 0.2 μm-wide gate resist is formed on a GaAs substrate 14 having a GaAs MODFET structure formed on its surface by an epitaxial growth method to form an element isolation region having a mesa structure, using a positive type photoresist. A pattern is formed by a reduction projection exposure method using a transparent phase shift mask.

For exposure, i of 1/5 reduction of NA = 0.54
A line stepper was used. As the resist, i-line resist “THMR-ip 3000” manufactured by Tokyo Ohka Kogyo Co., Ltd.
And the film thickness was set to 1.2 μm.

At the step portion of the mesa structure, the resist film thickness changes. When the resist film thickness changes by the light exposure method, the state of a standing wave generated in the resist film changes, and the sensitivity of the resist changes locally.

In order to prevent a change in the resist pattern width due to the local change in the sensitivity of the resist, an antireflection film was applied on the resist to prevent the generation of standing waves. As an antireflection film, “AZ Aqqta” manufactured by Hoechst Co.
r "was used.

After the development of the resist, the gate resist pattern was etched to a width of 0.15 μm by an oxygen plasma ashing method to obtain a gate resist pattern 15.

In FIG. 2B, the substrate 14 is washed with a tartaric acid solution, washed with water and dried, and then a SiO ₂ film 16 is deposited by a vacuum deposition method using electron beam heating. In order to improve the uniformity of the film thickness in the plane of the wafer, the film was deposited by a planetary method.

The thickness of the SiO ₂ film 16 was 4000 °. By cleaning with tartaric acid, contaminants on the surface of the GaAs substrate 14 are removed, and the SiO ₂ film 16 and the GaAs substrate 1 are removed.
4 The adhesion of the surface is improved. No substrate heating is performed. At this time, by setting the deposition rate to 200 ° per minute or less, SiO ₂ having good film quality and good adhesion to the GaAs substrate 14 can be obtained.
A film 16 can be formed.

After the evaporation, the SiO ₂ film 1 was formed using buffered hydrofluoric acid.
6 and a thickness of 100Å partial etch, to remove the SiO ₂ film 16 deposited on the side surfaces of the gate resist pattern 15, and the SiO ₂ film 16 deposited on the resist pattern G
The structure shown in FIG. 2B is obtained by separating the SiO ₂ film 16 deposited on the surface of the aAs substrate 14.

[0080] In FIG. 2 (c), was dissolved gate resist pattern 15 by using a resist release material, is lifted off the SiO ₂ film 16 on the resist pattern, SiO ₂
A gate pattern 17 is formed. As a resist stripping material, "Clean Strip HP" manufactured by Tokyo Ohka Kogyo Co., Ltd.
Was used.

At this time, the re-adhesion of the lifted-off SiO ₂ film to the substrate surface can be reduced by heating the release material below the boiling point to increase the dissolution rate of the resist. Further, after lift-off, the surface of the substrate is wiped off with a sponge such as acetic acid in water, so that the re-adhered SiO ₂ film can be completely removed.

[0082] forming a resist pattern of the ohmic electrode on a substrate formed with SiO ₂ gate pattern 17, using a buffer hydrofluoric acid, the resist pattern opening portion of the SiO ₂
The film 16 is etched to expose the GaAs surface.

Thereafter, AuGeNi / Au is vacuum-deposited and the ohmic electrode 18 shown in FIG. 2D is formed by a lift-off method. The thickness of AuGeNi / Au is changed to Si
By making the thickness smaller than the thickness of the O ₂ film 16, AuGeNi
/ Au can be easily lifted off using the SiO ₂ film 16 as a spacer. After forming the ohmic electrode 18, the substrate is heat-treated at 500 ° C.
The contact resistance of the s substrate 14 is reduced.

In FIG. 2E, in order to form a Schottky gate electrode by lift-off on the substrate on which the ohmic electrode 18 has been formed, a negative type photoresist film 19 is applied, and the gate electrode upper pattern 20 is formed by exposure and development. To form

The reason for using a negative photoresist is that an overhang-shaped cross section suitable for the lift-off method can be easily formed.

As a resist, "THMR-in 200 D1" manufactured by Tokyo Ohka Kogyo Co., Ltd. was used in a thickness of 1.4 μm. The width of the upper part of the gate electrode was 1 μm.

After the gate electrode upper pattern 20 is formed, the GaAs substrate 14 is wet-etched with a mixed aqueous solution of tartaric acid and hydrogen peroxide to form a recess 21. The end point of the etching was determined by measuring the electric resistance between the ohmic electrodes.

After the formation of the recess 21, Ti / Al is deposited by a vacuum deposition method using electron beam heating. The film thickness of Ti / Al was 1 μm. Thereafter, the negative resist film 19 is dissolved with a resist release material, and Ti / Ti on the resist pattern is removed.
Al is removed by lift-off to form a Schottky gate electrode 22 shown in FIG. "Remover 1165" manufactured by Shipley Co. was used as the resist stripping material.

After the gate electrode is formed, SiN is formed by P-CVD.
Is formed. The thickness of the protective film 23 made of SiN was 1000 °.

Note that an SiO film can be used instead of the SiO ₂ film 16. When an SiO film is used, FIG.
(D) SiO etching at the time of forming the ohmic electrode 18 is performed by reactive ion etching of CHF ₃ / O ₂ .

Table 1 below shows the difference in the adhesion of the SiO ₂ film between the oxygen plasma ashing process and the presence or absence of surface cleaning. Adhesion was evaluated by the adhesion of the SiO ₂ film 16 and the GaAs substrate 14 at the time of lift-off of the SiO ₂ film 16 in FIG. 2 (c). The conditions for resist pattern formation and oxygen plasma ashing are the same as in the embodiment of FIG.

[0092]

[Table 1]

As is evident from Table 1, without the oxygen plasma ashing, the SiO ₂ film 16 was made of GaAs after lift-off.
The s substrate 14 is peeled off from the surface. Even when oxygen plasma ashing is performed, film peeling during lift-off occurs. After performing the oxygen plasma incineration treatment, buffered hydrofluoric acid, hydrochloric acid, tartaric acid solution, or when washing with citric acid solution,
No film peeling during lift-off.

From the results, the oxygen plasma ashing process was performed after the development of the resist pattern, and the substrate was washed with a buffered hydrofluoric acid, hydrochloric acid, tartaric acid solution, or citric acid solution, so that the SiO ₂ and the GaAs substrate surface were adhered to each other. It is clear that the performance is improved. The same result was obtained for SiO.

FIG. 3 shows the line width of the gate resist pattern after development with respect to the resist exposure time when forming the gate resist pattern 15 in FIG. The horizontal axis is the resist exposure time, and the vertical axis is the gate resist pattern width after development.

When the width of the gate resist pattern after development is equal to 0.
In the region from 35 μm to more than 0.25 μm, the line width sharply decreases as the exposure time increases.

When the width of the gate resist pattern after development is equal to 0.
In the region from 25 μm to 0.20 μm, the decrease in the line width with the increase in the exposure time becomes gentle.

When the width of the gate resist pattern after development is equal to 0.
In an area smaller than 20 μm, the line width sharply decreases as the exposure time increases.

From the results shown in FIG. 3, it is apparent that the width of the gate resist pattern that can be formed stably with respect to the fluctuation of the exposure time is 0.20 to 0.25 μm.

FIG. 4 shows a change in the pattern yield when the amount of oxygen plasma ashing at the time of forming the gate resist pattern 15 in FIG. 2A is changed.

In FIG. 4, the horizontal axis is the gate resist pattern width after oxygen plasma ashing, and the vertical axis is the pattern yield. The pattern yield was determined by counting a normal gate pattern by microscopic observation after washing with a tartaric acid solution.

From 0.20 μm to 0.15 μm, the pattern yield is almost 100%. However, when the pattern width becomes smaller than 0.15 μm, the yield decreases sharply as the pattern width decreases. All pattern failures are pattern collapses.

From this, it can be seen that with a pattern width smaller than 0.15 μm, the resist does not sufficiently adhere to the GaAs surface for cleaning after oxygen plasma ashing. Similar results were obtained when washing with buffered hydrofluoric acid, citric acid solution, or hydrochloric acid.

FIG. 4 clearly shows that the minimum gate pattern width that can be formed is 0.15 μm.

FIG. 5 shows the relationship between the thickness of the SiO ₂ film 16 to be etched and the pattern yield before the lift-off in FIG. 2B. In FIG. 5, the horizontal axis represents the thickness of the SiO ₂ film to be etched, and the vertical axis represents the pattern yield.

The pattern yield was determined by observing the pattern after lift-off with a scanning electron microscope and counting normal patterns. When the etching amount is 100 ° or more, the pattern yield is almost 100%, but when the etching amount is 100 ° or less, the pattern yield decreases as the etching amount decreases. The defect content is a needle-like burr of SiO ₂ generated at the edge of the SiO ₂ pattern 15.

It is apparent from the result that etching of 100 ° or more is required before lift-off of SiO ₂ .

[0108]

According to the present invention, it is possible to form a GaAs MODFET having a lower noise performance than the conventional one.

[Brief description of the drawings]

FIG. 1 is a sectional view of one embodiment of a semiconductor device of the present invention.

FIG. 2 is a process cross-sectional view for explaining one embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 3 is a graph showing the relationship between the resist exposure time when forming a gate pattern and the line width of a gate resist pattern after development.

FIG. 4 is a graph showing a change in pattern yield when the amount of oxygen plasma ashing during formation of a gate resist pattern is changed.

Figure 5 is a graph showing the relationship between the etching film thickness and pattern yield of SiO ₂ film before lift-off of the SiO ₂ film

FIG. 6 is a cross-sectional view of a conventional GaAs MODFET.

FIG. 7 is a process cross-sectional view for explaining a method for manufacturing a conventional GaAs MODFET.

[Explanation of symbols]

Reference Signs List 1 semi-insulating GaAs substrate 2 intrinsic GaAs layer 3 intrinsic InGaAs layer 4 intrinsic AlGaAs layer 5 n-type AlGaAs layer 6 two-dimensional electron gas 7 n-type GaAs layer 8 ohmic electrode 9 Schottky gate electrode 10 recess 11 SiO ₂ layer 12 SiN protection Film 13 Capacitance between gate electrode and two-dimensional electron gas 14 GaAs substrate 15 Gate resist pattern 16 SiO ₂ film 17 SiO ₂ gate pattern 18 Ohmic electrode 19 Negative photoresist film 20 Gate electrode upper pattern 21 Recess 22 Schottky gate Electrode 23 SiN protective film

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/778 H01L 29/812 H01L 21/338 H01L 21/3065

Claims (6)

(57) [Claims] After a resist pattern is formed on a GaAs substrate, an insulating film is deposited on the entire surface of the substrate, and the insulating film on the resist pattern is removed by a lift-off method using the resist pattern to remove the insulating film. In the method for forming a pattern, a step of exposing the GaAs substrate to oxygen plasma between the resist pattern forming step and the vapor deposition step, followed by washing with a buffered hydrofluoric acid, a tartaric acid solution, or a citric acid solution A method for manufacturing a semiconductor device, comprising: 2. After forming a resist pattern on a GaAs substrate, SiO2 film was deposited on the entire surface of the substrate, the resist pattern by removing the SiO ₂ film on the resist pattern by a lift-off method using the SiO ₂ In the method of forming a film pattern, between the resist pattern forming step and the vapor deposition step, after exposing the GaAs substrate to oxygen plasma ashing, buffered hydrofluoric acid, hydrochloric acid, tartaric acid solution, or citric acid solution is added. A method for manufacturing a semiconductor device, comprising a step of using and cleaning. 3. After forming a resist pattern on a GaAs substrate, an SiO film is deposited on the entire surface of the substrate, and the SiO film on the resist pattern is removed by a lift-off method using the resist pattern to remove the SiO film. In the method of forming a pattern, after exposing the GaAs substrate to oxygen plasma ashing between the resist pattern forming step and the vapor deposition step, using a buffered hydrofluoric acid, hydrochloric acid, tartaric acid solution, or citric acid solution A method for manufacturing a semiconductor device having a cleaning step. 4. After forming a resist pattern on the substrate, an SiO ₂ film or SiO film is deposited on the entire surface of the substrate, and the SiO ₂ film or S on the resist pattern is lifted off using the resist pattern.
In the method of forming a pattern of the SiO ₂ film or the SiO film by removing the iO film, a step of etching the SiO ₂ film or the SiO film to a thickness of 100 ° or more using buffered hydrofluoric acid before the lift-off step A method for manufacturing a semiconductor device, comprising: 5. A method of forming a gate electrode pattern on a GaAs substrate using a first resist as a remaining pattern of the first resist, and shaving the first resist pattern by oxygen plasma ashing; after washing the buffer hydrofluoric acid, hydrochloric acid, by tartaric acid solution or citric acid solution,, SiO2 film or a SiO film is deposited on the whole surface of the substrate, the thickness of more than 100Å the SiO ₂ film or SiO film with a buffered hydrofluoric acid after partial etching, the SiO ₂ by removing the SiO ₂ film or SiO film on the first resist pattern by a lift-off method
After forming a gate electrode removal pattern made of a film or a SiO film, a source / drain electrode pattern is formed as a second resist removal pattern on the SiO ₂ film or the SiO film using a second resist. The SiO ₂ film or the SiO film in the opening of the second resist pattern is removed by etching, a metal serving as an ohmic electrode is deposited, and a source / drain electrode is formed by a lift-off method using the second resist pattern. After that, using a third resist, a resist pattern having an opening including all the openings of the SiO ₂ film or the SiO film pattern is formed, and a gate electrode removal pattern made of the SiO ₂ film or the SiO film is formed. And etching the GaAs substrate using the third resist pattern as an etching mask. After forming a recess structure by vacuum etching, a metal serving as a gate electrode is vacuum-deposited, lift-off is performed using the third resist pattern to form a gate electrode, and then a protective film is deposited on the entire surface of the substrate. A method for manufacturing a semiconductor device. 6. The minimum line width of the first resist pattern after development is 0.2 to 0.25 μm, and the minimum line width of the first resist pattern after oxygen plasma ashing is 0.15 μm or more. 6. The method for manufacturing a semiconductor device according to claim 5 , wherein: