JPH0845962A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enhance a FET in dielectric strength between a gate and a drain improving it in controllability of dielectric strength between a gate and a drain without markedly deteriorating it in mutual conductance. CONSTITUTION:A second recess 12 shallower than a first recess 4 is formed outside it in a region under a gate electrode upper layer 7 formed of low- resistance metal. The gate electrode upper layer 7 is changed in width, whereby the second recess 12 is changed in width, and a FET of this constitution can be improved in dielectric strength between a gate and a drain. A part of an active layer located under the second recess 12 becomes larger in thickness than another part of the active layer located under the first recess 4, whereby the FET can be enhanced in dielectric strength between a gate and a drain without deteriorating markedly in mutual conductance as compared with one made through a conventional method where a recess is increased in width.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a two-step recess in a field effect transistor having a T-type gate.

[0002]

2. Description of the Related Art A field effect transistor (hereinafter abbreviated as FET) having a T-shaped gate electrode capable of reducing the gate resistance even with a short gate length and excellent in high frequency characteristics.
Is being developed. In addition, for the purpose of setting the saturated drain current to a desired value, improving the gate-drain breakdown voltage, and the like,
An FET in which a recess called a recess is formed in an active layer and a gate electrode is provided in the recess is also used. One of the conventional manufacturing methods for an FET having such a T-shaped gate electrode and a recess is a manufacturing method disclosed in Japanese Patent Laid-Open No. 174374/1988.

FIG. 8 shows one application example of the method of manufacturing the FET shown in the above publication. First, as shown in FIG. 8A, a SiO film 2 having a thickness of about 200 nm is formed on a semi-insulating GaAs substrate 1 having an n-type active layer 20 formed on the surface thereof.
An insulating film such as is formed, and a resist 3 is further formed.
Next, the SiO film under the opening of the resist 3 is removed by reactive ion etching (hereinafter abbreviated as RIE) or the like, and the exposed GaAs surface is etched to a depth of 200 n.
A recess 4 of about m is formed. After that, as shown in FIG. 8B, the resist 3 is removed, an SiO film having a film thickness of about 500 nm is formed on the entire surface, and then an SiO 2 side wall 5 is formed by etching back. The width of the side wall 5 is about 200 nm. Next, as shown in FIG. 8 (c), a WSi film 6 (film thickness of about 200 nm), which is a heat-resistant gate material, and an Au film 7 (film thickness of 400 to 500 nm), which is a low resistance metal, are laminated to form a gate electrode. A resist 8 is formed on the region to be the T-type gate electrode. Thereafter, as shown in FIG. 8D, Au 7 is etched using the resist 8 as a mask, and WSi 6 is further etched. Next, as shown in FIG. 8 (e), plasma etching or the like is performed so that the width is made narrower than Au7.
After etching the side surface of the WSi 6 using u7 as a mask, the resist 8 and the SiO film 2 are removed. Finally, the SiO sidewall 5 may be removed as shown in FIG.

In such a T-type gate FET, the sidewall 5
The gate length can be shortened by using, and the gate resistance can be reduced because the Au film 7 having a low electric resistivity is used as the upper layer of the gate electrode.

However, in order to increase the output of the FET, it is important to control the gate-drain breakdown voltage. The gate-drain breakdown voltage is determined by the carrier concentration and thickness of the n-type active layer and the recess shape, but the carrier concentration and thickness of the active layer are almost determined by the electrical characteristics required for the FET. In the conventional manufacturing method described above, the recess width is determined by the gate length and the width of the SiO 2 side wall, and the range of change is also limited. Therefore, the control range of the gate-drain breakdown voltage is also limited.

[0006]

In the above-described conventional FET manufacturing method, the control range of the gate-drain breakdown voltage is limited. Further, in order to improve the gate-drain breakdown voltage, it is necessary to widen the recess width, but in this case, the area of the active layer with a small layer thickness under the recess becomes wide,
The source resistance and drain resistance increase, which reduces the transconductance.

In view of the above problems, it is an object of the present invention to improve the controllability of the gate-drain breakdown voltage and to improve the gate-drain breakdown voltage without significantly reducing the transconductance. Is.

[0008]

In a method of manufacturing a semiconductor device according to the present invention (claim 1), a first insulating film should be formed on a main surface of a semiconductor substrate, and a first recess thereof should be formed. Removing a portion corresponding to a portion to form an opening, and using the first insulating film as a mask to form a first recess in the semiconductor substrate through the opening,
A second insulating film is formed on the entire surface, the second insulating film is etched back, and the second insulating film is formed on the inner surface of the opening of the first insulating film and the inner surface of the first recess of the semiconductor substrate. Forming a side wall of an insulating film made of an insulating film, forming a heat resistant gate material film and a low resistance metal film on the entire surface, and including the first recess opening on the low resistance metal film. A step of forming a resist for forming a gate in a region where a large second recess opening is to be formed, a step of etching the low resistance metal film and the heat resistant gate material film using the resist as a mask, and a step of leaving the resist under the resist. The side surface of the heat resistant gate material film is etched using the low resistance metal film as a mask so that the width of the heat resistant gate material film is narrower than the width of the low resistance metal film. Low resistance metal Forming a gate electrode made of,
A step of removing the first insulating film, a step of forming a coating film on a main surface of the semiconductor substrate under a region of the low resistance metal film except a second recess forming region, and the coating film And, using the gate electrode and the sidewall of the insulating film as a mask, digging a second recess having a depth shallower than the first recess in the second recess forming region of the semiconductor substrate.

A method of manufacturing a semiconductor device according to the present invention (claim 2) is a method of manufacturing the above semiconductor device (claim 1).
In the step of forming the coating film, after applying a resist for forming a second recess, which becomes insoluble in a developing solution by irradiation of light, on the entire surface of the semiconductor substrate including the gate electrode, Removing the upper layer of the low resistance metal film until the portion of the low resistance metal film located outside the heat resistant gate material film is located on the surface of the resist, and exposing the entire surface of the semiconductor substrate including the gate electrode. After irradiating with light, the resist is developed, and only the resist located under the exposed portion of the low resistance metal film is removed.

A method of manufacturing a semiconductor device according to the present invention (claim 3) is a method of manufacturing the above semiconductor device (claim 1).
In the step of forming the coating film, the step of depositing a second recess forming insulating film on the entire surface by using an ECR plasma CVD method, and the step of forming a film outside the heat resistant gate material film of the low resistance metal film. The method for manufacturing a semiconductor device according to the present invention (Claim 4) is the method for manufacturing a semiconductor device according to the above (Claim 4). In the item 1), the step of forming the coating film is to deposit the coating film on the entire surface of the semiconductor substrate including the gate electrode by using a vacuum deposition method.

A method of manufacturing a semiconductor device according to the present invention (claim 5) is a method of manufacturing the above semiconductor device (claim 4).
In the above, the coating film is a metal film.

A method of manufacturing a semiconductor device according to the present invention (claim 6) is a method of manufacturing the above semiconductor device (claim 5).
In the above, the metal film is a metal film to be a source electrode and a drain electrode.

A method of manufacturing a semiconductor device according to the present invention (claim 7) is a method of manufacturing the above semiconductor device (claim 4).
In the above, the coating film is an insulating film.

A method for manufacturing a semiconductor device according to the present invention (claim 8) is a method for manufacturing the above semiconductor device (claim 1).
In, after the step of etching the low resistance metal film and the heat resistant gate material film with the gate forming resist as a mask, the side surface of the heat resistant gate material film is etched with the remaining low resistance metal film as a mask. Before the step of forming the gate electrode made of the heat resistant gate material and the low resistance metal, one side surface of the low resistance metal film and the heat resistant gate material film and the first insulating layer adjacent to the side surface. The method includes the step of forming a resist that serves as an etching mask of the first insulating film so as to cover a certain region on the film, and the step of removing the first insulating film includes the step of removing the first insulating film. The first insulating film is removed by etching in a region other than the region where the resist serving as the mask for etching the insulating film is formed.

A method of manufacturing a semiconductor device according to the present invention (claim 9) is a method of manufacturing the above semiconductor device (claim 8).
In the step of forming the coating film, after applying a resist for forming a second recess, which becomes insoluble in a developing solution by irradiation of light, on the entire surface of the semiconductor substrate including the gate electrode, Removing the upper layer of the low resistance metal film until the portion of the low resistance metal film located outside the heat resistant gate material film is located on the surface of the resist, and exposing the entire surface of the semiconductor substrate including the gate electrode. After irradiating with light, the resist is developed, and only the resist located under the exposed portion of the low resistance metal film is removed.

According to the method of manufacturing a semiconductor device (claim 10) of the present invention, in the method of manufacturing a semiconductor device (claim 8), the step of forming the coating film uses an ECR plasma CVD method. From the step of depositing the second recess forming insulating film on the entire surface and the step of etching away the insulating film located under the portion of the low resistance metal film outside the heat resistant gate material film. It will be.

A method of manufacturing a semiconductor device according to the present invention (claim 11) is the same as the method of manufacturing a semiconductor device (claim 8), wherein the step of forming the coating film is performed by using a vacuum deposition method. The coating film is deposited on the entire surface of the semiconductor substrate including the gate electrode.

A method of manufacturing a semiconductor device according to the present invention (claim 12) is a method of manufacturing the above semiconductor device (claim 1).
In 1), the coating film is a metal film.

A method for manufacturing a semiconductor device according to the present invention (claim 13) is a method for manufacturing a semiconductor device as described above (claim 1).
In 1), the coating film is an insulating film.

[0020]

In the method of manufacturing the FET according to the present invention,
A second recess, which is shallower than the first recess, is formed outside the first recess formed in the same manner as the conventional recess forming method described above, in a region below a gate electrode upper layer made of a low resistance metal. Therefore, the width of the second recess can be changed by changing the width of the upper layer of the gate electrode, and the controllability of the gate-drain breakdown voltage is improved. Further, since the second recess is shallower than the first recess, the thickness of the active layer under the second recess becomes thicker than the thickness of the active layer under the first recess, and when the recess width is widened by the conventional method. Compared with, the gate-drain breakdown voltage can be improved without significantly reducing the transconductance. Furthermore, since the formation of the second recess is performed subsequent to the formation of the gate electrode and utilizing the gate electrode structure, the process is simplified.

In the method of manufacturing an FET according to the present invention (claim 1), the first insulating film is formed on the main surface of the semiconductor substrate, and the portion corresponding to the portion where the first recess is to be formed is removed. To form an opening, a step of forming a first recess in the semiconductor substrate through the opening using the first insulating film as a mask, and forming a second insulating film on the entire surface. Etching back the second insulating film, and forming an insulating film sidewall made of the second insulating film on the inner surface of the opening of the first insulating film and the inner surface of the first recess of the semiconductor substrate. And a step of forming a heat resistant gate material film and a low resistance metal film on the entire surface, and a second recess opening larger than this including the first recess opening on the low resistance metal film should be formed. The step of forming a resist for forming a gate in the region, and A step of etching the low resistance metal film and the heat resistant gate material film as a mask, and using the low resistance metal film left under the resist as a mask to make the side surface of the heat resistant gate material film the heat resistant gate material film. Etching to have a width narrower than the width of the low resistance metal film to form a gate electrode made of the heat resistant gate material and the low resistance metal; and a step of removing the first insulating film, Forming a coating film on a region of the main surface of the semiconductor substrate below the low-resistance metal film except the second recess forming region, and using the coating film, the gate electrode and the insulating film sidewall as a mask , The second of the semiconductor substrate
Since the second recess having a shallower depth than the first recess is formed in the recess formation region, the width of the second recess can be changed by changing the width of the upper layer of the gate electrode made of the low resistance metal film. It can be changed, and the controllability of the gate-drain breakdown voltage is improved. Further, since the second recess is shallower than the first recess, the thickness of the active layer under the second recess becomes thicker than the thickness of the active layer under the first recess,
As compared with the case where the recess width is widened by the conventional method, the gate-drain breakdown voltage can be improved without significantly lowering the mutual conductance. Furthermore, since the formation of the second recess is performed subsequent to the formation of the gate electrode and utilizing the gate electrode structure, the process is simplified.

According to the method of manufacturing an FET (claim 2) of the present invention, in the method of manufacturing an FET (claim 1), the step of forming the coating film is performed by irradiating light with respect to a developing solution. An insoluble second recess forming resist is applied to the entire surface of the semiconductor substrate including the gate electrode, and then the upper layer of the resist is removed to expose the low resistance metal film outside the heat resistant gate material film. Exposing the exposed portion until the positioned portion is positioned on the surface of the resist, and irradiating the entire surface of the semiconductor substrate including the gate electrode with light, and then developing the resist to expose the low resistance metal film. Since the step of removing only the resist located underneath is performed, when the upper layer of the resist for forming the second recess is removed and then the entire surface is irradiated with light, the gate electrode is removed. The said heat-resistant resist under region outside the gate material film of the upper layer of low-resistance metal film, is shielded by the low-resistance metal film, the light is not irradiated. Therefore, only the resist in the region not irradiated with this light is removed by the development. In this way, the resist mask for the second recess forming etching can be formed by a simple process. Further, the width of the second recess can be changed by changing the width of the upper layer of the gate electrode made of the low resistance metal film, and the controllability of the gate-drain breakdown voltage is improved. Further, since the second recess is shallower than the first recess, the thickness of the active layer under the second recess becomes thicker than the thickness of the active layer under the first recess, and when the recess width is widened by the conventional method. Compared with, the gate-drain breakdown voltage can be improved without significantly reducing the transconductance.

In the method of manufacturing an FET according to the present invention (claim 3), in the method of manufacturing an FET (claim 1), the step of forming the coating film is performed by ECR plasma CV.
A step of depositing a second recess forming insulating film on the entire surface by using the D method, and etching the insulating film located under the portion of the low resistance metal film outside the heat resistant gate material film. It consists of the process of removing,
The film quality of the insulating film on the semiconductor substrate in the side surface of the gate electrode and the region under the low resistance metal film outside the heat resistant gate material film is
It is weaker than the film quality of the insulating film in other regions and is more likely to be etched. Therefore, the etching time can be set so that only the insulating film in this region is etched. In this way, the mask made of the insulating film for the second recess forming etching can be formed by a simple process. Further, the width of the second recess can be changed by changing the width of the upper layer of the gate electrode made of the low resistance metal film, and the controllability of the gate-drain breakdown voltage is improved. Further, since the second recess is shallower than the first recess, the thickness of the active layer under the second recess becomes thicker than the thickness of the active layer under the first recess, and when the recess width is widened by the conventional method. Compared with, the gate-drain breakdown voltage can be improved without significantly reducing the transconductance.

According to the method for producing an FET (claim 4) of the present invention, in the method for producing an FET (claim 1), the step of forming the coating film is performed by using a vacuum deposition method to form the coating film. Since the film is to be deposited on the entire surface of the semiconductor substrate including the gate electrode, when the substance to be the coating film is made to enter perpendicularly to the semiconductor substrate, the outside of the heat-resistant gate material film is The coating film is not deposited on the semiconductor substrate in the region below the low resistance metal film. This is because in the vacuum deposition method, the incident directions of atoms or molecules of the substance to be the coating film are aligned. In this method, a mask made of the coating film for the second recess forming etching can be formed by a simple process of only depositing the coating film. In addition, by changing the width of the gate electrode upper layer made of a low resistance metal film,
The width of the second recess can be changed, and the controllability of the gate-drain breakdown voltage is improved. Further, since the second recess is shallower than the first recess, the thickness of the active layer under the second recess becomes thicker than the thickness of the active layer under the first recess, and when the recess width is widened by the conventional method. Compared with, the gate-drain breakdown voltage can be improved without significantly reducing the transconductance.

A method for manufacturing an FET according to the present invention (claim 5) is a metal film in the above method for manufacturing an FET (claim 4) because the coating film is a metal film. When the substance is made to enter the semiconductor substrate perpendicularly, the metal film is not deposited on the semiconductor substrate in the region under the low resistance metal film outside the heat resistant gate material film.
This is because the vacuum evaporation method is used as described above. In this method, the mask made of the metal film for the second recess forming etching can be formed by a simple process of only depositing the metal film. Further, the width of the second recess can be changed by changing the width of the upper layer of the gate electrode made of the low resistance metal film, and the controllability of the gate-drain breakdown voltage is improved. Further, since the second recess is shallower than the first recess, the thickness of the active layer under the second recess becomes thicker than the thickness of the active layer under the first recess, and when the recess width is widened by the conventional method. Compared with, the gate-drain breakdown voltage can be improved without significantly reducing the transconductance.

According to a method of manufacturing an FET (Claim 6) according to the present invention, in the above method of manufacturing an FET (Claim 5), the metal film is a metal film to be a source electrode and a drain electrode. Therefore, this metal film is not deposited on the semiconductor substrate in the region under the low resistance metal film outside the heat resistant gate material film. According to this method, not only can the mask of the second recess formation etching metal film be formed only by depositing the metal film, but this metal film can be used as the source and drain electrodes as it is. Becomes Further, the width of the second recess can be changed by changing the width of the upper layer of the gate electrode made of the low resistance metal film, and the controllability of the gate-drain breakdown voltage is improved. Further, since the second recess is shallower than the first recess, the thickness of the active layer under the second recess becomes thicker than the thickness of the active layer under the first recess, and when the recess width is widened by the conventional method. Compared with, the gate-drain breakdown voltage can be improved without significantly reducing the transconductance.

A method for manufacturing an FET according to the present invention (claim 7) is an insulating film in the above method for manufacturing an FET (claim 4) because the coating film is an insulating film. When the substance is made to enter perpendicularly to the semiconductor substrate, the insulating film is not deposited on the semiconductor substrate in the region under the low resistance metal film outside the heat resistant gate material film.
This is because the vacuum evaporation method is used as described above. With this method, a mask made of the insulating film for the second recess forming etching can be formed by a simple process of only depositing the insulating film. Further, the width of the second recess can be changed by changing the width of the upper layer of the gate electrode made of the low resistance metal film, and the controllability of the gate-drain breakdown voltage is improved. Further, since the second recess is shallower than the first recess, the thickness of the active layer under the second recess becomes thicker than the thickness of the active layer under the first recess, and when the recess width is widened by the conventional method. Compared with, the gate-drain breakdown voltage can be improved without significantly reducing the transconductance.

A method for manufacturing an FET according to the present invention (claim 8) is the same as the method for manufacturing an FET (claim 1), wherein the resist for gate formation is used as a mask to form the low resistance metal film and the heat resistant gate material. After the step of etching the film, before the step of etching the side surface of the heat resistant gate material film using the remaining low resistance metal film as a mask to form a gate electrode made of the heat resistant gate material and the low resistance metal A side surface of the low resistance metal film and the heat resistant gate material film and the first side surface adjacent to the side surface.
And a step of forming a resist that serves as an etching mask for the first insulating film so as to cover a certain region on the insulating film, and the step of removing the first insulating film includes the step of removing the first insulating film. Since the first insulating film in the region other than the region where the resist serving as the etching mask of the first insulating film is formed is removed by etching, the second recess is the first insulating film of the gate electrode. Is formed only on the side opposite to the remaining side. When the second recess is formed only on the drain side by using this method, the gate-drain breakdown voltage is improved without increasing the source resistance, that is, without lowering the mutual conductance in the saturation region of the drain current. You can Further, the width of the second recess can be changed by changing the width of the upper layer of the gate electrode made of the low resistance metal film, and the controllability of the gate-drain breakdown voltage is improved.

According to a method of manufacturing an FET (claim 9) of the present invention, in the method of manufacturing an FET (claim 8), the step of forming the coating film is performed by irradiating light with respect to a developing solution. An insoluble second recess forming resist is applied to the entire surface of the semiconductor substrate including the gate electrode, and then the upper layer of the resist is removed to expose the low resistance metal film outside the heat resistant gate material film. Exposing the exposed portion until the positioned portion is positioned on the surface of the resist, and irradiating the entire surface of the semiconductor substrate including the gate electrode with light, and then developing the resist to expose the low resistance metal film. Since the step of removing only the resist located underneath is performed, when the upper layer of the resist for forming the second recess is removed and then the entire surface is irradiated with light, the gate electrode is removed. The said heat-resistant resist under region outside the gate material film of the upper layer of low-resistance metal film, is shielded by the low-resistance metal film, the light is not irradiated. Therefore, only the resist in the region not irradiated with this light is removed by the development. In this way, the resist mask for the second recess forming etching can be formed by a simple process. However, since the first insulating film is left on the substrate on one side of the gate electrode, the second recess is formed only on the side opposite to the side of the gate electrode on which the first insulating film is left. It When the second recess is formed only on the drain side by using this method, the source resistance is not increased and
That is, the gate-drain breakdown voltage can be improved without lowering the mutual conductance in the saturation region of the drain current. Further, the width of the second recess can be changed by changing the width of the upper layer of the gate electrode made of the low resistance metal film, and the controllability of the gate-drain breakdown voltage is improved.

In the method of manufacturing an FET according to the present invention (claim 10), the step of forming the coating film in the method of manufacturing an FET (claim 8) is the ECR plasma CV.
A step of depositing a second recess forming insulating film on the entire surface by using the D method, and etching the insulating film located under the portion of the low resistance metal film outside the heat resistant gate material film. It consists of the process of removing,
The film quality of the insulating film on the semiconductor substrate in the side surface of the gate electrode and the region under the low resistance metal film outside the heat resistant gate material film is
It is weaker than the film quality of the insulating film in other regions and is more likely to be etched. Therefore, the etching time can be set so that only the insulating film in this region is etched. In this way, the mask made of the insulating film for the second recess forming etching can be formed by a simple process. However, since the first insulating film is left on the substrate on one side of the gate electrode, the second recess is formed only on the side opposite to the side of the gate electrode on which the first insulating film is left. It When the second recess is formed only on the drain side by using this method, the gate-drain breakdown voltage is improved without increasing the source resistance, that is, without lowering the mutual conductance in the saturation region of the drain current. You can Further, the width of the second recess can be changed by changing the width of the upper layer of the gate electrode made of the low resistance metal film, and the controllability of the gate-drain breakdown voltage is improved.

According to a method of manufacturing an FET (Claim 11) according to the present invention, in the method of manufacturing an FET (Claim 8), the step of forming the coating film is performed by using a vacuum deposition method. Since the film is to be deposited on the entire surface of the semiconductor substrate including the gate electrode, when the substance to be the coating film is made to enter perpendicularly to the semiconductor substrate, the outside of the heat-resistant gate material film is The coating film is not deposited on the semiconductor substrate in the region below the low resistance metal film. This is because in the vacuum deposition method, the incident directions of atoms or molecules of the substance to be the coating film are aligned. In this method, a mask made of the coating film for the second recess forming etching can be formed by a simple process of only depositing the coating film. However, since the first insulating film is left on the substrate on one side of the gate electrode, the second recess is formed only on the side opposite to the side of the gate electrode on which the first insulating film is left. It When the second recess is formed only on the drain side by using this method, the gate-drain breakdown voltage is improved without increasing the source resistance, that is, without lowering the mutual conductance in the saturation region of the drain current. You can Further, the width of the second recess can be changed by changing the width of the upper layer of the gate electrode made of the low resistance metal film, and the controllability of the gate-drain breakdown voltage is improved.

A method of manufacturing an FET according to the present invention (claim 12) is a metal film in the above method of manufacturing an FET (claim 11), since the coating film is a metal film. When the substance is made to enter the semiconductor substrate perpendicularly, the metal film is not deposited on the semiconductor substrate in the region under the low resistance metal film outside the heat resistant gate material film. This is because the vacuum evaporation method is used as described above. In this method, the mask made of the metal film for the second recess forming etching can be formed by a simple process of only depositing the metal film. However, since the first insulating film is left on the substrate on one side of the gate electrode, the second recess is formed only on the side opposite to the side of the gate electrode on which the first insulating film is left. It Using this method, the second
If the recess is formed only on the drain side, the gate-drain breakdown voltage can be improved without increasing the source resistance, that is, without lowering the mutual conductance in the saturation region of the drain current. Further, the width of the second recess can be changed by changing the width of the upper layer of the gate electrode made of the low resistance metal film, and the controllability of the gate-drain breakdown voltage is improved.

A method of manufacturing an FET according to the present invention (claim 13) is an insulating film, since the coating film is an insulating film in the method of manufacturing an FET (claim 11). When the substance is made to enter perpendicularly to the semiconductor substrate, the insulating film is not deposited on the semiconductor substrate in the region under the low resistance metal film outside the heat resistant gate material film. This is because the vacuum evaporation method is used as described above. With this method, a mask made of the insulating film for the second recess forming etching can be formed by a simple process of only depositing the insulating film. However, since the first insulating film is left on the substrate on one side of the gate electrode, the second recess is formed only on the side opposite to the side of the gate electrode on which the first insulating film is left. It Using this method, the second
If the recess is formed only on the drain side, the gate-drain breakdown voltage can be improved without increasing the source resistance, that is, without lowering the mutual conductance in the saturation region of the drain current. Further, the width of the second recess can be changed by changing the width of the upper layer of the gate electrode made of the low resistance metal film, and the controllability of the gate-drain breakdown voltage is improved.

[0034]

【Example】

Example 1. A method of manufacturing the FET, which is the first embodiment of the present invention, will be described. First, the steps of the method of manufacturing the FET of this embodiment will be described with reference to FIG. Figure 1 (a) to (e)
The process of forming the first recess and the gate electrode up to
This is exactly the same as the conventional method shown in FIGS. 8 (a) to 8 (e). That is, first, as shown in FIG.
Semi-insulating G having an n-type active layer 20 formed on its surface
An insulating film such as a SiO film 2 having a film thickness of about 200 nm is formed on the aAs substrate 1, and a resist 3 is further formed. Next, the SiO film under the opening of the resist 3 is removed by RIE or the like, and the exposed GaAs surface is etched to a depth of 20.
A first recess 4 having a width of 0 nm and a width of about 0.8 μm is formed. After that, as shown in FIG. 1B, the resist 3 is removed, an SiO film having a film thickness of about 500 nm is formed on the entire surface, and then an SiO 2 side wall 5 is formed by etching back. The width of this side wall is about 200 nm. Next, as shown in FIG. 1 (c), a WSi film 6 (film thickness of about 200 n
m), an Au film 7 (a film thickness of about 400 to 50) which is a low resistance metal.
0 nm) and a resist 8 is formed on the region to be the T-type gate electrode. Thereafter, as shown in FIG. 1D, Au7 is etched using the resist 8 as a mask, and WSi6 is further etched. Next, as shown in FIG. 1 (e), the side surface of the WSi 6 is etched using the Au film 7 as a mask so as to be narrower than the Au film 7 by using plasma etching or the like, and then the resist 8 and the SiO film 2 are removed. Remove. As a result, the S formed on the inner surface of the first recess 4
T-type gate electrode 9 composed of two layers, iO side wall 5, WSi film layer 6 (gate lower layer) formed inside thereof, and Au film layer 7 (gate upper layer) formed thereon wider than WSi film layer 6 Is formed. At this time, the gate length is 0.4 μm, which is twice the width of the SiO 2 sidewall 5 from the first recess width of 0.8 μm.
The value obtained by subtracting m, that is, 0.4 μm. Next, Fig. 1 (f)
As shown in FIG. 5, the image reversal resist 10 is applied to the entire surface and the resist upper layer is removed by a method such as etch back so that the T-type gate upper layer is exposed above the resist surface (dotted line in the figure). At this time, the resist thickness remaining on the substrate surface is about 300 to 400 nm. A negative resist may be used instead of the image reversal resist. Next, the entire surface is exposed and then developed. At this time, as shown in FIG. 1 (g), the T-type gate upper layer serves as a mask, and only the resist in the region directly below the gate upper layer which is not irradiated with light (unexposed) is removed, and the resist 11 is formed in the other regions. Remains. GaA in the area where this resist is removed
The s substrate is etched to form a second recess as shown in FIG. At this time, the depth of the second recess is 100.
It is set to about nm so that it is shallower than the first recess.
After that, the resist 11 is removed. Further, as shown in FIG. 1 (i), the SiO side wall 5 may be removed. Finally,
As shown in FIG. 1J, the source / drain electrodes 21 and the passivation film 22 are formed to complete the FET.

Next, the operation and effect of the method of manufacturing the FET of this embodiment will be described. As described above, in this embodiment, a fine two-step recess shape, which is difficult to obtain by ordinary photolithography, can be obtained by a simple process. Further, the width of the second recess can be changed by changing the width of the upper layer of the gate electrode made of the Au film, and the controllability of the gate-drain breakdown voltage is improved. In addition, the second recess is the first
Since the thickness of the active layer under the second recess is thicker than the thickness of the active layer under the first recess, the transconductance is significantly larger than that when the recess width is widened by the conventional method. The gate-drain breakdown voltage can be improved without lowering the voltage. If the source and drain electrodes are formed before the gate is formed, the two-step recess can be formed while monitoring the gate breakdown voltage.

Example 2. It is a second embodiment of the present invention,
A method of manufacturing the FET will be described. First, the steps of the method for manufacturing the FET of this embodiment will be described with reference to FIG. First, the first recess and the T-type gate as shown in FIG. 2A are formed by using the same steps as FIGS. 1A to 1E described in the first embodiment. Next, as shown in FIG. 2B, an SCR having a film thickness of about 300 to 400 nm is formed by the ECR plasma CVD method.
The iO film 13 is formed. As a property of the film by the ECR plasma CVD method, the film attached to the side surface and the shadow behind the obstacle is
It is known to be fragile and susceptible to etching.
Utilizing this property, an etching solution such as hydrofluoric acid
As shown in FIG. 2C, the SiO film 13 on the side surface of the T-type gate electrode and the substrate surface immediately below the upper layer of the T-type gate electrode can be removed. At this time, the etching time is set so that the SiO film deposited on the region other than the above region remains.
Next, as shown in FIG. 2D, the exposed GaAs substrate immediately below the upper layer of the T-type gate electrode is etched to form a second recess. At this time, the depth of the second recess is set to about 100 nm so as to be shallower than that of the first recess. After that, the remaining SiO film 13 is removed by etching. Further, the SiO side wall 5 may be removed. Finally, the source and drain electrodes are formed and the passivation film is formed to complete the FET.

Next, the operation and effect of the method of manufacturing the FET of this embodiment will be described. As described above, the mask made of the SiO film for the second recess forming etching can be formed by a simple process. Further, the width of the second recess can be changed by changing the width of the upper layer of the gate electrode made of the low resistance metal film, and the controllability of the gate-drain breakdown voltage is improved. Further, since the second recess is shallower than the first recess, the thickness of the active layer under the second recess becomes thicker than the thickness of the active layer under the first recess, and when the recess width is widened by the conventional method. Compared with, the gate-drain breakdown voltage can be improved without significantly reducing the transconductance.

Example 3. F which is the third embodiment of the present invention
A method of manufacturing ET will be described. First, F of this embodiment
The steps of the ET manufacturing method will be described with reference to FIG. First, a first recess and a T-type gate as shown in FIG. 1E are manufactured by using the same steps as FIGS. 1A to 1E described in the first embodiment. Next, as shown in FIG. 3A, a coating film 14 made of a metal or an insulator that can easily remove Ti, Al, SiO, etc. is deposited by a vacuum evaporation method. The film thickness of this coating film is about 300 to 400 nm. In the vacuum deposition method, the incident directions of the deposits are aligned, so if this incident direction is perpendicular to the substrate, the coating film is not deposited on the substrate immediately below the upper layer of the T-type gate electrode and the GaAs is not deposited. The substrate surface remains exposed. Here, as shown in FIG. 3B, the second recess 1 is formed only on the exposed substrate surface by performing the etching for forming the second recess.
2 is formed. At this time, the depth of the second recess is 100.
It is set to about nm so that it is shallower than the first recess.
After that, the coating film 14 is removed by etching. Further, the SiO side wall 5 may be removed. Finally, the source and drain electrodes are formed and the passivation film is formed to complete the FET.

Next, the operation and effect of the method of manufacturing the FET of this embodiment will be described. As described above, in this embodiment, the mask made of the coating film for the second recess forming etching can be formed only by depositing the coating film, and the steps are simpler than those of the methods shown in the first and second embodiments. Be converted. Further, the width of the second recess can be changed by changing the width of the upper layer of the gate electrode made of the low resistance metal film, and the controllability of the gate-drain breakdown voltage is improved. Further, since the second recess is shallower than the first recess, the thickness of the active layer under the second recess becomes thicker than the thickness of the active layer under the first recess, and when the recess width is widened by the conventional method. Compared with, the gate-
The drain breakdown voltage can be improved. However, when a metal film is used as the coating film, it becomes difficult to monitor the gate breakdown voltage during etching for forming the second recess.

Example 4. It is a fourth embodiment of the present invention,
A method of manufacturing the FET will be described. First, the steps of the method for manufacturing the FET of this embodiment will be described with reference to FIG. In this embodiment, the coating film in the third embodiment is a metal film to be the source and drain electrodes. Since the vacuum evaporation method is used as in Example 3, as shown in FIG.
The metal film 15 serving as the source and drain electrodes is not deposited on the substrate immediately below the upper layer of the mold gate electrode, and the GaAs substrate surface can be left exposed. Here, by performing etching for forming the second recess, as shown in FIG.
As shown in (b), the second recess 12 is formed only on the exposed substrate surface. At this time, the depth of the second recess is set to about 100 nm so as to be shallower than that of the first recess. Further, the SiO sidewall 5 may be removed. Finally, the source and drain electrodes are formed and the passivation film is formed to complete the FET.

Next, the operation and effect of the method of manufacturing the FET of this embodiment will be described. In this embodiment, the metal film 15 serves as the source and drain electrodes as it is, and it is not necessary to remove the metal film. Therefore, the number of steps is further reduced as compared with the method shown in the third embodiment. Further, the width of the second recess can be changed by changing the width of the upper layer of the gate electrode made of the low resistance metal film, and the controllability of the gate-drain breakdown voltage is improved. Further, since the second recess is shallower than the first recess, the thickness of the active layer under the second recess becomes thicker than the thickness of the active layer under the first recess, and when the recess width is widened by the conventional method. Compared with, the gate-drain breakdown voltage can be improved without significantly reducing the transconductance.

Example 5. It is a fifth embodiment of the present invention,
A method of manufacturing the FET will be described. First, the steps of the method for manufacturing the FET of this embodiment will be described with reference to FIG. First, the Au film 7 and the WSi film 6 for forming the first recess 4 and the T-type gate are formed using the same steps as those in FIGS. 1A to 1D described in the first embodiment. Etching up to the same width is performed. Next, the resist 8 is removed, and as shown in FIG. 5A, a resist 16 is formed so as to cover one side surface of the gate electrode and a certain region on the SiO film 2 adjacent to this side surface. Further, as in the first embodiment, the side surface of the heat resistant gate material film 6 is etched using the low resistance metal film 7 as a mask. However, at this time, the side surface of the heat-resistant gate material film 6 on the side masked by the resist 16 is not etched. Next, using this resist 16 as a mask, the SiO film 2
After etching, the resist 16 is removed. As a result, only the SiO film under the resist 16 remains on the GaAs substrate. The following steps are exactly the same as the method using the image reversal resist described in the first embodiment. That is, as shown in FIG. 5 (b), the image reversal resist 10 is applied to the entire surface, and the resist upper layer is removed by a method such as etch back so that the T-type gate upper layer is located above the resist surface (dotted line in the figure). Make it exposed. At this time, the resist thickness remaining on the substrate surface is about 300 to 400 nm. A negative resist may be used instead of the image reversal resist. Next, after exposing the entire surface,
develop. At this time, as shown in FIG. 5 (c), the T-type gate upper layer serves as a mask, and only the resist in the region immediately below the gate upper layer which is not irradiated with light (unexposed) is removed.
The resist 11 remains in the other regions. The GaAs substrate surface in the region where the resist is removed is exposed, but the substrate surface in the region where the SiO film 2 is left is not exposed. Therefore, the second recess is formed in the next GaAs etching step only in the region adjacent to the side surface of the gate electrode where the SiO film 2 is not left. That is, as shown in FIG. 5D, the second recess is formed only on one side of the gate electrode. At this time, the depth of the second recess is set to about 100 nm so as to be shallower than that of the first recess. After this, the resist 11 and the remaining S
The iO film 2 is removed. Further, the SiO sidewall 5 may be removed. Finally, the source and drain electrodes are formed and the passivation film is formed to complete the FET.

Next, the operation and effect of the method of manufacturing the FET of this embodiment will be described. As described above, in this embodiment, the Si used as the mask for forming the first recess is used.
By not leaving the O film 2 completely etched after forming the T-type gate electrode, but leaving it in a certain region on one side of the T-type gate electrode, this can be used together with the image reversal resist to form the second recess. With the etching as a mask, the second recess is formed only on the side of the T-type gate electrode opposite to the side where the SiO film is left. When the second recess is formed only on the drain side of the gate electrode by using this method, the gate-drain breakdown voltage is increased without increasing the source resistance, that is, without decreasing the mutual conductance in the saturation region of the drain current. Can be improved. Further, the width of the second recess can be changed by changing the width of the upper layer of the gate electrode made of the low resistance metal film, and the controllability of the gate-drain breakdown voltage is improved.

Example 6. It is a sixth embodiment of the present invention,
A method of manufacturing the FET will be described. First, the steps of the method for manufacturing the FET of this embodiment will be described with reference to FIG. First, the Au film 7 and the WSi film 6 for forming the first recess 4 and the T-type gate are formed using the same steps as those in FIGS. 1A to 1D described in the first embodiment. Etching up to the same width is performed. Next, the step of FIG. 5A described in the fifth embodiment is performed. That is, after removing the resist 8, the resist 16 is formed so as to cover one side surface of the gate electrode and a certain region on the SiO film 2 adjacent to this side surface. Further, as in the first embodiment, the side surface of the heat resistant gate material film 6 is etched using the low resistance metal film 7 as a mask. However, at this time, the side surface of the heat-resistant gate material film 6 on the side masked by the resist 16 is not etched. Next, this resist 1
After etching the SiO film 2 using 6 as a mask, the resist 16 is removed. As a result, only the SiO film under the resist 16 remains on the GaAs substrate. The following steps are exactly the same as the method using the ECR plasma CVD method described in the second embodiment. That is, as shown in FIG. 6A, a film thickness of 300 to 40 is formed by the ECR plasma CVD method.
A SiO film 13 of about 0 nm is formed. It is known that as a property of the film formed by the ECR plasma CVD method, the film attached to the side surface and behind the obstacle is fragile and easily etched. Utilizing this property, the SiO film 13 on the side surface of the T-type gate electrode and the substrate surface immediately below the upper layer of the T-type gate electrode can be removed with an etching solution such as hydrofluoric acid, as shown in FIG. 6B. At this time, the etching time is set so that the SiO film deposited on the region other than the above region remains. Next, as shown in FIG. 6C, the exposed GaAs substrate immediately below the upper layer of the T-type gate electrode is etched,
The second recess 12 is formed. However, the second recess is formed only in the region adjacent to the side surface of the gate electrode on the side where the SiO film 2 is not left. That is, as shown in FIG. 5D, the second recess is formed only on one side of the gate electrode. At this time, the depth of the second recess is 10
It is set to about 0 nm so that it is shallower than the first recess. After that, the remaining SiO film 13 and SiO film 2 are removed by etching. Further, the SiO side wall 5 may be removed. Finally, the source and drain electrodes are formed and the passivation film is formed to complete the FET.

Next, the operation and effect of the method of manufacturing the FET of this embodiment will be described. As described above, in this embodiment, the Si used as the mask for forming the first recess is used.
By not leaving the O film 2 completely etched after forming the T-type gate electrode, but leaving it in a certain region on one side of the T-type gate electrode, the O film 2 is removed together with the SiO film 2 formed by the ECR plasma CVD method. The second recess is formed only on the side of the T-type gate electrode opposite to the side where the SiO film is left, using the etching mask for forming the recess. When the second recess is formed only on the drain side of the gate electrode by using this method, the gate-drain breakdown voltage is increased without increasing the source resistance, that is, without decreasing the mutual conductance in the saturation region of the drain current. Can be improved. Further, as described above, the mask made of the SiO film for the second recess forming etching can be formed by a simple process. Further, the width of the second recess can be changed by changing the width of the gate electrode upper layer made of the low resistance metal film, and the controllability of the gate-drain breakdown voltage is improved.

Example 7. It is a seventh embodiment of the present invention,
A method of manufacturing the FET will be described. First, the steps of the method for manufacturing the FET of this embodiment will be described with reference to FIG. First, the Au film 7 and the WSi film 6 for forming the first recess 4 and the T-type gate are formed using the same steps as those in FIGS. 1A to 1D described in the first embodiment. Etching up to the same width is performed. Next, the step of FIG. 5A described in the fifth embodiment is performed. That is, after removing the resist 8, the resist 16 is formed so as to cover one side surface of the gate electrode and a certain region on the SiO film 2 adjacent to this side surface. Further, as in the first embodiment, the side surface of the heat resistant gate material film 6 is etched using the low resistance metal film 7 as a mask. However, at this time, the side surface of the heat-resistant gate material film 6 on the side masked by the resist 16 is not etched. Next, this resist 1
After etching the SiO film 2 using 6 as a mask, the resist 16 is removed. As a result, only the SiO film 2 under the resist 16 remains on the GaAs substrate. The following steps are exactly the same as the method using the vacuum evaporation method described in the third embodiment. That is, as shown in FIG. 7A, a coating film 14 made of a metal or an insulator that can easily remove Ti, Al, SiO, etc. is deposited by a vacuum evaporation method. The film thickness of this coating film is about 300 to 400 nm. In the vacuum vapor deposition method, the incident directions of the deposits are aligned, so if this incident direction is perpendicular to the substrate, the coating film is not deposited on the substrate immediately below the upper layer of the T-type gate electrode and GaA
s The substrate surface remains exposed. However, the above-mentioned SiO
The substrate surface immediately below the gate electrode upper layer on the side where the film 2 is left is naturally still covered with the SiO film 2. Here, FIG.
As shown in (b), by performing etching for forming the second recess, the second recess 12 is formed only on the exposed substrate surface on one side of the gate electrode. At this time, the depth of the second recess is about 100 nm, and
Shallower than the recess. After this, the coating film 14
Are removed by etching, and the remaining SiO film 2 is also removed. Further, the SiO side wall 5 may be removed. Finally,
The FET is completed by forming source and drain electrodes and forming a passivation film.

Next, the operation and effect of the method of manufacturing the FET of this embodiment will be described. As described above, in this embodiment, the Si used as the mask for forming the first recess is used.
The O film 2 is not completely etched after the T-shaped gate electrode is formed, but is left in a certain region on one side of the T-shaped gate electrode, so that the O-film 2 is covered by the vacuum deposition method.
At the same time, it is used as an etching mask for forming the second recess, and the second recess is formed only on the side of the T-type gate electrode opposite to the side where the coating film is left. When the second recess is formed only on the drain side of the gate electrode by using this method, the gate-drain breakdown voltage is increased without increasing the source resistance, that is, without decreasing the mutual conductance in the saturation region of the drain current. Can be improved. Further, as described above, in the present embodiment, the mask made of the coating film for the second recess forming etching can be formed only by depositing the coating film. Is simplified. Further, the width of the second recess can be changed by changing the width of the gate electrode upper layer made of the low resistance metal film, and the controllability of the gate-drain breakdown voltage is improved.

[0048]

According to the method of manufacturing an FET of the present invention (claim 1), the first insulating film is formed on the main surface of the semiconductor substrate, and the portion corresponding to the portion where the first recess is to be formed is formed. To form an opening by removing the first insulating film, a step of digging a first recess in the semiconductor substrate through the opening using the first insulating film as a mask, and a second insulating film over the entire surface. And etching back the second insulating film, and insulating film sidewalls made of the second insulating film on the inner surface of the opening of the first insulating film and the inner surface of the first recess of the semiconductor substrate. Forming a heat resistant gate material film and a low resistance metal film on the entire surface, and forming a second recess opening larger than the first recess opening on the low resistance metal film. Forming a resist for forming a gate in a region to be formed, and the resist Etching the low resistance metal film and the heat resistant gate material film as a mask, and the heat resistant gate with the side surface of the heat resistant gate material film left using the low resistance metal film left under the resist as a mask Etching so that the width of the material film is narrower than the width of the low resistance metal film to form a gate electrode made of the heat resistant gate material and the low resistance metal; and removing the first insulating film. A step of forming a coating film on a region of the main surface of the semiconductor substrate below the low-resistance metal film other than the second recess forming region, the coating film, the gate electrode and the insulating film sidewall. As a mask, a step of digging a second recess having a shallower depth than the first recess in the second recess formation region of the semiconductor substrate is included.
Controllability of the gate-drain breakdown voltage is improved. Further, as compared with the case where the recess width is widened by the conventional method, the gate-drain breakdown voltage can be improved without significantly decreasing the transconductance. Furthermore, since the formation of the second recess is performed subsequent to the formation of the gate electrode and utilizing the gate electrode structure, the process is simplified.

According to a method of manufacturing an FET (claim 2) of the present invention, in the method of manufacturing an FET (claim 1), the step of forming the coating film is performed by irradiating light with a developing solution. An insoluble second recess forming resist is applied to the entire surface of the semiconductor substrate including the gate electrode, and then the upper layer of the resist is removed to expose the low resistance metal film outside the heat resistant gate material film. Exposing the exposed portion until the positioned portion is positioned on the surface of the resist, and irradiating the entire surface of the semiconductor substrate including the gate electrode with light, and then developing the resist to expose the low resistance metal film. Since it includes a step of removing only the resist located under the bottom, the resist mask for the second recess forming etching can be formed by a simple step. Also, the controllability of the gate-drain breakdown voltage is improved. Further, as compared with the case where the recess width is widened by the conventional method, the gate-drain breakdown voltage can be improved without significantly reducing the transconductance.

In the method of manufacturing an FET according to the present invention (claim 3), in the method of manufacturing an FET (claim 1), the step of forming the coating film is performed by ECR plasma CV.
A step of depositing a second recess forming insulating film on the entire surface by using the D method, and etching the insulating film located under the portion of the low resistance metal film outside the heat resistant gate material film. It consists of the process of removing,
A mask made of the insulating film for the second recess forming etching can be formed by a simple process. Also, the controllability of the gate-drain breakdown voltage is improved. Further, as compared with the case where the recess width is widened by the conventional method, the gate-drain breakdown voltage can be improved without significantly reducing the transconductance.

According to the method of manufacturing an FET (claim 4) of the present invention, in the method of manufacturing an FET (claim 1), the step of forming the coating film is performed by using a vacuum deposition method to coat the coating film. Since the film is to be deposited on the entire surface of the semiconductor substrate including the gate electrode, the mask of the coating film for the second recess forming etching can be formed by a simple process of only depositing the coating film. Can be formed. Also, the controllability of the gate-drain breakdown voltage is improved. Further, as compared with the case where the recess width is widened by the conventional method, the gate-drain breakdown voltage can be improved without significantly reducing the transconductance.

In the method for manufacturing an FET according to the present invention (claim 5), since the coating film is a metal film in the method for manufacturing an FET (claim 4), the metal film is covered. The mask made of the metal film for the second recess forming etching can be formed by a simple process of only attaching. Also,
Controllability of the gate-drain breakdown voltage is improved. further,
As compared with the case where the recess width is widened by the conventional method, the gate-drain breakdown voltage can be improved without significantly lowering the mutual conductance.

According to a method of manufacturing an FET (Claim 6) according to the present invention, in the method of manufacturing an FET (Claim 5), the metal film is a metal film to be a source electrode and a drain electrode. From the above, not only the mask of the metal film for the second recess forming etching can be formed only by depositing the metal film, but also this metal film becomes the source and drain electrodes as it is, so that the process is further simplified. . Also, the controllability of the gate-drain breakdown voltage is improved. Further, as compared with the case where the recess width is widened by the conventional method, the gate-drain breakdown voltage can be improved without significantly reducing the transconductance.

According to the method of manufacturing an FET (Claim 7) of the present invention, in the method of manufacturing an FET (Claim 4), the coating film is an insulating film. The mask made of the metal film for the second recess forming etching can be formed by a simple process of only attaching. Also,
Controllability of the gate-drain breakdown voltage is improved. further,
As compared with the case where the recess width is widened by the conventional method, the gate-drain breakdown voltage can be improved without significantly lowering the mutual conductance.

A method of manufacturing an FET according to the present invention (claim 8) is the same as the method of manufacturing an FET (claim 1), wherein the resist for gate formation is used as a mask to form the low resistance metal film and the heat resistant gate material. After the step of etching the film, before the step of etching the side surface of the heat resistant gate material film using the remaining low resistance metal film as a mask to form a gate electrode made of the heat resistant gate material and the low resistance metal A side surface of the low resistance metal film and the heat resistant gate material film and the first side surface adjacent to the side surface.
And a step of forming a resist that serves as an etching mask for the first insulating film so as to cover a certain region on the insulating film, and the step of removing the first insulating film includes the step of removing the first insulating film. Since the first insulating film in the region other than the region where the resist serving as the etching mask of the first insulating film is formed is removed by etching, the second recess is the first insulating film of the gate electrode. Is formed only on the side opposite to the remaining side. If the second recess is formed only on the drain side by using this method, the gate-gate can be formed without reducing the transconductance in the saturation region of the drain current.
The drain breakdown voltage can be improved. Also, the controllability of the gate-drain breakdown voltage is improved.

According to the method of manufacturing a FET (claim 9) of the present invention, in the method of manufacturing a FET (claim 8), the step of forming the coating film is performed by irradiating light with respect to a developing solution. An insoluble second recess forming resist is applied to the entire surface of the semiconductor substrate including the gate electrode, and then the upper layer of the resist is removed to expose the low resistance metal film outside the heat resistant gate material film. Exposing the exposed portion until the positioned portion is positioned on the surface of the resist, and irradiating the entire surface of the semiconductor substrate including the gate electrode with light, and then developing the resist to expose the low resistance metal film. Since it includes a step of removing only the resist located under the bottom, the resist mask for the second recess forming etching can be formed by a simple step. However, since the first insulating film is left on the substrate on one side of the gate electrode, the second recess is formed only on the side opposite to the side of the gate electrode on which the first insulating film is left. It When the second recess is formed only on the drain side by using this method, the gate-drain breakdown voltage can be improved without lowering the mutual conductance in the saturation region of the drain current. Also, the controllability of the gate-drain breakdown voltage is improved.

According to the method of manufacturing an FET (claim 10) of the present invention, in the method of manufacturing an FET (claim 8), the step of forming the coating film is performed by ECR plasma CV.
A step of depositing a second recess forming insulating film on the entire surface by using the D method, and etching the insulating film located under the portion of the low resistance metal film outside the heat resistant gate material film. It consists of the process of removing,
A mask made of the insulating film for the second recess forming etching can be formed by a simple process. However, since the first insulating film is left on the substrate on one side of the gate electrode, the second recess is formed only on the side opposite to the side of the gate electrode on which the first insulating film is left. It When the second recess is formed only on the drain side by using this method, the gate-drain breakdown voltage can be improved without lowering the mutual conductance in the saturation region of the drain current. Also, the controllability of the gate-drain breakdown voltage is improved.

According to the method of manufacturing an FET (claim 11) of the present invention, in the method of manufacturing an FET (claim 8), the step of forming the coating film is performed by using a vacuum deposition method to form the coating film. Since the film is to be deposited on the entire surface of the semiconductor substrate including the gate electrode, the mask of the coating film for the second recess forming etching can be formed by a simple process of only depositing the coating film. Can be formed. However, since the first insulating film is left on the substrate on one side of the gate electrode,
The second recess is formed only on the side of the gate electrode opposite to the side where the first insulating film is left. When the second recess is formed only on the drain side by using this method, the transconductance in the saturation region of the drain current is not lowered,
The gate-drain breakdown voltage can be improved. Also, the controllability of the gate-drain breakdown voltage is improved.

A method for manufacturing an FET according to the present invention (claim 12) is the same as the method for manufacturing an FET (claim 11) described above, but since the coating film is a metal film, the metal film is covered. The mask made of the metal film for the second recess forming etching can be formed by a simple process of only attaching. However, since the first insulating film is left on the substrate on one side of the gate electrode, the second recess is formed only on the side opposite to the side of the gate electrode on which the first insulating film is left. It When the second recess is formed only on the drain side by using this method, the gate-drain breakdown voltage can be improved without lowering the mutual conductance in the saturation region of the drain current. Also, the controllability of the gate-drain breakdown voltage is improved.

According to the method for manufacturing an FET (Claim 13) of the present invention, in the above method for manufacturing an FET (Claim 11), since the coating film is an insulating film, the insulating film is covered. The mask made of the metal film for the second recess forming etching can be formed by a simple process of only attaching. However, since the first insulating film is left on the substrate on one side of the gate electrode, the second recess is formed only on the side opposite to the side of the gate electrode on which the first insulating film is left. It When the second recess is formed only on the drain side by using this method, the gate-drain breakdown voltage can be improved without lowering the mutual conductance in the saturation region of the drain current. Also, the controllability of the gate-drain breakdown voltage is improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a method of manufacturing a T-type gate and a two-step recess of an FET according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a method of manufacturing a T-type gate and a two-step recess of an FET according to the second embodiment of the present invention.

FIG. 3 is a diagram showing a method of manufacturing a T-type gate and a two-step recess of an FET according to the third embodiment of the present invention.

FIG. 4 is a diagram showing a method of manufacturing a T-type gate and a two-step recess of an FET according to the fourth embodiment of the present invention.

FIG. 5 is a diagram showing a method of manufacturing a T-type gate and a two-step recess of an FET according to the fifth embodiment of the present invention.

FIG. 6 is a view showing a method of manufacturing a T-type gate and a two-step recess of FET according to a sixth embodiment of the present invention.

FIG. 7 is a diagram showing a method of manufacturing a T-type gate and a two-step recess of an FET according to a seventh embodiment of the present invention.

FIG. 8 is a diagram showing a conventional method for manufacturing a T-type gate and a recess of an FET.

[Explanation of symbols]

1 GaAs substrate, 2 SiO film, 3 resist, 4
First recess, 5 SiO side wall, 6 WSi, 7 A
u, 8 resist, 9 T-type gate electrode, 10 image reversal resist, 11 image reversal resist after exposure and development, 12 second recess, 13 EC
SiO film by R plasma CVD method, 14 coating film (metal film or insulating film) by vacuum deposition method, 15 source,
Drain electrode metal, 16 resist, 20 n-type active layer,
21 source and drain electrodes, 22 passivation film.

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/3213

Claims (13)

[Claims] 1. A method of manufacturing a semiconductor device, wherein a first insulating film is formed on a main surface of a semiconductor substrate, and a portion corresponding to a portion where the first recess is to be formed is removed to form an opening. And a step of digging a first recess into the semiconductor substrate through the opening using the first insulating film as a mask, and forming a second insulating film on the entire surface to form the second insulating film. Etching back the film to form an insulating film side wall made of the second insulating film on the inner surface of the opening of the first insulating film and the inner surface of the first recess of the semiconductor substrate; A step of forming a heat resistant gate material film and a low resistance metal film, and a gate forming resist in a region on the low resistance metal film where a second recess opening larger than the first recess opening is to be formed. And the resist as a mask Etching the low-resistance metal film and the heat-resistant gate material film, and using the low-resistance metal film left under the resist as a mask, the side surface of the heat-resistant gate material film is formed into a width of the heat-resistant gate material film. Is etched to be narrower than the width of the low resistance metal film to form a gate electrode made of the heat resistant gate material and the low resistance metal; a step of removing the first insulating film; Forming a coating film on a region of the main surface of the substrate below the low-resistance metal film except for the second recess forming region, and using the coating film, the gate electrode and the insulating film sidewall as a mask, And a step of digging a second recess having a shallower depth than the first recess into the second recess forming region of the semiconductor substrate. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the coating film, a resist for forming a second recess that becomes insoluble in a developing solution by irradiation with light is used as the gate. After coating on the entire surface of the semiconductor substrate including electrodes, the upper layer of the resist is removed and exposed until the portion of the low resistance metal film located outside the heat resistant gate material film is located on the surface of the resist. And irradiating the entire surface of the semiconductor substrate including the gate electrode with light, developing the resist, and removing only the resist located under the exposed portion of the low resistance metal film. A method of manufacturing a semiconductor device, comprising: 3. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the coating film includes a step of depositing a second recess forming insulating film on the entire surface by using an ECR plasma CVD method. And a step of removing the insulating film located below a portion of the low resistance metal film located outside the heat resistant gate material film by etching, the method for manufacturing a semiconductor device. 4. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the coating film, the coating film is formed on the entire surface of the semiconductor substrate including the gate electrode by using a vacuum deposition method. A method of manufacturing a semiconductor device, comprising: 5. The method of manufacturing a semiconductor device according to claim 4, wherein the coating film is a metal film. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the metal film is a metal film to be a source electrode and a drain electrode. 7. The method of manufacturing a semiconductor device according to claim 4, wherein the coating film is an insulating film. 8. The method of manufacturing a semiconductor device according to claim 1, wherein after the step of etching the low resistance metal film and the heat resistant gate material film by using the resist for forming a gate as a mask, the low residual metal film is left. Before the step of etching the side surface of the heat resistant gate material film using the resistance metal film as a mask to form a gate electrode made of the heat resistant gate material and the low resistance metal, the low resistance metal film and the heat resistant gate material A step of forming a resist serving as an etching mask of the first insulating film so as to cover one side surface of the film and a certain region on the first insulating film adjacent to the side surface, The step of removing the first insulating film is performed by etching the first insulating film in a region other than a region where a resist serving as an etching mask for the first insulating film is formed. A method of manufacturing a semiconductor device, characterized in that the semiconductor device is removed by means of. 9. The method of manufacturing a semiconductor device according to claim 8, wherein in the step of forming the coating film, a resist for forming a second recess that becomes insoluble in a developing solution by irradiation with light is used as the gate. After coating on the entire surface of the semiconductor substrate including electrodes, the upper layer of the resist is removed and exposed until the portion of the low resistance metal film located outside the heat resistant gate material film is located on the surface of the resist. And irradiating the entire surface of the semiconductor substrate including the gate electrode with light, developing the resist, and removing only the resist located under the exposed portion of the low resistance metal film. A method of manufacturing a semiconductor device, comprising: 10. The method of manufacturing a semiconductor device according to claim 8, wherein the step of forming the coating film includes a step of depositing a second recess forming insulating film on the entire surface by using an ECR plasma CVD method. And a step of removing the insulating film located below a portion of the low resistance metal film located outside the heat resistant gate material film by etching, the method for manufacturing a semiconductor device. 11. The method of manufacturing a semiconductor device according to claim 8, wherein in the step of forming the coating film, the coating film is formed on the entire surface of the semiconductor substrate including the gate electrode by using a vacuum deposition method. A method of manufacturing a semiconductor device, comprising: 12. The method of manufacturing a semiconductor device according to claim 11, wherein the coating film is a metal film. 13. The method of manufacturing a semiconductor device according to claim 11, wherein the coating film is an insulating film.