JPH01125983A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01125983A JPH01125983A JP28581487A JP28581487A JPH01125983A JP H01125983 A JPH01125983 A JP H01125983A JP 28581487 A JP28581487 A JP 28581487A JP 28581487 A JP28581487 A JP 28581487A JP H01125983 A JPH01125983 A JP H01125983A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- glass
- recess
- photoresist
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000000034 method Methods 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 11
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 7
- 230000001681 protective effect Effects 0.000 claims 2
- 239000011521 glass Substances 0.000 abstract description 19
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 17
- 238000000059 patterning Methods 0.000 abstract description 12
- 239000011248 coating agent Substances 0.000 abstract description 8
- 238000000576 coating method Methods 0.000 abstract description 8
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 230000005669 field effect Effects 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000007740 vapor deposition Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 3
- 238000003486 chemical etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 235000014121 butter Nutrition 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野j
本発明は半導体装置の製造方法に関し、特にマイクロ波
帯で用いられるFETのゲート電極形成に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to the formation of a gate electrode of an FET used in a microwave band.
一般に、超高周波で用いられるGaAS電界効果トツシ
ジスタにおいては、ソース・ドレイン間の耐圧を上げる
目的でリセス構造と呼ばれる形状をしたものが多く用い
られている。第2図は従来のリセス形状を有する電界効
果トラ〉ジスタの部分拡大断面図である。In general, GaAS field effect transistors used in ultra-high frequencies often have a shape called a recessed structure for the purpose of increasing the withstand voltage between the source and drain. FIG. 2 is a partially enlarged sectional view of a conventional field effect transistor having a recessed shape.
図において、+1)はソース電極、(2)はゲート電極
、(31はドレイン電極、(4)はGaAs活性層、(
51は半絶縁性GaAS基板である。従来、リセス構造
を有するGaA、S電界効果トランジスタ電極を形成す
るために下記の工程を用いて半絶縁性GaAs基板(5
)上に形成された台形のn形GaAs活性層(41はメ
サエッチングによシ作成し、オーミック性ソース電極(
1)およびドレイン電極(3:を形成した後、リセス部
(6)およびゲート電極(21を作成するためのレジス
トパターンにて、化学エツチングによりリセス溝を作成
し、そして蒸着によりゲート電極(2)が設けられるの
である。第3図(al〜te+は従来のリセス形状を有
する電界効果トランジスタを製造する工程の一部を示す
部分拡大断面図であり、図から明らかなように、リセス
幅を所望なものとするため、リセス形成用フォトレジス
ト(7)はレジストパターンにてリセス幅に対応したパ
ターンニングを行い深さ方向に早いエツチング液を選定
し化学エツチングを行うか、あるいわドライエツチング
にてエツチングする方法がとられている。この方法でリ
セス形成を行うと、リセス幅が所望なものが得られるが
、ゲート電極形成のため、再度レジストパターンによる
ゲートのバター二〉グが必要であり、リセス溝形成後に
ゲート形成用フォトレジスト(7a)についてレジスト
コーテイシグ、ゲート形成用バターニシグが行われる。In the figure, +1) is the source electrode, (2) is the gate electrode, (31 is the drain electrode, (4) is the GaAs active layer, (
51 is a semi-insulating GaAS substrate. Conventionally, in order to form a GaA, S field effect transistor electrode having a recessed structure, a semi-insulating GaAs substrate (5
) is formed on the trapezoidal n-type GaAs active layer (41 is formed by mesa etching), and an ohmic source electrode (
After forming 1) and the drain electrode (3), a recess groove is created by chemical etching using a resist pattern for creating the recessed part (6) and the gate electrode (21), and then the gate electrode (2) is formed by vapor deposition. FIG. 3 (al to te+ are partially enlarged cross-sectional views showing a part of the process of manufacturing a field effect transistor having a conventional recessed shape. As is clear from the figure, the recess width can be adjusted to the desired width. In order to achieve this, the photoresist (7) for forming the recess is patterned with a resist pattern corresponding to the recess width, and then chemical etching is performed by selecting an etching solution that is fast in the depth direction, or dry etching is performed. A method of etching is used.If a recess is formed using this method, the desired recess width can be obtained, but in order to form a gate electrode, it is necessary to butter the gate again using a resist pattern. After forming the recess groove, resist coating and gate forming photoresist (7a) are performed.
そして、その後にゲート電極材料の蒸着等によりゲート
電極の形成が行なわれる。Thereafter, a gate electrode is formed by vapor deposition of a gate electrode material.
従来のリセス形成後のレジストコーティング、その後の
ゲートパターニングでは、通常行なわれるスピナーのレ
ジスト均一化により、リセス溝凹St−レジストが埋め
、さらにソース・ドレインを覆う様にコーティングされ
るため、リセス溝部のゲート電極形成部のレジストは厚
くなり、光学露光、現像によるレジストのゲートバター
ニングでは、マスクのゲート開口部に比べ太いレジスト
のパターンになる欠点がある。In conventional resist coating after recess formation and subsequent gate patterning, the recess groove is filled with St-resist by uniformizing the resist using a spinner, and is further coated to cover the source and drain. The resist in the gate electrode forming area becomes thick, and gate patterning of the resist by optical exposure and development has the drawback that the resist pattern becomes thicker than the gate opening of the mask.
この発明は上記のような問題点を解消するためになされ
たものであり、リセス溝形成後のレジストのゲートパタ
ーニングでもマスクのゲート開口部と同等な細いレジス
タのゲートパターニングが出来ることを目的とする。This invention was made in order to solve the above-mentioned problems, and it is an object of the present invention to enable gate patterning of a thin resistor equivalent to the gate opening of a mask even when patterning a resist gate after forming a recess groove. .
この発明に係る半導体装置の製造方法は、リセス溝形成
後に、ウェハ全面にSiN 、 SiO等のガラスコー
ティングを行いリセス溝を埋める事及び、ソース・ドレ
イシ上のガラスをエツチング除去する事により、ゲート
パターニングの際のレジスト厚みを薄くするためのもの
である。The method for manufacturing a semiconductor device according to the present invention is to perform gate patterning by coating the entire surface of the wafer with glass such as SiN, SiO, etc. to fill the recess grooves after forming the recess grooves, and etching away the glass on the source drache. This is to reduce the thickness of the resist during the process.
この発明におけるSiN 、 SiO等によるガラスコ
ーティングにょろりセス溝の埋込みによりゲートパター
ニングのためのレジスト厚さは薄く出来、光学露光、現
像によるゲートパターニングでパターの広がりを抑え、
マスクのゲート開口部同様に細いレジストのゲートパタ
ーニングが行なえる。In this invention, the thickness of the resist for gate patterning can be reduced by filling the grooves in the glass coating with SiN, SiO, etc., and the spread of the pattern can be suppressed by gate patterning by optical exposure and development.
Thin resist gate patterning can be performed in the same manner as the gate opening of the mask.
以下、この発明を図により説明する。第1図(al〜(
hlはこの発明の一実施例により半導体装置を製造する
工程の一部を示す部分拡大図であり、図において、(a
)はソース電極(1)およびドレイン電極(31が形成
された後のリセス溝を得るためのレジストパターングの
状態、(1)lはリセス溝エツチング後の状態、(0)
はリセス溝形成用フォトレジスト除去後にガラスコート
した状態、(Dlはソース・ドレイン電極部のガラス(
8;を除去し、平坦化した状態、(e)はゲートパター
ニングのためにフォトレジストコーティングしてゲート
パタ一二シグした状態、(f)はゲート形成部を開口す
るためにガラス(81のエツチングをした状態、(g)
はゲート電極(2:を蒸着等によシ形成した状態、+h
)はリフトオフにより、フォトレジスト除去した状態を
示す。この様にリセス溝部をガラスコートにて埋め、ソ
ースおよびドレイシミ極上のガラスを除去する事により
平坦化がなされ、フォトレジスト厚さを薄く出来、リセ
ス溝にフォトレジストが重なり合う場合に比べ格段に薄
いフォトレジストでゲート形成用のバターニングが出来
るため、フォトレジストのゲートパター〉はマスク同様
の細いパターンが得られ、高周波特性の良いゲート電極
が得られる。尚、ゲートのバター二〉グの後は、この開
口部よりガラスのエツチングを行い、ゲート電極を蒸着
等で形成し、フォトレジストを除去すれは良い。Hereinafter, this invention will be explained with reference to the drawings. Figure 1 (al~(
hl is a partially enlarged view showing a part of the process of manufacturing a semiconductor device according to an embodiment of the present invention;
) is the state of resist patterning to obtain the recess groove after the source electrode (1) and drain electrode (31) are formed, (1)l is the state after recess groove etching, (0)
is the state coated with glass after removing the photoresist for forming the recess groove (Dl is the glass of the source/drain electrode part (
8; is removed and flattened; (e) is a state in which photoresist is coated for gate patterning and a gate pattern is formed; (f) is a state in which glass (81) is etched to open the gate forming part. (g)
is the gate electrode (2: formed by vapor deposition etc., +h
) shows the state in which the photoresist has been removed by lift-off. In this way, by filling the recess groove with glass coat and removing the glass on the top of the source and dray stain, flattening is achieved and the thickness of the photoresist can be reduced, which is much thinner than when the photoresist overlaps the recess groove. Since the resist can be patterned for gate formation, a photoresist gate pattern can have a thin pattern similar to a mask, and a gate electrode with good high frequency characteristics can be obtained. After buttering the gate, the glass can be etched from this opening, the gate electrode can be formed by vapor deposition, and the photoresist can be removed.
以上のように、この発明によれば、リセス溝幅をコント
ロールするためリセス形成後にガラスコートにてリセス
溝を、埋め、薄いフォトレジスト膜でゲートのバターニ
ングが出来るので、細いゲート電極が形成される。いわ
ば高周波特性の良いゲート電極がリセス幅を制御しなが
ら作成出来るのである。As described above, according to the present invention, after forming the recess, the recess groove can be filled with a glass coat to control the width of the recess groove, and the gate can be patterned with a thin photoresist film, so that a thin gate electrode can be formed. Ru. In other words, a gate electrode with good high frequency characteristics can be created while controlling the recess width.
マタ、ゲートパターニング後のガラスエツチングを行っ
た後VcoaAsのエツチングを行えば、2段のリセス
が出来る。さらに、ガラスエッチ〉グを行いGaAsの
エツチングを行えば多段のリセス溝が形成出来る。この
多段リセスが最外側のリセス幅を制御した状態で行える
ため、高周波特性の良い、高耐圧のゲート電極が形成出
来る。Actually, by performing glass etching after gate patterning and then performing VcoaAs etching, a two-stage recess can be created. Furthermore, by performing glass etching and etching GaAs, multi-stage recess grooves can be formed. Since this multi-stage recess can be performed while controlling the width of the outermost recess, a gate electrode with good high frequency characteristics and high breakdown voltage can be formed.
第1図(a)〜(h)はこの発明の一実施例によシ半導
体装置を製造する工程の一部を示す部分拡大図、第2図
は従来のリセス形状を有する電界効果トランジスタの部
分拡大図、第3図(al〜(e)は従来のリセス形状を
有する電界効果トランジスタを製造する工程の一部を示
す部分拡大断面図である。
図において、(1)はソース電極、2はゲート電極、(
31はドレイン電極、(4)はn fJ GaAs活性
層、(51は半絶縁性GaAs基板、(61はリセス部
、(7)はフォトレジスト(リセス形成用) 、(7a
)はフォトレジスト(ゲート形成用) 、(81はガラ
ス(81N 、 810等)である。
なお、図中、同一符号は同一または相当部分を示す◎1(a) to 1(h) are partially enlarged views showing a part of the process of manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a portion of a conventional field effect transistor having a recessed shape. The enlarged views and FIGS. 3A to 3E are partially enlarged sectional views showing a part of the process of manufacturing a conventional field effect transistor having a recessed shape. In the figure, (1) is a source electrode, and 2 is a Gate electrode, (
31 is a drain electrode, (4) is an n fJ GaAs active layer, (51 is a semi-insulating GaAs substrate, (61 is a recessed part, (7) is a photoresist (for recess formation), (7a)
) is photoresist (for gate formation), (81 is glass (81N, 810, etc.). In the figure, the same reference numerals indicate the same or equivalent parts◎
Claims (3)
構造内部を半導体表面保護膜にて埋め戻した後に該リセ
ス構造内部を加工するためにレジストパターンを形成す
ることを特徴とする半導体装置の製造方法。(1) A semiconductor device characterized by a step of forming a recess structure in the active layer, and forming a resist pattern for processing the inside of the recess structure after backfilling the inside of the recess structure with a semiconductor surface protective film. manufacturing method.
ことを特徴とする特許請求の範囲第1項記載の半導体装
置の製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor surface protective film is of SiN or SiO type.
た後にレジストパターン形成し、該半導体表向膜をエッ
チングしたGaAs表面をエッチングする工程を1回以
上繰り返した後に電極を形成することを特徴とする半導
体装置の製造方法。(3) The electrode is formed after the steps of backfilling the inside of the recess structure with a semiconductor surface film, forming a resist pattern, and etching the GaAs surface on which the semiconductor surface film has been etched are repeated one or more times. A method for manufacturing a semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28581487A JPH01125983A (en) | 1987-11-11 | 1987-11-11 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28581487A JPH01125983A (en) | 1987-11-11 | 1987-11-11 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01125983A true JPH01125983A (en) | 1989-05-18 |
Family
ID=17696433
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP28581487A Pending JPH01125983A (en) | 1987-11-11 | 1987-11-11 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01125983A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0548013A (en) * | 1991-08-19 | 1993-02-26 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
-
1987
- 1987-11-11 JP JP28581487A patent/JPH01125983A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0548013A (en) * | 1991-08-19 | 1993-02-26 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
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