JPH06120253A - Field effect transistor and its manufacture - Google Patents

Abstract

PURPOSE:To provide a device which has a high mechanical strength of a T-shaped gate and is free of an increase in parasitic capacitance. CONSTITUTION:A hollow part 20 surrounded by a first insulating layer 18 and a second insulating layer 19 is formed in a vicinity of a support 17a of a T-shaped gate 17 to reduce parasitic capacitance. The lower face of the top wide part 17a of the T-shaped gate 17 is supported by the second insulating layer 19. This design improves the mechanical strength of the T-shaped gate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, and more particularly to a high electron mobility transistor (HEM).
It relates to a field effect transistor having a so-called T-shaped gate such as T).

[0002]

2. Description of the Related Art Conventionally, as a field effect transistor of this type, a gate electrode is formed by a lift-off method as shown in FIG. That is, as shown in FIG. 14A, a first resist 2 is applied on the semiconductor layer 1, exposed and developed to form an opening 2a, and then wet-etched with an etching solution through the opening 2a. And the recess 3 is formed. Then, a second resist 4 is patterned on the first resist 2 as shown in FIG.

Next, a metal for a gate is vapor-deposited and the metal for a gate on the second resist 4 is lifted off.
The T-shaped gate 5 as shown in FIG. 14B is formed. However, in this conventional example, since the upper wide portion 5A of the gate 5 is not held at all, the pillar 5 is physically held.
B was easily damaged, and its mechanical strength was weak as a whole.

As a countermeasure against such a problem, FIG.
A field effect transistor manufactured by the manufacturing method as shown in FIG. In this method, first, as shown in FIG. 15A, an insulating film 6 is formed on the semiconductor layer 1, and the insulating film 6 is formed.
The opening 6a is formed at a predetermined position in the same manner by using a known technique. The opening width of the opening 6a is set to the width of the pillar of the gate.

Next, the semiconductor layer 1 is formed through the opening 6a.
Then, the recess 3 is wet-etched. And in FIG.
As shown in FIG. 15A, after patterning the resist 7, a gate metal is deposited and the gate metal on the resist 7 is lifted off to form a gate 8A as shown in FIG. 15B. It FIG. 16 shows a case where an etching method is used instead of the lift-off method. A resist pattern 9 is formed on the gate metal layer 8 and the gate metal layer 8 is dried using the resist pattern 9 as a mask. By etching, FIG.
A gate similar to that of (B) can be formed.

[0006]

However, the gate 8A of such a field effect transistor has the structure shown in FIG.
As shown in (B), since the space under the upper wide portion 8a of the gate 8A is filled with the insulating film 6, the mechanical strength of the gate is increased, but the parasitic capacitance C is increased and the high frequency characteristics of the field effect transistor are improved. There is a problem that lowers it.

Further, in the above-described conventional example, the width of the recess 3 is uniquely determined by the opening width of the first resist 2 or the insulating film 6. There was a problem that I could not get the degree of freedom.

The present invention was devised in view of such conventional problems and has the mechanical strength of a T-shaped gate and suppresses an increase in parasitic capacitance of the gate portion. A field effect transistor having improved controllability of the gate recess width is obtained.

[0009]

Therefore, according to the invention of claim 1, in a field effect transistor having a T-shaped gate electrode composed of a pillar portion and a wide portion, the vicinity of the pillar portion is hollow, and Supporting the lower part of the wide part with an insulator is the solution.

According to a second aspect of the present invention, a first semiconductor layer is formed on the semiconductor layer.
An insulating layer and a second insulating layer are sequentially laminated, and on the second insulating layer,
A positive opening resist and a negative opening resist are sequentially laminated, a first opening is formed in the negative opening resist, and a second opening narrower than the first opening is formed in the positive opening resist in the first opening. Forming a second layer of the positive resist.
The second insulating layer is etched using the opening as a mask to form a third opening, the positive resist in the first opening of the negative resist is removed, and then the first insulating layer is removed. Etching through the third opening of the second insulating layer to form a fourth opening, and recess etching of the semiconductor layer through the fourth opening, and then depositing a gate metal and lifting off. Is the solution.

[0011]

According to the first aspect of the present invention, since the vicinity of the pillar portion of the T-shaped gate electrode is hollow, the hollow portion exists in the space below the lower surface of the wide portion of the T-shaped gate electrode. Therefore, it has an effect of reducing the parasitic capacitance with respect to the one in which the lower surface of the wide portion is filled with the insulator. Moreover, since the lower surface of the wide portion is supported by the second insulating layer, the mechanical strength of the T-shaped gate electrode is enhanced.

According to the invention of claim 2, the width of the opening (the fourth opening) of the first insulating layer is controlled,
The width of the recess corresponding to it can also be controlled.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The field effect transistor and its manufacturing method according to the present invention will be described below in detail with reference to the embodiments shown in the drawings.

A plan view of the chip pattern in which the field effect transistor of the present embodiment is formed is as shown in FIG. 3, and the AA sectional view in FIG. 1 is shown in FIG. 1 and the BB sectional view is shown in FIG.
Shown in.

As shown in FIG. 1, the epitaxial structure in which the field effect transistor of this embodiment is formed is such that a buffer layer 12 made of non-doped GaAs having a high resistance and a non-doped layer are successively formed on a semi-insulating GaAs substrate 11. n ^- I
Channel layer 13 made of nGaAs, Si-doped n ⁺ −
Electron supply layer 14 made of AlGaAs, Si-doped n ⁺
A cap layer 15 made of -GaAs is formed.

A recess 16 is formed on the surface of such a structure. The recess 16 has a structure in which the electron supply layer 14 is cut off by penetrating the cap layer 15. A T-shaped gate 17 is erected on the bottom of the recess 16 and the lower surface of the upper wide portion 17a of the T-shaped gate 17 is
The second insulating layer 19 is supported by the second insulating layer 19, and the second insulating layer 19 is formed on the first insulating layer 18 formed on the cap layer 15.

Further, the pillar portion 1 of the gate of the first insulating layer 18
The end face 18a facing the 7b is located away from the column 17b, and a hollow portion 20 is formed in the vicinity of the periphery of the column 17b. A source electrode 22 and a drain electrode 23 are arranged on both sides of the first and second insulating layers 18 and 19. In the figure, 21 indicates a two-dimensional electron gas and 17A indicates a bad portion of the gate electrode.

As shown in FIG. 4, the cross section CC of FIG. 3 shows that the hollow portion 20 at the end of the gate is the wide portion 17 of the gate.
Since the second insulating layer 19 is sealed by contacting the lower surface of the end of a with the second insulating layer 19, the vacuum is maintained at the time of vapor deposition of the gate metal described later.

FIG. 5 is a sectional view showing a state in which the overcoat insulating film 24 is deposited.

In the field effect transistor having such a structure, the T-shaped gate 17 is formed due to the existence of the hollow portion 20.
Compared with the case where the lower part of the upper wide portion 17a of the above is completely filled with an insulator, the parasitic capacitance is reduced due to the difference in the dielectric constant of the vacuum and the insulator, and the mechanical strength of the T-shaped gate 17 is 2 Since it is supported by the insulating layer 19, it becomes stronger. Also, when using a semiconductor material such as AlInAs / GaInAs HEMT that easily forms a dielectric layer at the interface between the recess bottom (AlInAs) and the passivation film, according to the present embodiment, the vacuum sealing structure of the hollow portion 20 is used. Therefore, it is possible to prevent the above conductive layer from being formed.

Next, a method of manufacturing the field effect transistor of this embodiment will be described.

First, a buffer layer, a channel layer, an electron supply layer 14, and a cap layer 1 which are sequentially laminated on a GaAs substrate.
SiO ₂ is deposited on the cap layer 15, which is the uppermost layer of the epitaxial structure of No. 5, by a CVD method to a film thickness of 0.1 to 0.2.
to form a first insulating layer 18 on which S
The second insulating film 19 is formed by depositing iN by CVD to a film thickness of 0.1 to 0.2 μm. Next, after patterning the first and second insulating films 18 and 19 by using a photolithography technique and an etching technique as shown in FIG. 6, on the surface of the cap layer 15 where the insulating layer is not formed,
The source electrode 22 and the drain electrode 2 are formed by forming an ohmic metal having an AuGe / Ni structure using a known technique.
3 is formed. The first and second insulating layers 18 and 19 are
Are not limited to these as long as they satisfy the etching selectivity described later.

Next, as shown in FIG. 7, (EB: electron beam) positive resist (for example, SAL11 manufactured by Shipley).
0-PLI) 25 is formed to a thickness of 0.3 μm, and a negative resist (for example, RD2000 manufactured by Hitachi Chemical Co., Ltd.) is formed thereon.
N) 26 is coated to a thickness of ~ 1 μm. Then, in the negative resist 26, a pattern opening P (up to 1 μm) corresponding to the upper wide portion 17a of the T-shaped gate 17 (and the lead portion up to the pad portion 17A shown in FIG. 3) is formed. At this time, since the negative resist 26 is opened, the positive resist 25 in the opening P is not exposed and remains as it is. The types of both resists do not intersect during coating and do not affect each other during each development.
Moreover, any material may be used as long as it has resistance when the insulating layers 18 and 19 are etched. Further, it is desirable that the opening cross-sectional shape of the negative resist has an inverse taper shape as shown in FIG.

Next, as shown in FIG. 8, by using electron beam direct drawing or the like for the positive type resist 25 in the opening P of the negative type resist 26, an opening Q (~ 0. 2 μm)
Is formed, and using this as a mask, the second insulating layer 19 is opened by anisotropic dry etching such as reactive ion etching (RIE).

Next, as shown in FIG. 9, the positive resist 25 in the opening of the negative resist 26 is removed by exposing and developing the entire surface. At this time, the negative resist 26
Is selected to absorb the photosensitive wavelength of the positive resist 25. When the cross-sectional shape of the opening of the negative resist 26 is not the inverse taper shape, the developing time at this time is adjusted and an undercut is inserted as shown by the dotted line in FIG. .

Next, as shown in FIG. 10, the second insulating layer 1
The first insulating layer 18 is etched using the opening of 9 as a mask. This etching is performed using buffer hydrofluoric acid (HF: NH
The opening width of the first insulating layer corresponding to the width of the recess 16 described later can be adjusted by adjusting the overetching amount by using wet etching such as ₃ F = 1: 9).

Then, as shown in FIG. 11, the recess 16 reaching the electron supply layer 14 is recess-etched so that a predetermined threshold voltage of the field effect transistor can be obtained. For this etching, the semiconductor layer is GaAs, AlG
Since it is aAs, for example, H ₃ PO ₄ : H ₂ O ₂ : H ₂ O =
An etching solution of 3: 1: 100 or the like is used, but other etching or dry etching may be used.

Next, the etching of the first insulating layer 18 is performed again under the same conditions as the above-described etching. As shown in FIG. 12, the opening width S of the first insulating layer 18 is set to the opening P of the negative resist 26. Spread to the same extent. In this state, the gate Schottky metal is vapor-deposited and lifted off, so that
The structure shown in 3 is obtained. Actually, as shown in FIG. 5, an overcoat insulating film 24 is further deposited, and other gates,
Drain, source bonding pad metal, etc. are formed and completed.

According to the above manufacturing method, the cross section of the gate lead portion BB in FIG. 3 is as shown in FIG.
In FIG. 8, if the positive type resist 25 is opened only in the gate operating portion, the gate metal other than the gate operating portion will be formed on the second insulating layer 19, and the parasitic capacitance due to the gate lead portion will be reduced to the semiconductor layer. It is reduced as compared with the case of being formed in contact with the top.

Further, there is an advantage that the gate recess width can be controlled by adjusting the opening width of the first insulating layer 18.

As described above, the present invention is applied to AlInAs / GaInA.
Although the embodiment applied to the s-based HEMT has been described, the present invention can be applied to various field effect transistors using other semiconductor materials, and it goes without saying that various design changes are possible.

Further, in the above embodiment, the processing using the lift-off method was carried out, but it is of course possible to form the gate by using the etching method.

[0033]

As is apparent from the above description, according to the present invention, the mechanical strength of the T-shaped gate electrode of the field effect transistor can be improved, and the parasitic capacitance of the gate portion can be reduced. There is. Further, since the recess portion can be vacuum-sealed, it is possible to use a passivation film in which a conductive layer is formed at the recess interface.

According to the second aspect of the invention, there is the effect that the controllability of the gate recess width can be expanded.
Since the gate metal other than the gate operating portion can be formed on the second insulating layer, it has an effect of significantly reducing the parasitic capacitance as compared with the conventional example in which the gate metal is formed in contact with the semiconductor layer.

[Brief description of drawings]

FIG. 1 is a sectional view taken along line AA of FIG. 3 showing an embodiment of the present invention.

FIG. 2 is a sectional view taken along line BB in FIG. 3 showing an embodiment of the present invention.

FIG. 3 is a plan view of an embodiment of the present invention.

FIG. 4 is a sectional view taken along line CC of FIG.

FIG. 5 is a cross-sectional view showing a completed state of the field effect transistor of the example.

FIG. 6 is a cross-sectional view showing the manufacturing process of the example.

FIG. 7 is a cross-sectional view showing the manufacturing process of the example.

FIG. 8 is a cross-sectional view showing the manufacturing process of the example.

FIG. 9 is a sectional view showing the manufacturing process of the example.

FIG. 10 is a cross-sectional view showing the manufacturing process of the example.

FIG. 11 is a cross-sectional view showing the manufacturing process of the example.

FIG. 12 is a cross-sectional view showing the manufacturing process of the example.

FIG. 13 is a cross-sectional view showing the manufacturing process of the example.

14A and 14B are cross-sectional views showing steps of a conventional example.

15A and 15B are cross-sectional views showing steps of a conventional example.

FIG. 16 is a sectional view of a conventional example using an etching method.

[Explanation of symbols]

 13 ... Channel layer 14 ... Electron supply layer 15 ... Cap layer 16 ... Recess 17 ... T-shaped gate 17a ... Upper wide part 17b ... Strut part 18 ... First insulating layer 19 ... Second insulating layer 20 ... Hollow part

Claims (2)

[Claims] 1. A field effect transistor having a T-shaped gate electrode composed of a pillar portion and a wide portion, wherein the vicinity of the pillar portion is hollow, and the lower portion of the wide portion is supported by an insulator. Field effect transistor to be. 2. A first insulating layer and a second insulating layer are sequentially laminated on a semiconductor layer, a positive resist and a negative resist are sequentially laminated on the second insulating layer, and the negative resist is first laminated. After forming one opening, a second opening narrower in width than the first opening is formed in the positive resist in the first opening,
Then, the second insulating layer is etched using the second opening of the positive resist as a mask to form a third opening, and then the positive resist in the first opening of the negative resist is removed. And etching the first insulating layer through the third opening of the second insulating layer to form a fourth opening,
A method of manufacturing a field effect transistor, comprising performing recess etching of the semiconductor layer through the fourth opening, then depositing a gate metal and lifting off.