JPH0684950A - Manufacture of field effect transistor - Google Patents

Abstract

PURPOSE:To provide a method for manufacturing a field effect transistor having the step of forming a micro gate electrode adapted for a mass production. CONSTITUTION:The method for manufacturing a field effect transistor comprises the steps of forming only an upper layer resist 3 of double resist in an overhang shape, obliquely vapor-depositing an Al film 4 thereby to shorten a size of an opening of the resist 3, transferring it to a lower layer resist 2, and forming a T-type gate shape by etching, recess etching, gate metal vapor-depositing and lifting-off the resist 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a field effect transistor, and more particularly to a high frequency field effect transistor having a Schottky barrier gate electrode in a recess region formed in the surface layer of a semiconductor active layer. Manufacturing method.

[0002]

2. Description of the Related Art In recent years, field effect transistors (GaAsFET) using a compound semiconductor such as GaAs have been used as high frequency field effect transistors of 4 GHz or higher. In order to realize the high frequency characteristics (low noise, high gain) of the high frequency field effect transistor,
(1) Reduction of source resistance, (2) Reduction of gate resistance,
(3) It is desired to reduce the gate-source capacitance. Among them, in order to reduce the source resistance, a structure in which the semiconductor active layer under the gate electrode is dug into a concave shape (recess gate) has been proposed. Further, the reduction of the gate-source capacitance can be realized by shortening the gate length, but with the miniaturization of the gate, it is possible to simultaneously realize the reduction of the gate length and the reduction of the gate resistance. It has become a major factor in determining the high frequency characteristics of the high frequency field effect transistor. Conventionally, the cross-sectional shape of the gate electrode has been reduced in order to simultaneously realize the reduction of the gate length and the reduction of the gate resistance.
Many manufacturing methods for producing a T-type structure have been proposed. However, these methods are methods using an electron beam drawing apparatus, an ion beam drawing apparatus, or the like. After directly exposing a resist with an electron beam or an ion beam, a gate metal is vapor-deposited and lift-off or photoetching is performed to form a gate electrode Was a method of forming.

[0003]

The above-mentioned conventional manufacturing method has a problem that it is not suitable for mass production because it uses an electron beam drawing apparatus or an ion beam drawing apparatus. Further, a fine pattern having a beam diameter equal to or smaller than that of an electron beam or an ion beam cannot be drawn, and there is a limit to miniaturization. The present invention aims to overcome these drawbacks.

[0004]

In order to solve the above-mentioned drawbacks, the present invention provides a semiconductor active layer formed on a semiconductor active layer in a gate forming region between a source electrode and a drain electrode at regular intervals. First and second mask materials are formed, and second
Removing the mask material from the gate formation region to form a first opening, exposing the first mask material, depositing a metal film on the exposed first mask material to form a second opening, The first mask material is removed through the second opening to expose the semiconductor active layer, the deposited metal film is removed, and then the exposed semiconductor active layer is etched to form a recessed region to form a gate metal. Is deposited, the first and second mask materials are removed, and a Schottky barrier gate electrode is formed in the recess region.

[0005]

EXAMPLE An example of the present invention will be described below by taking a method of manufacturing a GaAs FET as an example. An AuGe film is vapor-deposited on the GaAs active layer 1, patterned into the shape of a source electrode / drain electrode, and then heat-treated to form Ga.
A source electrode / drain electrode (not shown) that makes ohmic contact with the As active layer is formed. A gate electrode is formed between the source electrode and the drain electrode formed at regular intervals. A photoresist 2 is formed as a first mask material on this gate formation region. Applying a second photoresist as a second mask material on the first photoresist 2,
An overhang shape is formed by exposure and development (Fig. 1). The first mask material can be formed in multiple layers with the photoresist of the second mask material, and must not be dissolved in a developing solution or the like when patterning the second mask material. Any material may be used as long as it serves as a mask and can be removed after the gate electrode is formed, and specifically, any of photoresist, polyimide, silicon dioxide film, silicon nitride film and the like may be used. When a photoresist is selected as the first mask material, it is applied on the GaAs active layer and then post-baked at 180 to 200 ° C.
A first mask material that satisfies the above conditions can be obtained.
By selecting a surface cross-linking type photoresist as the photoresist 3 of the second mask material, the overhang shape shown in FIG. 1 can be obtained.

Next, an Al film 4 is obliquely vapor-deposited from the direction of the arrow on the exposed first photoresist 2 with a space having a dimension corresponding to the gate length provided (FIG. 2). The vapor-deposited metal has only to be an etching mask for the first photoresist 2 and can be removed in a later step.
Was selected. The vapor deposition film thickness was 1000 angstroms or less. The vapor deposition angle θ is calculated as follows from the film thickness of the second photoresist 3, the opening size, and the desired gate length size. tan θ = (aperture size + gate length size) / 2 × film thickness

Next, using the Al film 4 as an etching mask,
The first photoresist 2 is removed by dry etching. Etching is performed with RF power of 50 W and O2 flow rate of 2.
Under the conditions of 5 SCCM and pressure of 1 × 10 ^-2 Torr, almost vertical etching shape is obtained (FIG. 3).

After the Al film 4 is removed by etching with hot phosphoric acid (FIG. 4), the GaAs active layer 1 is removed by etching with a phosphoric acid-hydrogen peroxide type etching solution or the like to form a recess (FIG. 5). Next, the gate metal 5 is vapor-deposited (FIG. 6), the first and second photoresists 2 and 3 are removed, and the gate electrode 6 is formed (FIG. 7). Hereinafter, a field effect transistor is formed by a normal semiconductor manufacturing process.

Through the above steps, a fine gate can be formed by a normal semiconductor manufacturing process. The size of the gate length can be determined by the vapor deposition angle of the Al film in FIG. 2 from the oblique direction, and the gate electrode of 0.1 μm or less can be formed. When performing such ultra-fine processing, it is necessary to form the first photoresist with a small film thickness. Usually, the film thickness of the first mask material is formed to be equal to or smaller than the gate length.

[0010]

As described above, according to the present invention, it is possible to obtain a fine gate electrode shape without an increase in gate resistance by a normal semiconductor manufacturing process. Further, it becomes possible to provide a method for manufacturing a field effect transistor which does not increase source resistance and source-gate capacitance, and it is possible to improve high frequency characteristics. In addition, it has become possible to form ultra-fine shapes with an electron beam or ion beam diameter or less.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing method of the present invention.

FIG. 2 is a cross-sectional view showing the manufacturing method of the present invention.

FIG. 3 is a cross-sectional view showing the manufacturing method of the present invention.

FIG. 4 is a cross-sectional view showing the manufacturing method of the present invention.

FIG. 5 is a cross-sectional view showing the manufacturing method of the present invention.

FIG. 6 is a cross-sectional view showing the manufacturing method of the present invention.

FIG. 7 is a cross-sectional view showing the manufacturing method of the present invention.

[Explanation of sign]

 1 GaAs Active Layer 2 First Photoresist 3 Second Photoresist 4 Al Film 5 Gate Metal 6 Gate Electrode

Claims (1)

[Claims] 1. A recessed region is formed in a gate forming region between a source electrode and a drain electrode formed on a semiconductor active layer at regular intervals, and a Schottky barrier gate electrode is formed in the recessed region. In the method of manufacturing a field effect transistor according to claim 1, a step of forming a first mask material on the semiconductor active layer in the gate formation region, and a step of forming a second mask material on the first mask material, Removing the second mask material from the gate formation region, forming a first opening, and exposing the first mask material; and depositing a metal film on the exposed first mask material. Forming a second opening, removing the first mask material through the second opening to expose the semiconductor active layer, removing the metal film, and exposing Etching the active semiconductor layer , A step of forming the recessed region, a step of depositing a gate metal, and a step of removing the first and second mask materials and forming a Schottky barrier gate electrode. Manufacturing method of transistor.