KR100364710B1 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
- Publication number
- KR100364710B1 KR100364710B1 KR1019940018754A KR19940018754A KR100364710B1 KR 100364710 B1 KR100364710 B1 KR 100364710B1 KR 1019940018754 A KR1019940018754 A KR 1019940018754A KR 19940018754 A KR19940018754 A KR 19940018754A KR 100364710 B1 KR100364710 B1 KR 100364710B1
- Authority
- KR
- South Korea
- Prior art keywords
- gaas
- layer
- substrate
- photoresist
- photoresist pattern
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract description 15
- 238000004519 manufacturing process Methods 0.000 title abstract description 10
- 239000004065 semiconductor Substances 0.000 title abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 34
- 229920001721 polyimide Polymers 0.000 description 5
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- MVPPADPHJFYWMZ-UHFFFAOYSA-N chlorobenzene Chemical compound ClC1=CC=CC=C1 MVPPADPHJFYWMZ-UHFFFAOYSA-N 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000004380 ashing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 GaAs MESFET의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a GaAs MESFET.
종래의 유전체막 어시스티드(assisted) T-게이트 GaAs MESFET 제조방법을 제1 도에 공정순서에 따라 도시하였다.A conventional method for fabricating an assisted dielectric film assisted T-gate GaAs MESFET is shown in FIG. 1 according to the process sequence.
먼저, 제 1 도(a)와 같이 GaAs 기판(1)상에 GaAs 버퍼층(2), n-GaAs 활성층(4)를 차례로 성장시킨 후, 상기 n+-GaAs 활성층(4)과 n-GaAs 층(3), GaAs 버퍼층(2)를 차례로 성장시킨 후 상기 n+-GaAs 활성층(4)과 n-GaAs 층(3), GaAs 버퍼층(2)의 소정부분까지 메사형태로 식각한 다음, 상기 메사구조의 양쪽에 소오스 및 드레인패드(5)를 형성하여 소오스 및 드레인 오믹콘택(ohmic contact)을 형성하고, 기판 전면에 폴리이미드(polyimide)(6)를 형성한 후, 이 위에 포토레지스트(7)를 도포한 다음 게이트 패턴을 형성한다.First, as shown in FIG. 1A, a GaAs buffer layer 2 and an n-GaAs active layer 4 are sequentially grown on the GaAs substrate 1, and then the n + -GaAs active layer 4 and the n-GaAs layer are grown. (3), the GaAs buffer layer 2 is sequentially grown, and the n + -GaAs active layer 4, the n-GaAs layer 3, and a predetermined portion of the GaAs buffer layer 2 are etched in mesa form, and then the mesa Source and drain pads 5 are formed on both sides of the structure to form source and drain ohmic contacts, and a polyimide 6 is formed on the entire surface of the substrate, and then the photoresist 7 thereon. Is then applied to form a gate pattern.
이어서 제 1 도 (b)와 같이 상기 포토레지스트패턴(7)이 형성된 기판 전면에 PECVD(Plasma Enhanced Chemical Vapor Deposition)방법으로 산화막 또는 질화막등의 절연층(8)을 증착한 후, 이를 RIE(Reactive Ion Etching)에 의해 이방성 식각한 후, 제 1 도 (c)와 같이 상기 절연층(8)의 식각에 의해 노출된 폴리이미드막(6)을 식각한다.Subsequently, as shown in FIG. 1B, an insulating layer 8 such as an oxide film or a nitride film is deposited on the entire surface of the substrate on which the photoresist pattern 7 is formed by PECVD (Plasma Enhanced Chemical Vapor Deposition), and then RIE (Reactive) After anisotropic etching by ion etching, the polyimide film 6 exposed by etching the insulating layer 8 is etched as shown in FIG.
다음에 제 1 도 (d)와 같이 상기 절연층(8)을 습식식각에 의해 제거한 후, 상기 n+-GaAs 활성층(4)을 리세스(recess) 에칭하여 리세스구조(10)를 형성한다.Next, as shown in FIG. 1D, the insulating layer 8 is removed by wet etching, and then the n + -GaAs active layer 4 is recessed and etched to form a recess structure 10. .
이어서 제 1 도 (e)와 같이 기판 전면에 게이트 형성을 위한 금속(11)을 증착한 후, 리프트오프(lift-off)공정을 거쳐 제 1 도 (f)에 도시된 바와 같이 T 형 게이트(11)를 형성한다.Subsequently, a metal 11 for forming a gate is deposited on the entire surface of the substrate as shown in FIG. 1 (e), and then, through a lift-off process, as shown in FIG. 11) form.
상술한 종래기술에 의한 MESFET는 폴리이미드와 포토레지스트 등의 두 가지 층을 사용하여 제작하므로 공정이 복잡하고, 폴리이미드의 형성온도가 300℃정도의 고온이므로 GaAs에 손상을 가할 수 있는 여지가 있다.Since the MESFET according to the related art is manufactured by using two layers such as polyimide and photoresist, the process is complicated, and since the formation temperature of the polyimide is about 300 ° C., there is a possibility of damaging GaAs. .
또한 리프트오프공정시 상부층의 포토레지스트는 아세톤으로 리프트오프되는 폴리미미드층은 O2애슁(ashing)에 의해 제거되야 하기 때문에 리세스 에칭된 활성 층이 플라즈마로 인한 손상을 받을 수 있는 문제가 있다.In addition, since the photoresist of the upper layer is lifted off with acetone during the lift-off process, the polyimide layer lifted off with acetone has to be removed by O 2 ashing, so that the recess-etched active layer may be damaged by plasma. .
본 발명은 상술한 문제를 해결하기 위한 것으로, 단순한 공정에 의해 특성이 향상된 MESFET를 제조할 수 있는 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a method for manufacturing a MESFET having improved characteristics by a simple process.
상기 목적을 달성하기 위한 본 발명의 반도체소자 제조방법은 기판상에 포토레지스트를 도포하는 단계와, 상기 포토레지스트에 게이트패턴을 전사시켜 오버 행 구조의 포토레지스트패턴을 형성하는 단계, 상기 포토레지스트패턴을 마스크로 하여 기판을 리세스 에칭하는 단계, 상기 포토레지스트패턴 및 리세스 에칭된 기판부위 표면에 SiN을 증착하는 단계, 상기 SiN막을 이방성 식각하여 기판 소정부위를 노출시키는 단계, 기판 전면에 금속을 각도증착하는 단계, 및 상기 포토레지스트패턴을 리프트로프하는 단계를 포함하여 이루어진다.The semiconductor device manufacturing method of the present invention for achieving the above object is a step of applying a photoresist on a substrate, and transferring a gate pattern to the photoresist to form a photoresist pattern having an overhang structure, the photoresist pattern Recess etching the substrate using the mask as a mask; depositing SiN on the surface of the photoresist pattern and the recess-etched substrate; exposing the substrate to a predetermined region by anisotropically etching the SiN film; And depositing the photoresist pattern.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제 2 도(a)에 본 발명에 따른 GaAs 기판(1)상에 GaAs 버퍼층(2), n-GaAs 층(3), n+-GaAs 활성층(4)을 차례로 성장시킨 후, 상기 n+-GaAs 활성층(4)과 n-GaAs층(3), GaAs 버퍼층(2)의 소정부분까지 메사형태로 식각한 다음, 상기 메사 구조의양쪽에 소오스 및 드레인패드(5)를 형성하여 소오스 및 드레인 오믹콘택(ohmic contact)을 형성하고, 기판 전면에 포토레지스트(7)를 도포한 다음, 이를 게이트 패턴으로 패터닝한다.In Fig. 2 (a), a GaAs buffer layer 2, an n-GaAs layer 3, and an n + -GaAs active layer 4 are sequentially grown on a GaAs substrate 1 according to the present invention, and then n + - A predetermined portion of the GaAs active layer 4, the n-GaAs layer 3, and the GaAs buffer layer 2 is etched in a mesa shape, and then source and drain pads 5 are formed on both sides of the mesa structure so that the source and drain ohmic An ohmic contact is formed, a photoresist 7 is applied to the entire surface of the substrate, and then patterned into a gate pattern.
이때, 프토레지스트(7)의 단면을 오버행(overhang)구조로 형성하는데, 이를 설명하면 다음과 같다.At this time, the cross section of the protoresist 7 is formed in an overhang structure, which will be described below.
먼저, 포토레지스트를 도포한 후, 자외선에 선택적으로 노광시킨 다음 모노클로 로벤젠(mono-chloro benzene)에 담가(dipping) 약 10 분이 경과한 후, 모노클로 로벤젠을 제거하고 현상하게 되면 오버행구조를 얻을 수 있다.First, after the photoresist is applied, it is selectively exposed to ultraviolet rays, and after about 10 minutes of dipping in mono-chlorobenzene, the monochlorobenzene is removed and developed. Can be obtained.
이어서 다음에 제 2 도 (b)에 도시된 바와 같이 상기 포토레지스트(7)를 마스크로 하여 상기 n+-GaAs 활성층(4)과 n-GaAs 층(3)을 리세스 에칭하여 리세스부(12)를 형성한다.Subsequently, as shown in FIG. 2B, the n + -GaAs active layer 4 and the n-GaAs layer 3 are recessed and etched using the photoresist 7 as a mask to form a recessed portion ( 12).
다음에 기판 전면에 PECVD를 이용하여 SiN(13)을 증착하면 우수한 스텝커버리지(step coverage)에 의해 제 2 도 (c)에 도시된 바와 같은 형태로 SiN 막(13)이 형성되며, RIE에 의해 상기 SiN 막(13)을 이방성 식각하면 제 2 도 (d)에 도시된 바와 같은 형태를 얻을 수 있다.Next, the SiN 13 is deposited on the entire surface of the substrate by PECVD to form the SiN film 13 in the form as shown in FIG. 2C by excellent step coverage, and by RIE. When the SiN film 13 is anisotropically etched, a shape as shown in FIG. 2 (d) can be obtained.
이때, SiN 막(13)의 식각에 의해 노출된 n-GaAs 층(3)의 폭이 게이트길이가 되게 된다.At this time, the width of the n-GaAs layer 3 exposed by the etching of the SiN film 13 becomes the gate length.
이어서 제 2 도 (e)에 도시된 바와 같이 게이트 형성용 금속(11)을 각도증착한다.Subsequently, as shown in FIG. 2E, the gate forming metal 11 is angularly deposited.
상기 게이트 금속의 각도증착은 자전과 공전을 동시에 수행할 수 있는 전자 빔 지그(E-beam jig)에 기판을 약 30° 정도가 유지되도록 장착한 다음 증착을 수행하면 된다.The angular deposition of the gate metal may be carried out by attaching the substrate to an E-beam jig capable of simultaneously rotating and revolving so as to maintain about 30 ° and then performing deposition.
다음에 상기 포토레지스트패턴을 리프트오프하여 제 2 도 (f)에 도시된 바와 같이 T 형 게이트(11)를 형성한 후, 패시베이션(passivation) 막(14)으로서, 예컨대 SiN을 증착한 후, 이를 선택적으로 제거하여 소오스, 드레인, 게이트의 패드부분을 노출시킨 다음 전기적 특성 및 와이어 본딩(wire bonding) 특성의 향상을 위해 Au(16)를 전기도금함으로써 MESFET제작을 완료한다.Next, the photoresist pattern is lifted off to form a T-type gate 11 as shown in FIG. 2 (f), and then, as the passivation film 14, for example, SiN is deposited. The fabrication of the MESFET is completed by selectively removing and exposing the pad portions of the source, drain, and gate, and then electroplating Au (16) for the improvement of electrical characteristics and wire bonding characteristics.
이상 상술한 바와 같이 본 발명에 의하면 게이트 패턴을 전사시킨 포토레지스트의 오버행 구조와 Sin의 증착 특성을 이용하여 게이트 길이가 감소된 T형 게이트를 용이하게 제조할 수 있다.As described above, according to the present invention, a T-type gate having a reduced gate length can be easily manufactured using the overhang structure of the photoresist on which the gate pattern is transferred and the deposition characteristic of Sin.
또한 본 발명의 공정은 절연층의 제거나 게이트 금속의 리프트오프가 용이하고 간편하며, T형 게이트 제조에 사용된 SiN 막을 계속해서 제거하지 않고 사용하므로 활성층의 표면상태 안정에 기여하여 MESFET 특성을 향상시키게 된다.In addition, the process of the present invention is easy and simple to remove the insulating layer or lift-off of the gate metal, it is used without continuing to remove the SiN film used in the T-type gate fabrication contributes to stabilization of the surface state of the active layer to improve the MESFET characteristics Let's go.
제 1 도는 종래 기술에 따른 T 형 게이트구조를 가진 MESFET 제조방법을 도시한 공정순서도1 is a process flowchart showing a method for manufacturing a MESFET having a T-type gate structure according to the prior art.
제 2 도는 본 발명에 따른 T 형 게이트구조를 가지는 MESFET 제조방법을 도시한 공정순서도2 is a process flowchart showing a method for manufacturing a MESFET having a T-type gate structure according to the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
1 : GaAs기판 2 : GaAs 버퍼층1 GaAs substrate 2 GaAs buffer layer
3 : n-GaAs 층 4 : n+-GaAs 층3: n-GaAs layer 4: n + -GaAs layer
5 : 소오스 및 드레인패드 7 : 포토레지스트5 source and drain pad 7 photoresist
13 : SiN 막 15 : 패시베이션막13: SiN film 15: passivation film
16 : Au 막16: Au film
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940018754A KR100364710B1 (en) | 1994-07-29 | 1994-07-29 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940018754A KR100364710B1 (en) | 1994-07-29 | 1994-07-29 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960006005A KR960006005A (en) | 1996-02-23 |
| KR100364710B1 true KR100364710B1 (en) | 2003-02-25 |
Family
ID=37490976
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940018754A KR100364710B1 (en) | 1994-07-29 | 1994-07-29 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100364710B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100744681B1 (en) * | 2001-12-19 | 2007-08-01 | 주식회사 하이닉스반도체 | A fabricating method of semiconductor device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4536942A (en) * | 1982-12-09 | 1985-08-27 | Cornell Research Foundation, Inc. | Fabrication of T-shaped metal lines for semiconductor devices |
| US4599790A (en) * | 1985-01-30 | 1986-07-15 | Texas Instruments Incorporated | Process for forming a T-shaped gate structure |
| JPH0228333A (en) * | 1988-07-18 | 1990-01-30 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| US4997778A (en) * | 1988-09-05 | 1991-03-05 | Korea Electronics And Telecommunications Research Institute | Process for forming a self-aligned FET having a T-shaped gate structure |
| JPH0684950A (en) * | 1992-08-28 | 1994-03-25 | New Japan Radio Co Ltd | Manufacture of field effect transistor |
-
1994
- 1994-07-29 KR KR1019940018754A patent/KR100364710B1/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4536942A (en) * | 1982-12-09 | 1985-08-27 | Cornell Research Foundation, Inc. | Fabrication of T-shaped metal lines for semiconductor devices |
| US4599790A (en) * | 1985-01-30 | 1986-07-15 | Texas Instruments Incorporated | Process for forming a T-shaped gate structure |
| JPH0228333A (en) * | 1988-07-18 | 1990-01-30 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| US4997778A (en) * | 1988-09-05 | 1991-03-05 | Korea Electronics And Telecommunications Research Institute | Process for forming a self-aligned FET having a T-shaped gate structure |
| JPH0684950A (en) * | 1992-08-28 | 1994-03-25 | New Japan Radio Co Ltd | Manufacture of field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| KR960006005A (en) | 1996-02-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100262940B1 (en) | Method for fabricating compound semiconductor device using lift-off of insulator | |
| KR0179116B1 (en) | Method for manufacturing self-aligned t-type gate | |
| JP3229550B2 (en) | Method of superposing T-type gate electrode and method of superposing T-type low resistance metal | |
| KR100364710B1 (en) | Method for manufacturing semiconductor device | |
| JP3674917B2 (en) | Manufacturing method of semiconductor device | |
| JPH03165526A (en) | Manufacture of field effect transistor | |
| JPS61240684A (en) | Schottky-type field effect transistor and manufacture thereof | |
| JP2667840B2 (en) | Method for manufacturing compound semiconductor device | |
| JPS60244075A (en) | Manufacture of e/d structure integrated circuit | |
| JP2652657B2 (en) | Gate electrode formation method | |
| JPH0226385B2 (en) | ||
| JPH02185043A (en) | Manufacture of semiconductor device | |
| JPS6180821A (en) | Pattern inverting method | |
| JPS6279677A (en) | Manufacture of semiconductor device | |
| JPS58194374A (en) | Manufacture of semiconductor device | |
| JPH0684954A (en) | Manufacture of semiconductor device | |
| JPS63291476A (en) | Manufacture of semiconductor device | |
| JPS598378A (en) | Gaas fet | |
| JPH0574817A (en) | Manufacture of semiconductor device | |
| JPS616870A (en) | Manufacture of field-effect transistor | |
| JPH04352333A (en) | Manufacture of semiconductor device | |
| JPS59119764A (en) | Manufacture of field effect type semiconductor device | |
| JPS6216574A (en) | Manufacture of field-effect transistor | |
| JPS5877261A (en) | Semiconductor device | |
| JPH09186189A (en) | Manufacture of compound semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E902 | Notification of reason for refusal | ||
| N231 | Notification of change of applicant | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20070918 Year of fee payment: 6 |
|
| LAPS | Lapse due to unpaid annual fee |