JPH0226385B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a three-dimensional wiring in a semiconductor device, and more particularly to a method for forming an air-insulated three-dimensional wiring.

Semiconductor elements, especially junction gate field effect transistors (hereinafter referred to as
GaAsMESFET) has been put into practical use as a microwave transistor that overcomes the characteristic limits of Si bipolar transistors. The output power of such microwave GaAs MESFETs can be increased by increasing the total gate width.
Therefore, GaAs MESFETs for power use are usually
As shown in the plan view of figure a, a comb-shaped drain electrode 1
1 and source electrodes 12 are arranged alternately, and a gate electrode 13 is arranged between them. In order to achieve such a configuration, the wiring 121 to the source electrode 12 and the power supply wiring 131 to the gate electrode 13 must necessarily be three-dimensionally wired (crossover) at a position such as point 14. Usually these crossovers are shown in Figure 1b and A in Figure 1a.
As shown in the cross section of the -A' section, a structure is adopted in which the two wiring electrodes are insulated by the SiO ₂ film 15.

However, at ultra-high frequencies above the X band, the parasitic capacitance generated in these three-dimensional interconnections cannot be ignored compared to the gate-source depletion layer capacitance _CGS of the FET itself, and together with dielectric loss, the gain or band characteristics This contributes to the decline. Although the parasitic capacitance can be reduced to some extent by reducing the width of the three-dimensionally intersecting electrodes, an increase in wiring resistance is not preferable because it causes electromigration of the wiring electrodes.
The most effective way to significantly reduce parasitic capacitance without increasing parasitic resistance is to insulate the intersection with air without using a dielectric (air crossover structure).

Several devices with air crossover structures have been reported so far, but all of their formation methods mainly utilize etching selectivity. In other words, an air crossover structure is obtained by forming a spacer material (copper is commonly used) between both wiring electrodes by electrolytic plating, etc., and then selectively etching away only the spacer material. It is.

Using traditional methods like this
When trying to make a GaAs MESFET into an air crossover, the following problems arise. (1) Sensitive to acid or alkaline solutions
It is difficult to obtain an etching solution that can selectively remove only the spacer material without attacking gate electrodes made of GaAs or Al. (2) It is difficult to process spacer material formed to a thickness of several μm with good uniformity within the wafer.

An object of the present invention is to provide a novel method for forming air-insulated three-dimensional wiring.

According to the present invention, a first photoresist layer consisting of a thick film is formed on a band-shaped electrode serving as a first wiring on a substrate, and by exposing it to CF ₄ plasma, a modified layer containing many fluorine atoms is formed on the surface. a step of forming a thick film wiring having a thickness similar to that of the first photoresist layer by performing electrolytic plating using the first photoresist layer as a mask, and a step of forming a metal film for power supply on the entire surface. After depositing, forming a second photoresist layer having an opening at the intersection with the first wiring,
forming a second wiring that intersects the first wiring by performing electrolytic plating again; and after removing the second photoresist layer, using the second wiring as a mask, forming a second wiring that intersects the first wiring; Air insulation characterized by comprising the steps of removing the film by ion etching or chemical etching, further treating the exposed first photoresist layer with O ₂ plasma to remove the altered layer, and then removing it with an organic solvent. A method for forming three-dimensional wiring can be obtained.

According to the present invention, since the photoresist itself, which can be easily processed in a normal photolithography process, is used as a spacer material, the steps required to form three-dimensional wiring are greatly simplified compared to conventional methods.

Below, as an example of the present invention
This will be explained in detail using the air crossover of GaAs MESFET as an example.

Figures 2 and 3 are diagrams for explaining one embodiment of the present invention, Figures 2 a to f are plan views of main parts of the manufacturing process, and Figures 3 a to f are A in Figure 2, respectively. −A′,
Main part sectional views taken along B-B', CC', D-D', E-E', and F-F' are shown. First, an active layer 21 is epitaxially grown on a semi-insulating GaAs substrate 20, and a layer for forming a shot key barrier is formed on this layer.
Gate electrode 22 made of Al, ohmic source electrode 23 and drain electrode 2 made of AuGeNi
4 is formed by a lift-off method using normal optical exposure (FIG. 2a). Next, a SiO ₂ film 25 serving as a protective film for the Al gate electrode 22 is deposited on the entire surface of the wafer to a thickness of about 3000 Å by CVD, and windows are opened in the source and drain electrode extraction portions 231 and 241 and the gate electrode extraction portion 221. Next, the gate pad section 222 made of Al and the gate pad section 222 are drawn out from there.
In order to prevent reaction with the bonding wire made of Au, the reaction prevention electrode 22 is made of, for example, Ti/Pt.
3 is selectively formed on the gate pad portion 222, for example, Ti/Au is deposited to a thickness of about 500 Å each as a power supply metal film 26 for electrolytic plating (FIG. 3b). After applying a positive photoresist 27 such as AZ1375 (trade name) to a thickness of 4 to 6 μm over the entire surface of the wafer, patterning is performed to selectively cover the power supply wiring 224 to the gate electrode 22 (second photoresist 27).
(shaded area in figure c). Next, after baking at 120℃ for about 60 minutes, CF ₄ gas pressure 0.3 Torr, RF
A CF ₄ plasma treatment is performed for about 2 minutes under the condition of a power of 200 W to form an altered layer 28 of about 200 Å containing many fluorine atoms on the surface. This altered layer 28 is insoluble in organic solvents such as n-butyl acetate, which is a solvent for AZ-based resists, and in developing solutions for AZ-based resists.
Easily removed by O ₂ plasma treatment. This CF ₄ plasma treatment has the effect of preventing the resist pattern 27 from being deformed in the subsequent photoprocessing step. Next, in the shaded area in Figure 2 d.
By applying Au plating, the photoresist layer 2
A thick film wiring 29 having a thickness similar to that of 7 is formed. For the purpose of preventing deformation after completion of the cross-over electrode that will be formed later, it is desirable that the thickness of the thick film wiring 29 be equal to or slightly thicker than the photoresist layer 27. Next, after forming the same power supply metal film 30 as described above again by vapor deposition on the entire surface,
A photoresist 31 such as AZ1350J is applied and patterned so that the shaded area in FIG. 2e is selectively covered. In the conventional method in which the first layer of photoresist 27 is not subjected to CF ₄ plasma treatment, step breakage tends to occur due to poor coverage due to the complicated shape of the step portion, and this second layer of photoresist 31 During patterning, the first layer of resist was dissolved and the power supply metal film 30 was deformed or lifted off, making it difficult to form a crossover electrode later. Next, using the photoresist layer 31 as a mask, gold plating is applied again to form a crossover electrode 32 having a thickness of, for example, 2 to 3 μm (FIG. 3e). Next, after removing the photoresist 31 with an organic solvent such as acetone, using the crossover electrode 32 as a mask, Ar ion beam etching or I ₂ :
KI: Using a H ₂ O-based and H ₂ SO ₄ -based etching solution, unnecessary power supply metal film 32 other than the crossover electrode 32 portion is removed. Then _O2 gas pressure
Photoresist layer 2 exposed by O ₂ plasma treatment for about 2 minutes under conditions of 0.5 Torr and RF power of 200 W.
After removing the deteriorated layer 28 on the surface of 7, completely remove the photoresist 27 using a resist remover (J-100).
Finally, by selectively removing unnecessary power supply metal film 26 using the same etching solution as described above, gate power supply wiring 224 and crossover electrode 32 as shown in FIG. 3F are formed. The air-insulated air crossover structure is completed.

As described above, if the forming method of the present invention is used, the spacer material, which conventionally requires a complicated process, can be easily formed using a normal photo process, resulting in improved productivity, yield, and reliability. It has become possible to significantly improve the

[Brief explanation of drawings]

Figure 1 a and b are for general electric power, respectively.
11, 12, and 13 are the drain, source, and gate electrodes, respectively; 15 is the SiO ₂ film;
Reference numeral 1 indicates a source wiring, and reference numeral 131 indicates a gate wiring 14, which indicates a three-dimensional wiring portion of the source wiring 121 and the gate wiring 131. Figures 2 a to f and 3 a to f are diagrams for explaining one embodiment of the present invention. Figures 2 a to f are plan views of main parts of the manufacturing process, and Figures 3 a to f are FIG. 3 is a sectional view of the main part of FIG. 2; In each figure, 20...semi-insulating GaAs substrate,
21... Operating layer, 22, 23, 24... Gate, source, drain electrode, respectively, 25... SiO ₂
Membrane, 26, 30... Metal membrane for power supply, 27, 31...
...Positive photoresist, 28...Altered layer, 29...
... Thick film wiring, 32 ... Crossover electrode, 22
1, 231, 241... windows for gate, source, and drain electrodes opened in the SiO ₂ film 25, 222... gate pad, 223... metal film for reaction prevention, 224... wiring for gate power supply.

Claims (1)

[Claims] 1. A first wire that covers a first wiring provided on a substrate.
a step of selectively forming a photoresist layer, a step of making the surface of the first photoresist layer a modified layer containing a large amount of fluorine atoms, and a step of forming a photoresist layer with a similar thickness using the first photoresist layer as a mask. a step of selectively forming a thick film wiring; a step of selectively forming a second photoresist layer having openings at intersections with the first wiring; The second line that intersects with the wiring of
a step of selectively forming the wiring of the first photoresist layer, a step of removing the second photoresist layer, and a step of removing the second photoresist layer;
1. A method for forming an air-insulated three-dimensional wiring, comprising the step of removing a photoresist layer. 2. The method for forming three-dimensional wiring according to claim 1, wherein the first and second photoresist layers are positive resists.