JPH0260213B2 - - Google Patents
Info
- Publication number
- JPH0260213B2 JPH0260213B2 JP78386A JP78386A JPH0260213B2 JP H0260213 B2 JPH0260213 B2 JP H0260213B2 JP 78386 A JP78386 A JP 78386A JP 78386 A JP78386 A JP 78386A JP H0260213 B2 JPH0260213 B2 JP H0260213B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- sio
- insulating film
- electrode
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 230000001681 protective effect Effects 0.000 claims 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 23
- 238000000034 method Methods 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
〔概要〕
GaAsFETの製造において、従来はそのまま残
しておいたリフトオフ用のスペーサとなる絶縁膜
を除去し、新たな層間絶縁膜を形成することによ
り表面を平坦化する。[Detailed Description of the Invention] [Summary] In the production of GaAsFET, the insulating film serving as a spacer for lift-off, which was conventionally left as is, is removed and a new interlayer insulating film is formed to flatten the surface.
本発明は半導体装置の製造方法に関するもの
で、さらに詳しく言えば、GaAsFETの製造にお
いて基板の表面を平坦化するための方法に関する
ものである。
The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for flattening the surface of a substrate in manufacturing a GaAsFET.
〔従来の技術〕
GaAsFETを作る方法を第３図の断面図を参照
して説明すると、まずそのａに示される如く、
GaAs基板１１上のレジスト膜３１を図示の如く
パターニングし、例えばシリコン（Si）を加速電
圧60KeV、ドーズ量１×1012／cm2のドーズ量でイ
オン注入してｎ型層１２を形成し、レジスト膜３
１を除去する。[Prior art] The method of manufacturing a GaAsFET will be explained with reference to the cross-sectional view of Fig. 3. First, as shown in Fig. 3,
The resist film 31 on the GaAs substrate 11 is patterned as shown in the figure, and the n-type layer 12 is formed by, for example, ion-implanting silicon (Si) at an acceleration voltage of 60 KeV and a dose of 1×10 12 /cm 2 . Resist film 3
Remove 1.
次に、全面にWSiを4000Åの厚さにスパツタで
成長し、それを第３図ｂに示される如くパターニ
ングしてゲート電極１４を作る。 Next, WSi is grown on the entire surface by sputtering to a thickness of 4000 Å and patterned as shown in FIG. 3b to form the gate electrode 14.
次に、第３図ｃに示される如く、レジスト膜３
２を図示の如くパターニングし、レジスト膜３２
とゲート電極１４をマスクにしてSiを加速電圧
175KeV、ドーズ量１×1013／cm2でイオン注入し
てn+型層１３を形成する。 Next, as shown in FIG. 3c, the resist film 3
2 is patterned as shown in the figure to form a resist film 32.
Using the gate electrode 14 as a mask, apply an acceleration voltage to Si.
The n + type layer 13 is formed by ion implantation at 175 KeV and a dose of 1×10 13 /cm 2 .
次に、基板表面を保護するパツシベーシヨン膜
を作るために、Si窒化膜１５（Si3N4膜、以下単
に窒化膜という）を1000Åの厚さに化学気相成長
法（CVD法）で成長し、その上に二酸化シリコ
ン膜１６（SiO2膜）を5000Åの厚さにCVD法で
成長する。SiO2膜１６は次の工程のリフトオフ
のスペーサとなるものである。ソース・ドレイン
電極を形成するためSiO2膜１６の上に設けたレ
ジスト膜３３を第３図ｄに示す如くパターニング
し、レジスト膜３３をマスクにSiO2膜１６と窒
化膜１５をエツチングし、蒸着によつてAuGe／
Au34を4000Åの厚さに被着し、アセトンを用い
てレジスト膜を溶かし、リフトオフによつてソー
ス電極１７、ドレイン電極１８を形成する。ドラ
イエツチングの場合、SiO2のエツチングには
（CF4＋CHF3）ガスを、また窒化膜のエツチング
には（CF4＋O2）ガスを用いる。 Next, in order to create a passivation film to protect the substrate surface, a Si nitride film 15 (Si 3 N 4 film, hereinafter simply referred to as nitride film) was grown to a thickness of 1000 Å by chemical vapor deposition (CVD). A silicon dioxide film 16 (SiO 2 film) is grown thereon to a thickness of 5000 Å by CVD. The SiO 2 film 16 serves as a lift-off spacer in the next step. In order to form source/drain electrodes, the resist film 33 provided on the SiO 2 film 16 is patterned as shown in FIG. By AuGe/
Au34 is deposited to a thickness of 4000 Å, the resist film is dissolved using acetone, and a source electrode 17 and a drain electrode 18 are formed by lift-off. In the case of dry etching, (CF 4 +CHF 3 ) gas is used for etching SiO 2 , and (CF 4 +O 2 ) gas is used for etching nitride film.
次いで、第３図ｅの如くFET相互を絶縁分離
し基板の他の部分に電極を形成するなどの目的の
ために、層間絶縁膜となるSiO2膜１９をCVD法
で5000Åの厚さに成長し、このSiO2膜１９にコ
ンタクトホール２０を窓開けして電極２１を形成
する。 Next, as shown in Figure 3e, in order to insulate and separate the FETs from each other and form electrodes on other parts of the substrate, a SiO 2 film 19 that will become an interlayer insulating film is grown to a thickness of 5000 Å using the CVD method. Then, a contact hole 20 is opened in this SiO 2 film 19 to form an electrode 21.
前記した第２層のSiO2膜１９が窓開けされた
ときの状態は、第３図ｄに示される。4000Åの厚
さのゲート電極１４の上には、1000Åの窒化膜１
５、リフトオフ用スペーサSiO2膜１６（5000
Å）、層間絶縁膜であるSiO2膜１９（5000Å）が
堆積されているので、図に矢印で示す段差は
11000Åになり、表面が平坦でなくなり、上に形
成される電極のためのコンタクトホール２０を正
確に開口することが難しく、また電極２１を形成
しても断線しやすい問題がある。
The state when the second layer SiO 2 film 19 is opened is shown in FIG. 3d. A 1000 Å thick nitride film 1 is formed on the 4000 Å thick gate electrode 14.
5. Lift-off spacer SiO 2 film 16 (5000
Å), since the SiO 2 film 19 (5000 Å), which is an interlayer insulating film, is deposited, the step indicated by the arrow in the figure is
11000 Å, the surface is no longer flat, it is difficult to accurately open the contact hole 20 for the electrode formed above, and even if the electrode 21 is formed, there is a problem that the wire is easily broken.
本発明はこのような点に鑑みて創作されたもの
で、GaAsFETの製造において、ゲート電極部の
段差を小にし表面が平坦に形成される方法を提供
することを目的とする。 The present invention was created in view of these points, and an object of the present invention is to provide a method for manufacturing a GaAsFET by reducing the step difference in the gate electrode portion and forming a flat surface.
第１図ａは本発明実施例平面図、同図ｂとｃは
同図ａのＢ−Ｂ線、Ｃ−Ｃ線に沿う断面図、第２
図は第１図のデバイスを作る工程を示す断面図で
ある。
Figure 1a is a plan view of an embodiment of the present invention, Figures b and c are sectional views taken along line B-B and line C-C in Figure a, and Figure 2.
The figure is a cross-sectional view showing the process of making the device of FIG. 1.
本発明の方法においては、従来例工程の第３図
ｄに示す工程が終つた後において、SiO2膜１６
を除去し、従来のSiO2膜１９に変るSiO2膜２２
を形成し、このSiO2膜２２にコンタクトホール
２０を形成するものである。 In the method of the present invention, after the conventional process shown in FIG. 3d is completed, the SiO 2 film 16 is
The SiO 2 film 22 is removed and replaced with the conventional SiO 2 film 19.
is formed, and a contact hole 20 is formed in this SiO 2 film 22.
上記方法においては、従来のSiO2膜１６を除
去した後に、SiO2膜２２を形成するのであるか
ら、SiO2膜１６の5000Åの厚さだけ段差が小に
なり、表面が平坦化されるのである。
In the above method, the SiO 2 film 22 is formed after removing the conventional SiO 2 film 16, so the step is reduced by the 5000 Å thickness of the SiO 2 film 16, and the surface is flattened. be.
以下、図面を参照して本発明実施例を詳細に説
明する。
Embodiments of the present invention will be described in detail below with reference to the drawings.
本発明においては、第３図ａ，ｂ，ｃ，ｄを参
照して説明した従来工程と同じ工程をなす。 In the present invention, the same steps as the conventional steps described with reference to FIGS. 3a, b, c, and d are performed.
次いで、第２図ａに示される如く、SiO2膜１
６を除去する。それには、（CF4＋CHF3）ガスを
用いるドライエツチングによる。 Next, as shown in FIG. 2a, the SiO 2 film 1
Remove 6. This is done by dry etching using (CF 4 +CHF 3 ) gas.
次いで、SiO2を5000Åの厚さにCVDで成長し
てSiO2膜２２を形成し、このSiO2膜２２にコン
タクトホール２０を開口すると、第１図ａに示さ
れる構造が作られ、ゲート電極部の段差は、矢印
で示す如く従来例に比べて5000Å小になつてい
る。 Next, SiO 2 is grown to a thickness of 5000 Å by CVD to form a SiO 2 film 22, and a contact hole 20 is opened in this SiO 2 film 22 to create the structure shown in FIG. As shown by the arrow, the height difference between the parts is 5000 Å smaller than that of the conventional example.
次いで、電極２１を形成して第２図ｂに示され
る如くGaAsFETを完成する。 Next, an electrode 21 is formed to complete the GaAsFET as shown in FIG. 2b.
なお、第１図ｃはソースにオーバレイ電極２３
を設けた例である。 Note that FIG. 1c shows an overlay electrode 23 on the source.
This is an example where .
以上説明してきたように、本発明によれば、
GaAsFETにおいて、ゲート電極部の段差が従来
例に比べ小になり、表面が平坦化されるので、電
極２１の形成が容易になるだけでなく、それの切
断が防止される効果がある。
As explained above, according to the present invention,
In the GaAsFET, the step difference in the gate electrode portion is smaller than in the conventional example, and the surface is flattened, which not only facilitates the formation of the electrode 21 but also prevents it from being cut.
第１図ａは本発明実施例の平面図、同図ｂ，ｃ
は同図ａのＢ−Ｂ線、Ｃ−Ｃ線に沿う断面図、第
２図ａとｂは本発明方法を実施する工程における
半導体装置要部の断面図、第３図ａないしｅは従
来例工程を示す断面図である。
第１図ないし第３図において、１１はGaAs基
板、１２はｎ型層、１３はn+型層、１４はゲー
ト電極、１５は窒化膜、１６はSiO2膜、１７は
ソース電極、１８はドレイン電極、１９はSiO2
膜、２０はコンタクトホール、２１は電極、２２
はSiO2膜、２３はオーバレイ電極、３１，３２，
３３はレジスト膜である。
Figure 1a is a plan view of an embodiment of the present invention, Figures b and c
2A and 2B are sectional views of the main parts of a semiconductor device in the process of carrying out the method of the present invention, and FIGS. It is a sectional view showing an example process. 1 to 3, 11 is a GaAs substrate, 12 is an n-type layer, 13 is an n + type layer, 14 is a gate electrode, 15 is a nitride film, 16 is a SiO 2 film, 17 is a source electrode, and 18 is a Drain electrode, 19 is SiO 2
film, 20 is a contact hole, 21 is an electrode, 22
is a SiO 2 film, 23 is an overlay electrode, 31, 32,
33 is a resist film.
Claims (1)
し、全面に基板保護膜１５とリフトオフスペーサ
となる絶縁膜１６を形成する工程、 全面にレジスト膜３３を形成し、それをパター
ニングしたレジストパターンをマスクに前記絶縁
膜１６と基板保護膜１５をエツチングし、ソー
ス・ドレイン電極用物質を堆積し、リフトオフに
よりソース電極１７とドレイン電極１８を形成す
る工程、 前記絶縁膜１６を除去し、全面に絶縁膜２２を
形成し、絶縁膜２２にコンタクトホール２０を開
口して電極２１を形成することを特徴とする半導
体装置の製造方法。[Claims] 1. A step of forming a gate electrode 14 on a GaAs substrate 11, forming a substrate protective film 15 and an insulating film 16 serving as a lift-off spacer on the entire surface, forming a resist film 33 on the entire surface, and patterning it. The insulating film 16 and the substrate protection film 15 are etched using the prepared resist pattern as a mask, a material for source/drain electrodes is deposited, and a source electrode 17 and a drain electrode 18 are formed by lift-off, and the insulating film 16 is removed. . A method of manufacturing a semiconductor device, which comprises forming an insulating film 22 over the entire surface, and forming contact holes 20 in the insulating film 22 to form electrodes 21.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP78386A JPS62159473A (en) | 1986-01-08 | 1986-01-08 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP78386A JPS62159473A (en) | 1986-01-08 | 1986-01-08 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62159473A JPS62159473A (en) | 1987-07-15 |
| JPH0260213B2 true JPH0260213B2 (en) | 1990-12-14 |
Family
ID=11483294
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP78386A Granted JPS62159473A (en) | 1986-01-08 | 1986-01-08 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62159473A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113421950B (en) * | 2021-06-21 | 2023-04-28 | 安徽华晟新能源科技有限公司 | Method for manufacturing solar cell |
-
1986
- 1986-01-08 JP JP78386A patent/JPS62159473A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62159473A (en) | 1987-07-15 |
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