JPH0653160A - Method of forming self-aligned contact - Google Patents

Method of forming self-aligned contact

Info

Publication number
JPH0653160A
JPH0653160A JP20513192A JP20513192A JPH0653160A JP H0653160 A JPH0653160 A JP H0653160A JP 20513192 A JP20513192 A JP 20513192A JP 20513192 A JP20513192 A JP 20513192A JP H0653160 A JPH0653160 A JP H0653160A
Authority
JP
Japan
Prior art keywords
contact
self
silicon oxide
oxide film
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20513192A
Other languages
Japanese (ja)
Inventor
Hiromitsu Namita
博光 波田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP20513192A priority Critical patent/JPH0653160A/en
Publication of JPH0653160A publication Critical patent/JPH0653160A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To form a self-aligned contact without leaving large steps by using a void formed intentionally in a silicon oxide film instead of using a step. CONSTITUTION:Gate electrode 3 and a cap silicon oxide film 4 are laminated on a silicon substrate 1, and a silicon oxide film 5 is deposited over the substrate so that a void 8 may be formed between the electrodes 3. The silicon oxide film 5, masked with a photoresist 6 having a window 9, is etched to make a contact hole 7 self-aligned with the void. In this manner, a self-aligned contact is formed on a flat surface with no steps remaining at the contact hole. This prevents troubles in subsequent steps such as exposure and etching, thus improving yield.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、コンタクトの形成法に
関し、特にある程度の目合わせずれを許容するセルフア
ラインコンタクト構造の形成方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact, and more particularly to a method for forming a self-aligned contact structure which allows some misalignment.

【0002】[0002]

【従来の技術】セルフアラインコンタクト形成技術とし
て、例えばゲート電極間にコンタクトをセルフアライン
で開口する場合に、図2に示すようなゲート電極の段差
を積極的に利用してコンタクトを開口する方法が従来よ
りよく用いられる。
2. Description of the Related Art As a technique for forming a self-aligned contact, for example, when a contact is self-aligned between gate electrodes, there is a method of actively utilizing the steps of the gate electrode as shown in FIG. Used more often than before.

【0003】つまり、図2(a)に示すように、シリコ
ン基板21上には、シリコン酸化膜22で区画された領
域を有し、このシリコン基板21上に形成したゲート電
極23とキャップシリコン酸化膜24との積層構造をシ
リコン酸化膜25で覆った後、コンタクトのリソグラフ
ィーを行い、図2(b)のように、フォトレジスト26
に開口28を形成する。この際、フォトレジスト26の
開口28の寸法は、実際のコンタクト寸法より大きくて
も、また、多少の目合わせずれがあっても良い。その
後、図2(c)に示すごとく、シリコン酸化膜25のエ
ッチバックを行い、フォトレジストを剥離してゲート電
極23,23間にセルフアラインでコンタクト開口部2
7を形成する。
That is, as shown in FIG. 2A, a silicon substrate 21 has a region partitioned by a silicon oxide film 22, and a gate electrode 23 and a cap silicon oxide formed on the silicon substrate 21. After the laminated structure with the film 24 is covered with the silicon oxide film 25, contact lithography is performed, and as shown in FIG.
An opening 28 is formed in the. At this time, the size of the opening 28 of the photoresist 26 may be larger than the actual contact size, or there may be some misalignment. After that, as shown in FIG. 2C, the silicon oxide film 25 is etched back, the photoresist is removed, and the contact opening 2 is self-aligned between the gate electrodes 23.
Form 7.

【0004】[0004]

【発明が解決しようとする課題】ところが、上述した従
来のセルフアラインコンタクト形成技術では以下に述べ
るような問題点がある。すなわち、上述のセルフアライ
ンコンタクト形成技術は、ゲート電極等の段差を利用し
てセルフアラインコンタクトを形成するものである。し
たがって、段差は、コンタクト形成のために必ず必要で
あるが、段差が大きいために後工程のエッチング,露光
等でエッチング残り,レジスト寸法のバラツキ等の問題
を発生する。
However, the above-described conventional self-aligned contact forming technique has the following problems. That is, the above-described self-aligned contact forming technique forms a self-aligned contact by utilizing the step difference of the gate electrode or the like. Therefore, the step is always necessary for forming the contact, but the step is large, so that there is a problem such as residual etching due to etching in a later step, exposure, etc., and variations in resist size.

【0005】本発明の目的は、このような従来の問題点
を解決し、後工程に大きな段差を残さないセルフアライ
ンコンタクトの形成法を提供することにある。
An object of the present invention is to solve the above conventional problems and provide a method for forming a self-aligned contact that does not leave a large step in a subsequent process.

【0006】[0006]

【課題を解決するための手段】前記目的を達成するた
め、本発明に係るセルフアラインコンタクト形成法にお
いては、配線の形成工程と、絶縁被覆膜成長工程と、コ
ンタクト開口工程とを有し、配線に隣接したコンタクト
領域へコンタクトを形成するセルフアラインコンタクト
形成法であって、配線形成工程は、基板上に配線材料膜
と第1の絶縁膜とを順次成膜し、次いで余分の第1の絶
縁膜及び配線材料膜を除去し、第1の絶縁膜と配線との
積層構造の対を同一の幅でコンタクト形成領域に隣接し
て形成する工程であり、絶縁被覆工程は、前記第1の絶
縁膜と配線との積層構造により生ずる段差部上にオーバ
ハングさせて第2の絶縁膜を成長する工程であり、コン
タクト開口工程は、コンタクト領域の前記第2の絶縁膜
をエッチング除去し、オーバハングの下方に形成された
ボイドに通ずるコンタクト開口を形成する工程である。
In order to achieve the above object, the self-aligned contact forming method according to the present invention includes a wiring forming step, an insulating coating film growing step, and a contact opening step. A self-aligned contact forming method for forming a contact in a contact region adjacent to a wiring, in which the wiring forming step comprises sequentially forming a wiring material film and a first insulating film on a substrate, and then forming an extra first film. This is a step of removing the insulating film and the wiring material film, and forming a pair of a laminated structure of the first insulating film and the wiring adjacent to the contact formation region with the same width. The step of growing the second insulating film by overhanging on the step portion generated by the laminated structure of the insulating film and the wiring, and the contact opening step removes the second insulating film in the contact region by etching. A step of forming a contact opening leading to voids formed below the overhang.

【0007】[0007]

【作用】本発明のセルフアラインコンタクトの形成法に
おいては、段差を利用してコンタクトを形成せず、シリ
コン酸化膜を成長する際に故意にコンタクト形成領域に
ボイドを形成し、このボイドを利用してセルフアライン
コンタクトを形成するものであり、したがって、コンタ
クトの開口の際、段差は不要である。
In the method of forming a self-aligned contact of the present invention, a contact is not formed by utilizing a step, and a void is intentionally formed in the contact formation region when the silicon oxide film is grown, and this void is used. Self-aligned contacts are formed as a result, and therefore no step is required at the time of opening the contact.

【0008】[0008]

【実施例】次に本発明について図面を参照して説明す
る。図1は、本発明の一実施例を工程順に示した図であ
る。同図において、1はシリコン基板、2はシリコン酸
化膜、3はゲート電極,4はキャップシリコン酸化膜、
5はシリコン酸化膜,6はフォトレジスト、7はコンタ
クト開口部、をそれぞれ示す。
The present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an embodiment of the present invention in the order of steps. In the figure, 1 is a silicon substrate, 2 is a silicon oxide film, 3 is a gate electrode, 4 is a cap silicon oxide film,
Reference numeral 5 is a silicon oxide film, 6 is a photoresist, and 7 is a contact opening.

【0009】まず、図1(a)において、シリコンの選
択酸化によりシリコン基板1にシリコン酸化膜2を形成
し、ゲート酸化の工程後、基板全面にポリシリコン膜,
シリコン酸化膜をCVD法によりこの順に堆積する。そ
の後、ゲート電極の形成工程によりシリコン酸化膜,ポ
リシリコン膜のエッチングを行い、シリコン基板1上
に、ゲート電極3と、その上に同一の幅で形成されたキ
ャップシリコン酸化膜4の積層構造を得る。
First, in FIG. 1A, a silicon oxide film 2 is formed on a silicon substrate 1 by selective oxidation of silicon, and after a step of gate oxidation, a polysilicon film is formed on the entire surface of the substrate.
A silicon oxide film is deposited in this order by the CVD method. Then, the silicon oxide film and the polysilicon film are etched in the step of forming the gate electrode to form a laminated structure of the gate electrode 3 on the silicon substrate 1 and the cap silicon oxide film 4 formed on the silicon substrate 1 with the same width. obtain.

【0010】次にイオン注入等により拡散層を形成した
後、プラズマCVD法により図1(b)のようにシリコ
ン酸化膜5を全面に堆積する。プラズマCVD法により
膜堆積を行うと、両ゲート電極3,3間の段差部上に張
り出したオーバーハング形状となり、ゲート電極3,3
間は、酸化膜5によって完全には埋まらず、ボイド8が
発生する。
Next, after forming a diffusion layer by ion implantation or the like, a silicon oxide film 5 is deposited on the entire surface by plasma CVD as shown in FIG. When the film is deposited by the plasma CVD method, an overhang shape protruding on the step portion between the gate electrodes 3 and 3 is formed.
The space is not completely filled with the oxide film 5, and a void 8 is generated.

【0011】次にコンタクトのフォトリソグラフィー工
程により、図1(c)のようにコンタクト形成領域のフ
ォトレジスト6の一部に開口9を形成する。次にコンタ
クト形成領域上のシリコン酸化膜5をエッチングするこ
とにより、コンタクト開口部7を形成する(図1
(d))。
Next, an opening 9 is formed in a part of the photoresist 6 in the contact formation region by a contact photolithography process as shown in FIG. Next, the contact opening 7 is formed by etching the silicon oxide film 5 on the contact formation region (see FIG. 1).
(D)).

【0012】このエッチングの際、コンタクト形成領域
には、ボイド8が存在するので、エッチングすべき膜厚
は、コンタクト深さより薄く、したがって、コンタクト
露光時に目合わせずれを生じてもゲート−コンタクト間
の絶縁が保たれ、コンタクトは、セルフアラインで開口
する。
Since voids 8 exist in the contact formation region during this etching, the film thickness to be etched is smaller than the contact depth. Therefore, even if misalignment occurs during exposure of the contact, the gap between the gate and the contact can be increased. The insulation is maintained and the contacts open in self-alignment.

【0013】[0013]

【発明の効果】以上説明したように本発明によれば、平
坦な表面上でセルフアラインコンタクトを形成でき、ま
た、開口後も大きな段差が残らない。したがって、後工
程の露光,エッチングなどで発生する問題を減少するこ
とができ、したがって、製造の歩留りが向上する等の効
果がある。
As described above, according to the present invention, a self-aligned contact can be formed on a flat surface, and no large step remains after opening. Therefore, it is possible to reduce the problems that occur in the exposure and etching in the subsequent process, and therefore, it is possible to improve the manufacturing yield.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)〜(d)は、本発明の一実施例で用いた
工程手順を示した図である。
1A to 1D are diagrams showing a process procedure used in an embodiment of the present invention.

【図2】(a)〜(c)は、従来のセルフアラインコン
タクト形成法の工程手順を示した図である。
2A to 2C are diagrams showing a process procedure of a conventional self-aligned contact forming method.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 シリコン酸化膜 3 ゲート電極 4 キャップシリコン酸化膜 5 シリコン酸化膜 6 フォトレジスト 7 コンタクト開口部 8 ボイド 9 フォトレジストの開口 1 Silicon Substrate 2 Silicon Oxide Film 3 Gate Electrode 4 Cap Silicon Oxide Film 5 Silicon Oxide Film 6 Photoresist 7 Contact Opening 8 Void 9 Photoresist Opening

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 配線の形成工程と、絶縁被覆膜成長工程
と、コンタクト開口工程とを有し、配線に隣接したコン
タクト領域へコンタクトを形成するセルフアラインコン
タクト形成法であって、 配線形成工程は、基板上に配線材料膜と第1の絶縁膜と
を順次成膜し、次いで余分の第1の絶縁膜及び配線材料
膜を除去し、第1の絶縁膜と配線との積層構造の対を同
一の幅でコンタクト形成領域に隣接して形成する工程で
あり、 絶縁被覆工程は、前記第1の絶縁膜と配線との積層構造
により生ずる段差部上にオーバハングさせて第2の絶縁
膜を成長する工程であり、 コンタクト開口工程は、コンタクト領域の前記第2の絶
縁膜をエッチング除去し、オーバハングの下方に形成さ
れたボイドに通ずるコンタクト開口を形成する工程であ
ることを特徴とするセルフアラインコンタクト形成法。
1. A self-aligned contact forming method for forming a contact in a contact region adjacent to a wiring, which comprises a wiring forming step, an insulating coating film growing step, and a contact opening step. The wiring material film and the first insulating film are sequentially formed on the substrate, and then the excess first insulating film and the wiring material film are removed, and a pair of the laminated structure of the first insulating film and the wiring is formed. Is formed adjacent to the contact formation region with the same width, and the insulating coating step overhangs the second insulating film by overhanging on the step portion generated by the laminated structure of the first insulating film and the wiring. The contact opening step is a step of growing, and the contact opening step is a step of etching and removing the second insulating film in the contact region to form a contact opening communicating with a void formed below the overhang. Self-aligned contact formation method.
JP20513192A 1992-07-31 1992-07-31 Method of forming self-aligned contact Pending JPH0653160A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20513192A JPH0653160A (en) 1992-07-31 1992-07-31 Method of forming self-aligned contact

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20513192A JPH0653160A (en) 1992-07-31 1992-07-31 Method of forming self-aligned contact

Publications (1)

Publication Number Publication Date
JPH0653160A true JPH0653160A (en) 1994-02-25

Family

ID=16501951

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20513192A Pending JPH0653160A (en) 1992-07-31 1992-07-31 Method of forming self-aligned contact

Country Status (1)

Country Link
JP (1) JPH0653160A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100358122B1 (en) * 2000-12-14 2002-10-25 주식회사 하이닉스반도체 A method for forming self-aligned contact hole in semiconductor device
KR100379507B1 (en) * 2000-07-20 2003-04-10 주식회사 하이닉스반도체 Method for Fabricating of Semiconductor Device
KR20030087744A (en) * 2002-05-09 2003-11-15 삼성전자주식회사 Method for forming contact hole in integrated circuit
US6703314B2 (en) * 2001-12-14 2004-03-09 Hynix Semiconductor Inc. Method for fabricating semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100379507B1 (en) * 2000-07-20 2003-04-10 주식회사 하이닉스반도체 Method for Fabricating of Semiconductor Device
KR100358122B1 (en) * 2000-12-14 2002-10-25 주식회사 하이닉스반도체 A method for forming self-aligned contact hole in semiconductor device
US6703314B2 (en) * 2001-12-14 2004-03-09 Hynix Semiconductor Inc. Method for fabricating semiconductor device
KR100492898B1 (en) * 2001-12-14 2005-06-03 주식회사 하이닉스반도체 Method for fabricating semiconductor device
KR20030087744A (en) * 2002-05-09 2003-11-15 삼성전자주식회사 Method for forming contact hole in integrated circuit

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